CN102738024A - 半导体封装及其引线框 - Google Patents

半导体封装及其引线框 Download PDF

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CN102738024A
CN102738024A CN2011100821175A CN201110082117A CN102738024A CN 102738024 A CN102738024 A CN 102738024A CN 2011100821175 A CN2011100821175 A CN 2011100821175A CN 201110082117 A CN201110082117 A CN 201110082117A CN 102738024 A CN102738024 A CN 102738024A
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tube core
lead
chassis
lead finger
finger
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刘鹏
贺青春
吴萍
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NXP USA Inc
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Freescale Semiconductor Inc
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Abstract

本发明涉及一种半导体封装及其引线框。利用第一和第二引线框装配半导体封装。第一引线框包括管芯底盘，第二引线框包括引线指。当第一和第二引线框配合时，引线指围绕管芯底盘。部分地蚀刻管芯底盘的侧表面以在管芯底盘上形成扩展的管芯连附表面，以及部分地蚀刻每一个引线指的部分顶表面以形成与所述管芯底盘的蚀刻侧表面互补的引线指表面。半导体管芯连附到扩展的管芯连附表面，以及所述半导体管芯的接合衬垫电气地连接到引线指。封装材料覆盖管芯、电连接和管芯底盘的顶表面和引线指。

Description

半导体封装及其引线框
技术领域
本发明通常涉及半导体器件封装，以及更具体地涉及用于方形扁平无引线(QFN)封装的引线框设计。
背景技术
当前，广泛地使用了半导体器件。随着这些器件变得更小并且变得更具功能性，期望具有能够容纳具有增强功能的更大的管芯的器件封装。
一种封装半导体管芯的方法涉及使用引线框，所述引线框具有管芯衬垫，在管芯衬垫上安装一个或更多个管芯。引线框还包括从封装向外突出的电引线，所述电引线被用于允许从一个或更多个管芯或者其他外部设备接收电信号以及从一个或更多个管芯将电信号传输到印刷电路板(PCB)或者其他外部设备。
另一类型的基于引线框的封装是无引线封装，例如双边无引线(DFN)和方形扁平无引线(QFN)封装。在上述封装中，引线不从封装向外突出，而是与封装的底部或者侧面(或者封装的底部和侧面二者)齐平。
图1示出了现有的无引线半导体封装10的剖视图，其具有半导体管芯12、具有管芯底盘16的引线框14和围绕管芯底盘16的引线指18。半导体管芯12的接合衬垫利用接合线20电气地耦合到引线指18。模塑化合物包封半导体管芯12和接合线20以形成半导体封装10。
然而，如图所示，能够被并入封装10的半导体管芯12的尺寸受到了引线框14的管芯底盘16的尺寸的限制。因此，可能需要更大的引线框来封装大的半导体管芯，由此导致了尺寸、设计和成本的损失。此外，由于不能使用更小尺寸的互连结构，因此使用更大的引线框可能导致额外的定制要求。
因此，需要存在一种在不增加总体封装尺寸的情况下易于封装大半导体管芯的半导体封装技术。
发明内容
在一个实施例中，本发明提供了一种封装半导体管芯的方法。所述方法包括如下步骤：提供引线框结构，所述引线框结构具有包括管芯底盘的第一引线框和包括引线指的第二引线框。第一引线框和第二引线框优选地包括在装配工艺期间分离的引线框面板。所述管芯底盘的厚度大于引线指的厚度。所述管芯底盘的侧表面被蚀刻一半以形成扩展的管芯连附表面，同时每一个引线指的顶表面被蚀刻一半以与扩展的管芯连附表面互补的引线指表面。管芯底盘和引线指被布置为使得引线指容纳扩展的管芯连附表面。半导体管芯连附到所述扩展的管芯连附表面，并且所述半导体管芯的接合衬垫电气地连接到所述引线框的所述引线指。封装材料覆盖引线框、管芯的顶表面和二者之间的电连接。
在另一实施例中，本发明提供了一种用于封装半导体集成电路的引线框结构。所述引线框结构包括形成在第一引线框上的管芯底盘和形成在分离的第二引线框上的引线指。所述第一和第二引线框在装配工艺期间配合，以使得引线指围绕管芯底盘。每一个引线指的部分顶表面被部分蚀刻以形成与被蚀刻的管芯底盘表面互补的引线指表面，用于容纳所述管芯底盘的扩展的管芯连附表面。
附图说明
通过举例的方式示出了本发明，并且本发明不限于附图，其中相同的参考标号表明相同的部件。为了简单和清楚起见而示出了附图中的部件，其并不一定是按比例描绘的。例如，为了清晰起见，各层和区域的厚度可能被放大了。
图1示出了现有的无引线半导体封装的截面侧视图；
图2示出了根据本发明一个实施例的封装的半导体器件的截面侧视图；
图3示出了图2的封装半导体器件的底部平面图；
图4A-4E示出了根据本发明实施例的装配半导体器件的步骤，其中图4A示出了截面侧视图，其示出了引线框的被部分蚀刻的引线指；
图4B示出了图4A的被部分蚀刻的引线指和被部分蚀刻的管芯底盘；
图4C示出了利用管芯连附粘结剂将半导体管芯连附到管芯底盘的扩展的管芯连附表面的步骤；
图4D示出了将半导体管芯电气地连接到引线框的引线的步骤；以及
图4E示出了将封装材料分配到引线框的顶表面上的步骤。
具体实施方式
此处公开了本发明的详细的说明性实施例。然而，此处公开的具体结构和功能的细节仅仅是示例性的，出于描述本发明的实例实施例的目的。本发明可以以多个可选形式实现，而不应该被理解为仅仅局限于此处阐述的实施例。
现在参考图2，示出了根据本发明实施例的封装的半导体器件30的剖视图。半导体器件30包括具有管芯底盘34的第一引线框32和具有多个引线指36的第二引线框35。第一和第二引线框32、35配合以使得引线指36围绕管芯底盘34。引线框32和35可以由易于成型的导电材料形成，例如导电金属，如铝或者铜或者铜合金。导电金属可以是裸露的、部分被镀的或者镀有其它金属或者合金(例如铁/镍合金、银等等)。进一步，在装配工艺期间，可以分离地形成管芯底盘34和引线指36，管芯底盘34被配置在各引线指之间。在本优选实施例中，管芯底盘34比引线指36厚。
在图2所示的示例性实施例中，管芯底盘34的侧表面38和40以及每一个引线指36的顶表面42和44被部分地蚀刻，从而形成由参考数字46、48和50、52表示的互补表面，这形成了管芯底盘34上的扩展的管芯连附表面54。
在本发明的一个示例性实施例中，管芯底盘34的侧表面38和40以及引线指36的部分顶表面42和44被蚀刻一半，从而形成扩展的管芯连附表面54和互补的引线指。应当注意，与图1所示的现有半导体封装10相比，部分蚀刻管芯底盘34和引线指36所形成的扩展的管芯连附表面54有利于将较大的管芯并入封装30内。
半导体管芯56连附到扩展的管芯连附表面54并且电气地耦合到引线指36。半导体管芯56可以是例如闪存芯片(NOR/NAND)、控制器芯片、微处理器、ASIC等等。可以利用管芯连附粘结剂(例如环氧树脂或者合成橡胶)将半导体管芯56连附到扩展的管芯连附表面54。然而，也可以使用其他适当的粘结材料。由于半导体管芯56和管芯连附粘结剂在本领域中是公知的，因此对于全面理解本发明来说，并不需要进一步说明和可能的可选实施例。
在本发明的该示例性实施例中，利用线58将半导体管芯56的接合衬垫电气地耦合到引线框32的引线指36。利用已知的线接合技术和线接合设备，线58可以被接合到半导体管芯56的接合衬垫以及可以被接合到引线指36上的相应接触焊盘。如在现有技术中已知的，线58由导电材料(例如金或者铝)形成，以及可以是裸露的或者被涂覆的。
封装材料60被沉积到半导体管芯56的顶表面、引线指36上以及被沉积在引线指36和管芯底盘34的互补表面46、48和50、52之间的空隙62、64内。封装材料60还覆盖线58。如在现有技术中已知的，封装材料60可以包括塑料或者环氧树脂模塑化合物。图2的封装半导体器件的实例结构被用于扁平无引线封装(DFN或者QFN)，尽管带引线的器件也落入本发明的范畴。
图3示出了半导体器件30的底部平面图。如图所示，该半导体器件是QFN型封装。图中示出了管芯底盘34的暴露的底表面和引线指36的暴露部分。管芯底盘34和引线指36的互补的蚀刻侧表面使得能够在具有与图1的现有器件10相同总尺寸的封装内容纳更大尺寸的管芯。例如，在一个实施例中，管芯底盘尺寸增加20％，这允许管芯尺寸的相应增加。当然，如本领域技术人员将会理解的，增加的管芯尺寸还将取决于整体的封装要求。
图4A-4E示出了用于装配半导体器件30的各个步骤。现在参考图4A，示出了第二引线框35的部分蚀刻的引线指36的截面侧视图。尽管在所述图中仅仅示出了其中一个第二引线框35，然而应当理解，可以从引线框阵列或者面板形成引线框35，由此使得可以同时装配多个器件。
如图所示，每一个引线指36的部分顶表面42和44被部分蚀刻以形成引线指表面48和52。蚀刻部分位于引线指的邻近第二引线框35内中央孔的端部。引线指36的蚀刻部分的蚀刻深度可以为引线指总厚度的大约二分之一。例如，如果引线指36为5mil厚，则引线指的蚀刻部分的厚度将为大约2.5-3.0mil。在所示的实施例中，第二引线框35连附到带80，带80例如是高温粘结带，而第二引线框35的底表面82连附到粘结带80。(如此处使用的，1.0mil大约为0.0254毫米)。
图4B示出了布置在引线指36内的第一引线框32的管芯底盘34，由此使得引线指36包围管芯底盘34。类似于引线指36，管芯底盘34的底表面84连附到带80。尽管仅仅示出了一个管芯底盘34，然而管芯底盘34可以被形成为与引线指组的互补面板配合的管芯底盘面板或阵列，由此使得可以同时形成多个器件。如图所示，管芯底盘34的侧表面38和40被部分地蚀刻以形成管芯底盘34上的扩展的管芯连附表面54。应当注意，引线指表面48和52对于被蚀刻的管芯底盘表面46和50是互补的。
在所示的实施例中，管芯底盘34的厚度86大于引线指36的厚度88。在一个示例性实施例中，管芯底盘34的未蚀刻部分的厚度86大约为8mm，以及引线指38的未蚀刻部分的厚度88大约为5mil；而管芯底盘34的蚀刻部分的厚度大约为4mil以及引线指36的蚀刻部分的厚度大约为2.5mil。进一步的，管芯底盘34与引线指36隔开优选大约1.5-2.0mil。进一步的，管芯底盘34和引线指36之间的空隙62、64或者空间为大约2.0-2.5mil。
如图所示，互补的引线指表面48和52容纳扩展的管芯连附表面54。可以利用已知的化学蚀刻方法来执行管芯底盘34和引线指36的选择性蚀刻。
图4C示出了将半导体管芯56连附到扩展的管芯连附表面54的步骤。利用管芯连附粘结剂(例如管芯接合环氧树脂)将半导体管芯56连附到扩展的管芯连附表面54。可以利用拾取放置工具90将半导体管芯56配置在管芯连附表面54上。
图4D示出了将半导体管芯56电气地连接到第一引线框32的步骤。在本发明的该示例性实施例中，通过线58利用公知的线接合方法和已知的线接合设备，将半导体管芯56的接合衬垫电气地连接到引线指36的相应衬垫。如图所示，在优选实施例中，线58接合到引线指36的未蚀刻部分。
图4E示出了将封装材料60(例如环氧树脂)分配到引线框32的顶表面上的步骤。封装材料60覆盖半导体管芯56、引线指36和线58。封装材料60填充管芯底盘34和引线指36的互补表面46、48和50、52之间的空隙62和64。可以利用已知的封装引线指36、管芯54和线58，如在现有技术中已知的，所述已知的方法例如是利用现有的分配机器的喷嘴或者在塑模框中以及通过注入塑模。可选的可以用于封装材料60的已知材料包括填充硅石的树脂、陶瓷、无卤化物的材料等等或其组合。通常以液态施加封装材料并随后固化直至其转变为固态。
随后，通过去除所述带80形成图2所示的半导体器件30，并且如果同时形成多个器件，则例如通过切单使得各器件彼此分离。
尽管上述的装配工艺仅仅示出了一个管芯56，然而本领域技术人员理解，可以使用该方法形成在管芯底盘34上安装多于一个管芯的层叠管芯封装或者存在多于一个管芯底盘34的多管芯封装。
如上所述，本发明允许在不改变封装总体尺寸的情况下封装大的半导体管芯。通过部分蚀刻管芯底盘和引线框的引线指以形成在管芯底盘上提供扩展的管芯连附表面的互补表面，由此形成了扩展的管芯连附表面。因此，可以在用于相对较小的管芯的相同封装设计内容纳更大的管芯。有益地，更大的管芯尺寸促进了在不需要改变封装设计的情况下的更多的器件功能。
尽管此处参考特定实施例描述了本发明，但是在不背离如以下权利要求书所阐明的本发明的保护范围的情况下，可以作出各种改型和改变。

Claims (10)

1.一种封装半导体管芯的方法，包括如下步骤：
提供引线框结构，所述引线框结构包括具有管芯底盘的第一引线框和具有多个引线指的第二引线框，其中所述管芯底盘的侧表面被部分地蚀刻以在所述管芯底盘上形成扩展的管芯连附表面，以及部分地蚀刻每一个引线指的一部分顶表面以形成相应的互补引线指表面；
布置所述第一和第二引线框，以使得所述互补的引线指容纳所述扩展的管芯连附表面；
将半导体管芯连附到所述扩展的管芯连附表面；
将所述半导体管芯的接合衬垫电气地连接到所述引线框的所述引线指；以及
将封装材料分配到所述第一和第二引线框的顶表面上，由此使得所述封装材料覆盖所述半导体管芯、所述引线指和二者之间的电连接。
2.如权利要求1所述的封装半导体管芯的方法，其中所述管芯底盘的厚度大于每一个引线指的厚度，以及其中所述管芯底盘的未蚀刻部分的厚度为所述管芯底盘的被蚀刻部分的厚度的大约两倍，以及每一个引线指的未蚀刻部分的厚度为所述引线指的被蚀刻部分的厚度的大约两倍。
3.如权利要求1所述的封装半导体管芯的方法，其中所述电气连接步骤包括利用线接合方法使用线将所述半导体管芯的接合衬垫连接到所述引线指，以及所述线被连附到所述引线指的未蚀刻部分。
4.如权利要求1所述的封装半导体管芯的方法，进一步包括在所述管芯连附步骤之前将所述第一和第二引线框的底表面连附到带材料，以及在所述封装步骤之后去除所述带材料。
5.一种根据权利要求1所述的方法封装的半导体器件。
6.一种封装的半导体器件，包括：
管芯底盘；
围绕所述管芯底盘的多个引线指，其中部分地蚀刻所述管芯底盘的侧表面和每一个引线指的部分顶表面，以形成允许所述管芯底盘上的扩展的管芯连附表面的互补表面；
半导体管芯，连附到所述管芯底盘的扩展的管芯连附表面以及电气地耦合到所述引线指；以及
封装材料，其覆盖所述管芯、引线指并且填充所述被蚀刻的管芯底盘和所述引线指之间的空隙。
7.如权利要求6所述的封装的半导体器件，其中所述管芯底盘的厚度大于所述引线指的厚度，所述管芯底盘的侧表面和每一个引线指的部分顶表面被蚀刻一半，以形成扩展的管芯连附表面和互补的引线指。
8.如权利要求6所述的封装的半导体器件，其中利用接合线将所述半导体管芯的接合衬垫电气地耦合到所述引线指中的相应引线指。
9.一种用于封装半导体集成电路的引线框结构，所述引线框结构包括：
第一引线框，包括管芯底盘，其中所述管芯底盘的侧表面被部分地蚀刻以形成扩展的管芯连附表面；以及
第二引线框，包括多个引线指，其中每一个引线指的一部分顶表面在一端处被部分地蚀刻，
其中在所述第一和第二引线框配合时，所述第二引线框的引线指围绕所述第一引线框的所述管芯底盘，并且所述管芯底盘的被蚀刻侧面与所述引线指的被蚀刻顶表面处于互补布置，用于容纳所述管芯底盘的扩展的管芯连附表面。
10.如权利要求9所述的引线框结构，其中所述第一引线框包括多个管芯底盘，以及所述第二引线框包括相应的多组引线指。
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RJ01 Rejection of invention patent application after publication