JP5266156B2 - 差動増幅器 - Google Patents
差動増幅器 Download PDFInfo
- Publication number
- JP5266156B2 JP5266156B2 JP2009178960A JP2009178960A JP5266156B2 JP 5266156 B2 JP5266156 B2 JP 5266156B2 JP 2009178960 A JP2009178960 A JP 2009178960A JP 2009178960 A JP2009178960 A JP 2009178960A JP 5266156 B2 JP5266156 B2 JP 5266156B2
- Authority
- JP
- Japan
- Prior art keywords
- differential amplifier
- terminal
- input
- gate
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45318—Indexing scheme relating to differential amplifiers the AAC comprising a cross coupling circuit, e.g. two extra transistors cross coupled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45394—Indexing scheme relating to differential amplifiers the AAC of the dif amp comprising FETs whose sources are not coupled, i.e. the AAC being a pseudo-differential amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45396—Indexing scheme relating to differential amplifiers the AAC comprising one or more switches
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Description
MP101〜MP104、MP110、MP210 PMOSトランジスタ
MN101〜MN104、MN110、MN210 NMOSトランジスタ
C301〜C304 容量素子
IT、IB 入力端子
OT、OB 出力端子
Claims (1)
- それぞれが第1の電源端子と第2の電源端子間に接続され、差動出力信号の一方を出力する第1の電流経路と、前記差動出力信号の他方を出力する第2の電流経路とを備え、
前記第1の電流経路は、
前記第1の電源端子と前記差動信号のうち一方を出力する第1の出力端子との間に接続され、制御端子に差動入力信号の一方が入力される第1のトランジスタと、
前記第2の電源端子と前記第1の出力端子との間に接続され、制御端子に前記差動入力信号の他方が入力される第2のトランジスタと、
前記第1の電源端子と前記第1のトランジスタとの間に接続される第1のスイッチ回路と、を有し、
前記第2の電流経路は、
前記第2の電源端子と前記差動信号のうち他方を出力する第2の出力端子との間に接続され、制御端子に差動入力信号の一方が入力される第3のトランジスタと、
前記第1の電源端子と前記第2の出力端子との間に接続され、制御端子に前記差動入力信号の他方が入力される第4のトランジスタと、
前記第2の電源端子と前記第3のトランジスタとの間に接続される第2のスイッチ回路と、を有し、
前記第1、第2のスイッチ回路は、制御信号により駆動状態が制御される
差動増幅器。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009178960A JP5266156B2 (ja) | 2009-07-31 | 2009-07-31 | 差動増幅器 |
US12/801,304 US8125274B2 (en) | 2009-07-31 | 2010-06-02 | Differential amplifier |
TW099117760A TW201106613A (en) | 2009-07-31 | 2010-06-02 | Differential amplifier |
US13/244,467 US8384480B2 (en) | 2009-07-31 | 2011-09-24 | Differential amplifier |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009178960A JP5266156B2 (ja) | 2009-07-31 | 2009-07-31 | 差動増幅器 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2011035597A JP2011035597A (ja) | 2011-02-17 |
JP2011035597A5 JP2011035597A5 (ja) | 2012-04-05 |
JP5266156B2 true JP5266156B2 (ja) | 2013-08-21 |
Family
ID=43526424
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009178960A Active JP5266156B2 (ja) | 2009-07-31 | 2009-07-31 | 差動増幅器 |
Country Status (3)
Country | Link |
---|---|
US (2) | US8125274B2 (ja) |
JP (1) | JP5266156B2 (ja) |
TW (1) | TW201106613A (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9166638B2 (en) * | 2014-02-14 | 2015-10-20 | Rafael Microelectronics, Inc. | Integrated circuit chip for receiver collecting signals from satellites |
GB2548070B (en) * | 2014-12-19 | 2020-12-16 | Intel Ip Corp | Stacked semiconductor device package with improved interconnect bandwidth |
CN114079449B (zh) * | 2020-08-18 | 2024-08-02 | 瑞昱半导体股份有限公司 | 信号输出装置及方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2690060B2 (ja) | 1989-08-29 | 1997-12-10 | 富士通株式会社 | 半導体回路 |
JP2713182B2 (ja) * | 1994-09-26 | 1998-02-16 | 日本電気株式会社 | レシーバ装置 |
JP2773692B2 (ja) * | 1995-07-28 | 1998-07-09 | 日本電気株式会社 | 入力バッファ回路 |
US6980055B2 (en) * | 2003-08-11 | 2005-12-27 | Texas Instruments Incorporated | CMOS differential buffer circuit |
JP4230881B2 (ja) * | 2003-10-23 | 2009-02-25 | 富士通マイクロエレクトロニクス株式会社 | 半導体集積回路、及びレベル変換回路 |
WO2006117860A1 (ja) * | 2005-04-28 | 2006-11-09 | Thine Electronics, Inc. | 差動駆動回路およびそれを内蔵する電子機器 |
-
2009
- 2009-07-31 JP JP2009178960A patent/JP5266156B2/ja active Active
-
2010
- 2010-06-02 TW TW099117760A patent/TW201106613A/zh unknown
- 2010-06-02 US US12/801,304 patent/US8125274B2/en active Active
-
2011
- 2011-09-24 US US13/244,467 patent/US8384480B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US8384480B2 (en) | 2013-02-26 |
JP2011035597A (ja) | 2011-02-17 |
US20120126894A1 (en) | 2012-05-24 |
US20110025416A1 (en) | 2011-02-03 |
TW201106613A (en) | 2011-02-16 |
US8125274B2 (en) | 2012-02-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6336831B2 (ja) | インタフェース回路、それを用いた半導体集積回路 | |
JP6643157B2 (ja) | 半導体装置 | |
JP5547451B2 (ja) | パワーオンリセット回路 | |
JP3657243B2 (ja) | レベルシフタ、半導体集積回路及び情報処理システム | |
JP2011096950A (ja) | 半導体装置、センスアンプ回路、半導体装置の制御方法及びセンスアンプ回路の制御方法 | |
JP3625881B2 (ja) | バスシステム及びバスセンスアンプ | |
JP2011120158A (ja) | 半導体装置及び電源スイッチ回路 | |
JP4920398B2 (ja) | 電圧発生回路 | |
KR20180028005A (ko) | 레벨 시프트 회로 및 반도체 장치 | |
JP5266156B2 (ja) | 差動増幅器 | |
US8766697B2 (en) | Level shifting circuit with adaptive feedback | |
JP5421075B2 (ja) | 入力回路 | |
JP2007067709A (ja) | 比較回路および半導体装置 | |
US7859305B2 (en) | Input/output circuit | |
JP4774287B2 (ja) | 出力回路 | |
US7598791B2 (en) | Semiconductor integrated apparatus using two or more types of power supplies | |
JP5133102B2 (ja) | 半導体集積回路 | |
JP6540290B2 (ja) | レベルコンバータ回路 | |
JP3935266B2 (ja) | 電圧検知回路 | |
JP4744909B2 (ja) | ヒステリシスコンパレータ | |
JP4884942B2 (ja) | 発振回路 | |
JP2008017566A (ja) | 電源発生回路 | |
JP5598377B2 (ja) | 出力回路 | |
JP2010219486A (ja) | 中間電位発生回路 | |
JP2010288004A (ja) | 駆動回路 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120217 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20120217 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130417 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130423 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130502 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5266156 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |