JP4171492B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP4171492B2 JP4171492B2 JP2006036929A JP2006036929A JP4171492B2 JP 4171492 B2 JP4171492 B2 JP 4171492B2 JP 2006036929 A JP2006036929 A JP 2006036929A JP 2006036929 A JP2006036929 A JP 2006036929A JP 4171492 B2 JP4171492 B2 JP 4171492B2
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- wiring
- electrode
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- bumps
- conductor
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- 239000004065 semiconductor Substances 0.000 title claims description 79
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000004020 conductor Substances 0.000 claims description 59
- 239000000758 substrate Substances 0.000 claims description 49
- 238000000034 method Methods 0.000 claims description 13
- 230000001681 protective effect Effects 0.000 claims description 12
- 239000010410 layer Substances 0.000 claims description 5
- 239000011241 protective layer Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 description 12
- 230000006378 damage Effects 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 7
- 238000007689 inspection Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000007747 plating Methods 0.000 description 7
- 239000011347 resin Substances 0.000 description 7
- 229920005989 resin Polymers 0.000 description 7
- 238000007789 sealing Methods 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910007637 SnAg Inorganic materials 0.000 description 1
- 229910008433 SnCU Inorganic materials 0.000 description 1
- 229910007116 SnPb Inorganic materials 0.000 description 1
- 229910005728 SnZn Inorganic materials 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
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Description
図1は、本発明の第1の実施形態における半導体装置の断面図である。なお、従来例と同一の要素には同一符号を付して、説明の繰り返しを省略する。
図5は、本発明の第2の実施形態における半導体装置の断面図である。図1の実施形態と同様の要素については、同一符号を付して、説明の繰り返しを省略する。
2、22 半導体チップ
3、23 封止樹脂
4、24 フィルム基材
5、25 導体配線
6、12、14、16a〜16d 配線バンプ
7、27 電極
8、13、15 電極バンプ
9 保護膜
10 接合ツール
11 検査カメラ
26 バンプ
28 フォトレジスト
28a 長方形パターン
29 露光マスク
29a 光透過領域
Claims (3)
- 複数本の導体配線の各々に設けられた配線バンプを有するテープキャリア基板と、
前記テープキャリア基板上に搭載された半導体素子とを備え、
前記半導体素子の電極が前記配線バンプを介して前記導体配線と接続されている半導体装置において、
前記導体配線の幅は前記電極の幅よりも小さく、
前記半導体チップの前記電極上に、前記配線バンプより硬度が高く、かつサイズが小さい電極バンプが形成され、前記配線バンプと前記電極バンプの接合を介して前記半導体素子の電極が前記導体配線と接続され、
前記電極バンプは前記導体配線に当接することなく前記配線バンプに埋没し、前記電極バンプの前記配線バンプに埋没した部分の高さは、前記配線バンプが設けられた部分における前記導体配線の厚みよりも低く、
かつ前記配線バンプは前記電極または前記電極上の保護膜に接触する構造であり、前記配線バンプの前記保護膜に接触する領域は、前記電極の周縁に形成された前記保護膜の段差より内側に位置することを特徴とする半導体装置。 - 前記電極バンプは、Ni層及びAu層からなる請求項1に記載の半導体装置。
- 複数本の導体配線の各々に設けられた配線バンプを有するテープキャリア基板上に、半導体チップを搭載し、前記半導体チップの電極上に形成された電極バンプと前記配線バンプを接合することにより、前記半導体素子の前記電極と前記導体配線とを接続する半導体装置の製造方法において、
前記導体配線の幅を前記電極の幅よりも小さく形成して、前記電極バンプと前記配線バンプを形成し、
前記電極バンプと前記配線バンプが対向するように前記半導体チップと前記テープキャリア基板の位置合わせを行い、
前記電極バンプと前記配線バンプを接合し、それにより、前記電極バンプを前記導体配線に当接しないように前記配線バンプに埋没させ、前記電極バンプの前記配線バンプに埋没した部分の高さを、前記配線バンプが設けられた部分における前記導体配線の厚みよりも低くするとともに、前記電極または前記電極上の保護膜に前記配線バンプを接触させ、前記配線バンプの前記保護膜に接触する領域を、前記電極の周縁に形成された前記保護膜の段差より内側に位置させることを特徴とする半導体装置の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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JP2006036929A JP4171492B2 (ja) | 2005-04-22 | 2006-02-14 | 半導体装置およびその製造方法 |
TW095113624A TW200723423A (en) | 2005-04-22 | 2006-04-17 | Semiconductor device and method for producing the same |
US11/405,060 US7382050B2 (en) | 2005-04-22 | 2006-04-17 | Semiconductor device and method for producing the same |
KR1020060036240A KR20060111408A (ko) | 2005-04-22 | 2006-04-21 | 반도체 장치 및 그 제조방법 |
US12/075,359 US7772697B2 (en) | 2005-04-22 | 2008-03-11 | Semiconductor device and method for producing the same |
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JP2005124346 | 2005-04-22 | ||
JP2006036929A JP4171492B2 (ja) | 2005-04-22 | 2006-02-14 | 半導体装置およびその製造方法 |
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US (2) | US7382050B2 (ja) |
JP (1) | JP4171492B2 (ja) |
KR (1) | KR20060111408A (ja) |
TW (1) | TW200723423A (ja) |
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JP4728782B2 (ja) * | 2005-11-15 | 2011-07-20 | パナソニック株式会社 | 半導体装置およびその製造方法 |
JP2007227557A (ja) * | 2006-02-22 | 2007-09-06 | Nec Electronics Corp | 半導体実装体及びその製造方法 |
US8409979B2 (en) | 2011-05-31 | 2013-04-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties |
TW201432826A (zh) * | 2013-02-01 | 2014-08-16 | Chipbond Technology Corp | 半導體封裝製程及其結構 |
TWI514530B (zh) * | 2013-08-28 | 2015-12-21 | Via Tech Inc | 線路基板、半導體封裝結構及線路基板製程 |
JP2016162985A (ja) * | 2015-03-05 | 2016-09-05 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
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US5929521A (en) * | 1997-03-26 | 1999-07-27 | Micron Technology, Inc. | Projected contact structure for bumped semiconductor device and resulting articles and assemblies |
JPH11307719A (ja) * | 1998-04-20 | 1999-11-05 | Mitsubishi Electric Corp | 半導体装置 |
JP3195590B2 (ja) * | 1999-04-27 | 2001-08-06 | 日東電工株式会社 | フレキシブル配線板 |
JP2001313314A (ja) * | 2000-04-28 | 2001-11-09 | Sony Corp | バンプを用いた半導体装置、その製造方法、および、バンプの形成方法 |
JP2002043376A (ja) | 2000-07-19 | 2002-02-08 | Shinkawa Ltd | 電子部品の検査方法および電子部品組立装置 |
JP2003031613A (ja) | 2001-07-12 | 2003-01-31 | Matsushita Electric Works Ltd | フリップチップ実装体及びフリップチップ実装方法 |
JP2003234433A (ja) * | 2001-10-01 | 2003-08-22 | Matsushita Electric Ind Co Ltd | 半導体装置、半導体装置の実装方法、ならびに実装体およびその製造方法 |
JP2003168822A (ja) * | 2001-11-30 | 2003-06-13 | Shin Etsu Handotai Co Ltd | 発光素子及びその製造方法 |
JP3565835B1 (ja) | 2003-04-28 | 2004-09-15 | 松下電器産業株式会社 | 配線基板およびその製造方法ならびに半導体装置およびその製造方法 |
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2006
- 2006-02-14 JP JP2006036929A patent/JP4171492B2/ja active Active
- 2006-04-17 US US11/405,060 patent/US7382050B2/en active Active
- 2006-04-17 TW TW095113624A patent/TW200723423A/zh unknown
- 2006-04-21 KR KR1020060036240A patent/KR20060111408A/ko not_active Application Discontinuation
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US20060237841A1 (en) | 2006-10-26 |
US7772697B2 (en) | 2010-08-10 |
US7382050B2 (en) | 2008-06-03 |
US20080164608A1 (en) | 2008-07-10 |
JP2006324635A (ja) | 2006-11-30 |
KR20060111408A (ko) | 2006-10-27 |
TW200723423A (en) | 2007-06-16 |
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