CN103227163A - 最小化封装件缺陷的凸块结构设计 - Google Patents

最小化封装件缺陷的凸块结构设计 Download PDF

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CN103227163A
CN103227163A CN2012102450691A CN201210245069A CN103227163A CN 103227163 A CN103227163 A CN 103227163A CN 2012102450691 A CN2012102450691 A CN 2012102450691A CN 201210245069 A CN201210245069 A CN 201210245069A CN 103227163 A CN103227163 A CN 103227163A
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chip package
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CN103227163B (zh
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林俊成
黄震麟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

一种形成凸块结构的机制，能够形成芯片和衬底之间的凸块结构，以消除或减小焊料短路、助焊剂残留物及底部填充物空隙的风险。通过接合凸块结构中的铜柱的总高度除以接合凸块结构的间隔来定义α比率，可以建立α比率的下限以避免短路。也可以建立芯片封装件的间隔的下限以避免助焊剂残留物和底部填充物空隙形成。而且，铜柱凸块的纵横比具有下限，以避免间隔不足；以及上限，由于制造工艺限制。通过遵循适当的凸块设计和工艺准则，芯片封装件的产量和可靠性可能增加。本发明还提供了最小化封装件缺陷的凸块结构设计。

Description

最小化封装件缺陷的凸块结构设计
技术领域
本发明一般地涉及半导体技术领域，更具体地来说，涉及芯片封装件及其形成方法。
背景技术
现代电路的制造通常涉及许多工艺操作。首先在半导体晶圆上方制造集成电路，该半导体晶圆包含多个复制的半导体芯片，每一个半导体芯片都包括集成电路。然后，将晶圆切割为半导体芯片并封装半导体芯片。封装工艺有两个主要目的：保护精密的半导体芯片，并且把内部集成电路连接到外部连接件。
封装集成电路（IC）芯片过程中，焊料接合是将IC芯片接合至封装衬底的一种方法，该封装衬底可能或可能不包括集成电路和/或其他无源元件。封装衬底也可能包括硅通孔（TSV）。焊料接合工艺可能涉及在焊料上方的施加助焊剂、焊料回流、以及助焊剂去除。芯片封装过程中具有许多挑战。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种芯片封装件，包括：第一铜柱，位于芯片上方且具有第一高度；以及第二铜柱，位于衬底上方且具有第二高度；其中，所述第二铜柱通过焊料层与所述第一铜柱接合，以形成具有间隔的所述芯片封装件的第一铜柱凸块结构，其中，所述第一高度和所述第二高度的总和与所述间隔的比率等于或大于约0.6且小于1。
在该芯片封装件中，所述第一铜柱的第一宽度等于或小于约30μm以及所述第二铜柱的第二宽度也等于或小于约30μm。
该芯片封装件进一步包括第二铜柱凸块结构，所述第二铜柱凸块结构紧挨着所述第一铜柱凸块结构形成，其中，所述第一铜柱凸块结构和第二铜柱凸块结构之间的间距等于或小于约60μm。
在该芯片封装件中，所述第一铜柱的纵横比等于或大于约0.45。
在该芯片封装件中，所述间隔等于或大于约30μm。
在该芯片封装件中，所述第一铜柱设置在金属焊盘上方，并且在所述第一铜柱和所述金属焊盘之间具有凸块底部金属化（UBM）层。
在该芯片封装件中，所述衬底是中介板。
在该芯片封装件中，所述中介板包括硅通孔。
在该芯片封装件中，所述第一铜柱具有以下形状中的一种：圆形、椭圆形、跑道形、圆角矩形或圆角正方形。
在该芯片封装件中，所述焊料层是无铅层，所述焊料层包括锡银，或锡、铅、银、铜、镍、铋、钴、钨的合金，或其组合。
该芯片封装件进一步包括所述芯片和所述衬底之间的底部填充物；其中所述底部填充物没有空隙。
根据本发明的另一方面，提供了一种芯片封装件，包括：第一铜柱，位于芯片上方且具有第一高度；以及第二铜柱，位于衬底上方且具有第二高度；其中，所述第二铜柱通过焊料层与所述第一铜柱接合，以形成具有间隔的所述芯片封装件的第一铜柱凸块结构，其中，所述第一高度和第二高度的总和与所述间隔的比率等于或大于约0.6且小于1，并且所述第一铜柱的第一宽度等于或小于约30μm。
根据本发明的又一方面，提供了一种形成芯片封装件的方法，包括：提供具有多个第一铜柱凸块的芯片，其中，所述多个第一铜柱凸块具有第一铜柱高度；提供具有多个第二铜柱凸块的衬底，其中，所述多个第二铜柱凸块具有第二铜柱高度；通过在所述多个第一铜柱凸块和所述多个第二铜柱凸块上进行焊料层回流，将所述多个第一铜柱凸块和所述多个第二铜柱凸块接合在一起，以形成所述芯片封装件的第一铜柱凸块结构，其中，所述第一铜柱凸块结构具有间隔，其中，所述第一铜柱高度和所述第二铜柱高度的总和与所述间隔的比率等于或大于约0.6且小于1。
该方法进一步包括：在接合之前，在所述多个第一铜柱凸块和所述多个第二铜柱凸块上方施加助焊剂；以及在接合之后，从所述芯片和所述衬底之间去除所述助焊剂，其中，在去除所述助焊剂之后，所述芯片封装件上基本上没有残留物。
该方法进一步包括：在接合之后，将底部填充物形成在所述芯片和所述衬底之间，其中，所述底部填充物基本上不含有空隙。
在该方法中，所述多个第一铜柱凸块和所述多个第二铜柱凸块的规定宽度等于或小于约30μm。
在该方法中，所述多个第一铜柱凸块和所述多个第二铜柱凸块的间距等于或小于约60μm。
在该方法中，所述多个第一铜柱凸块和所述多个第二铜柱凸块的纵横比等于或大于约0.45。
在该方法中，所述间隔等于或大于约30μm。
附图说明
为了更完整地理解实施例及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1A是根据一些实施例的具有衬底的凸块结构的横截面图。
图1B是根据一些实施例的分别地形成铜柱凸块之后的芯片和衬底的横截面图。
图1C是根据一些实施例的将芯片接合至衬底以形成封装件的横截面图。
图1D是根据一些实施例的接合芯片和衬底的工艺流程。
图1E是根据一些实施例的芯片封装件的横截面图。
图2A是根据一些实施例的芯片封装件的横截面图。
图2B是根据一些实施例的凸块间距、凸块间间隔以及间隔高度相对于焊料层总厚度的曲线图。
图3A是根据一些实施例的铜柱宽度为20μm、15μm和10μm的α比率和间隔高度相对于焊料总厚度的曲线图。
图3B根据一些实施例的铜柱宽度为20μm、15μm和10μm的α比率和间隔高度相对于焊料总厚度的曲线图。
图4A是根据一些实施例的两个封装件的助焊剂清洗的残留物作为间隔的函数的曲线图。
图4B是根据一些实施例的铜柱凸块的各个俯视图。
具体实施方式
以下详细讨论了本公开内容的实施例的制造和使用。然而，应该理解，实施例提供了许多可以在各种具体环境中实现的可应用的创造性概念。所讨论的具体实施例仅为说明性的，并且没有限定本公开内容的范围。
图1A是根据一些实施例的具有衬底110的凸块结构100。衬底110可以是半导体衬底，如体硅衬底，但是该衬底可以包括其他半导体材料，如III族、IV族，和/或V族元素。半导体器件114（例如，晶体管）可以形成在衬底110的表面上。衬底110可以包括硅、砷化镓、绝缘体上硅（“SOI”）或其他类似的材料。衬底110也可以包括：无源器件，例如电阻器、电容器、电感器等；或有源器件，诸如晶体管。在示例性实施例中，衬底110可以包括另外的集成电路。衬底100可以是中介板。此外，在可选的实施例中，衬底110也可以是其他材料。例如，可以使用多层电路板。衬底110也可以包括双马来酰亚胺三嗪（bismaleimide triazine,BT）树脂、FR-4（一种复合材料，由具有阻燃的环氧树脂粘合剂的纺织玻璃纤维布组成）、陶瓷、玻璃、塑料、胶带、薄膜、或者其他支撑材料。
互连结构112包括形成在其中并连接到半导体器件114的金属线和通孔（未示出），互连结构112形成在衬底110上方。金属线和通孔可以由铜或铜合金形成，并且使用众所周知的镶嵌工艺形成。互连结构112可能包括公知的层间介电层（ILD）和金属间介电层（IMD）。
金属焊盘128形成在互连结构112上方。金属焊盘128可能包括铝，因此还称为铝金属焊盘128，但是金属焊盘也可以由其他材料形成，或者包括其他材料，例如，铜、银、金、镍、钨、其合金、和/或其多层。例如，金属焊盘128可以通过下面的互连结构112电连接至半导体器件114。金属焊盘128可以是顶部金属层或再分布层（RDL）。在一些实施例中，形成钝化层130以覆盖金属焊盘128的边缘部分。钝化层130可以由聚酰亚胺或其他已知的介电材料形成。另外的钝化层可以形成在互连结构112上方并形成在与金属焊盘128相同的层中或者金属焊盘128上方。另外的钝化层可以由诸如氧化硅、氮化硅、未掺杂硅酸盐玻璃（USG）、聚酰亚胺的材料和/或其多层形成。
根据一些实施例，凸块结构100包括扩散阻挡层140和薄种子层142。扩散阻挡层140可以是钛层、氮化钛层、钽层、或氮化钽层。种子层142的材料可能包括铜或铜合金，因此在下文中被称为铜种子层142。然而，也可以包括其他材料，诸如银、金、铝、及其组合。组合的扩散阻挡层140和铜种子层142可以称为凸块底部金属化（UBM）层145。
在一些实施例中，凸块结构100也包括铜层150、金属层152和焊料层160。根据一些实施例，通过利用限定开口的光掩膜进行电镀形成铜层150、金属层152和焊料层160。在一些实施例中，金属层152是含镍层，例如，含镍层包括通过电镀形成的镍层或镍合金层。在一些其他的实施例中，金属层152含钴或钨。金属层152防止形成铜和焊料的金属化合物（IMC）。例如，焊料层160可以是由锡银或焊料材料形成的无铅预焊料层，焊料层包括锡、铅、银、铜、镍、铋的合金、或其组合。图1A中，作为回流的结果，焊料层160具有圆角。
铜层150的厚度大于焊料层160的厚度；凸块结构100被称为铜柱（或导柱）凸块。对于先进的芯片封装来说，减小了凸块间距和凸块宽度。铜柱凸块能够减小凸块间距和宽度。图1A的实施例仅仅是例子；凸块的其他实施例也是可能的。在以下专利申请中提供了凸块形成工艺的进一步的细节：于2010年7月23日提交且名称为“Preventing UBM Oxidation in BumpFormation Processes”的美国专利申请第12/842,617号；和于2010年7月中29日提交且名称为“Mechanisms for Forming Copper Pillar Bumps”的美国专利申请第12/846,353号，将这两个申请的全部内容结合于此作为参考。
图1B是根据一些实施例的分别地形成铜柱凸块121和126之后的芯片120和衬底125的横截面图。衬底125可以包括有源或无源器件，并具有硅通孔（TSV）。铜柱凸块121与铜柱凸块126对准，以用于接合。
图1C示出了根据一些实施例的芯片120接合至衬底125以形成封装件122的横截面图。芯片120和衬底125之间的空间填充有底部填充物127，接合焊料123具有平滑的轮廓。图1C中的凸块结构具有间距P1和间隔（或间隔高度）S1。铜柱凸块121和126的宽度是W1。
图1D示出了根据一些实施例接合芯片120和衬底125的工艺流程135。在操作136中，铜柱凸块形成在芯片120和衬底125上方。在操作137中，在一些实施例中，助焊剂分别地施加在铜柱凸块121和铜柱凸块126上方。助焊剂是化学清洗剂，该化学清洗剂有助于在焊料回流过程中防止焊料的氧化。施加助焊剂可能涉及将凸块浸渍在助焊剂中或者将助焊剂散布在铜柱凸块上方。在一些实施例中，助焊剂施加在铜柱凸块121或铜柱凸块126的一个上方，但不是施加两个铜柱凸块121和126上方。助焊剂施加完成之后，在操作138中，铜柱凸块121和126通过焊料回流接合在一起。然后，在操作139中，从通过凸块121和126接合在一起的芯片120和衬底125之间的空间去除（或清洗）助焊剂。根据一些实施例，助焊剂去除（或清洗）可能涉及喷涂溶剂、施加去离子（DI）水、加热、和干燥芯片封装件122。在去除助焊剂之后，在操作140中，底部填充物形成在芯片120和衬底125之间的空间中。底部填充物形成可能涉及在空间里注入底部填充材料并且还固化底部填充材料。
图1E是根据一些实施例的芯片封装件122*的横截面图。芯片封装件122*包括芯片120*和衬底125*，其中，铜柱凸块121*和铜柱凸块126*接合在一起以形成凸块结构B1*和B2*。芯片120*、衬底125*、凸块121*和凸块126*分别地与芯片120、衬底125、凸块121和凸块126类似。凸块121*和凸块126*之间的间距为距离P2，铜柱凸块121和126之间的间距为距离P1，其中，距离P2小于距离P1。铜柱凸块121*和铜柱凸块126*的宽度W2小于图1C中的W1。封装件122*的间隔S2也小于图1C的间隔S1。
图1E示出了凸块结构B1*和B2*之间的焊料123*的桥接（参见桥接区123’），该桥接是狭窄的间距和/或多余焊料123*的结果。焊料桥接导致不期望信号误差和芯片故障。图1E也示出了一些焊料123*溢出覆盖铜柱121*的侧壁（参见区域123”），从而也可以被称为铜柱侧壁上的焊料润湿。由于形成了铜和焊料的金属化合物（IMC），铜柱的焊料润湿增加了铜导柱短路和劣化的风险。
如以上在工艺流程135中所述的，在铜柱凸块121*和126*焊接在一起以形成凸块结构B1*和B2*之后，去除助焊剂。由于减小了铜柱凸块121*和126*之间的间距P2并且减小了间隔S2，芯片封装件122*的一些区域中的助焊剂很难去除。此外，现有桥接区123’使得芯片封装件122*的一些区域中的助焊剂去除甚至更加困难。图1E示出了凸块结构B1*和B2*之间及桥接区123’下方的残留助焊剂128*。残留助焊剂128*可能导致底部填充物中的空隙。在去除助焊剂之后，形成底部填充物127*。桥接区123’和残留助焊剂128*之间的减小空间导致空隙129*形成在底部填充物127*中。由于凸块强度不足和缺少底部填充物保护，空隙129*可能在器件工作期间导致初期凸块故障。因为具有凸块结构B1*和B2*的形成不良所导致的各种问题，所以重要的是适当形成封装件之间的凸块结构，以提高用于通过较小间距、较小铜柱宽度和较小间隔进行先进封装的成品率和可靠性。
图2A是根据一些实施例的芯片封装件200的横截面图。芯片封装件200与芯片封装件122*类似，且芯片封装件200具有间隔S，以及间距P。铜柱结构的铜层的宽度为W。芯片上的铜柱凸块121的焊料层增加厚度为T1和衬底上的铜柱凸块126的焊料层增加厚度为T2，当T1+T2较小时，焊料层T的厚度大致等于焊料层的增加厚度。图1B中限定了T1和T2。当T1+T2较大的情况下，由于焊料材料（在焊料结点123）并为一体和焊料超过铜柱边界突出，T明显地小于T1+T2。铜柱凸块121的铜层高度为C1，铜柱凸块126的铜层高度为C2。相邻的焊料层之间的最小距离为D（或凸块间间隔）。图2B是根据一些实施例的凸块间距、凸块间间隔以及间隔高度相对于焊料层的总厚度（T1+T2）的曲线图。在一些实施例中，T1等于T2。图2B示出了D随着总焊料厚度（T1+T2）的增加而减小。当焊料层变得越厚，焊料层突出的部分变得越大，从而降低了凸块间间隔D。
图2B示出了根据一些实施例的三个不同凸块设计的计算结果。在图2B中的例子中，铜柱的宽度是间距尺寸的一半。对于具有40μm的间距（P）和20μm的铜层宽度W的凸块来说，曲线210表示凸块间间隔D相对于焊料厚度T的变化。曲线220与曲线210类似，然而，对于曲线220来说，间距为30μm且宽度W为15μm。类似地，对于曲线230来说，间距为20μm且宽度W为10μm。曲线210-230的数据表明凸块间间隔D随着间距的降低和宽度W的降低而降低。凸块间间隔D随着焊料总厚度（T1+T2）的增加而减小。当T1+T2较大时，在接合焊料123处的更多焊料向外突出。因此，凸块间间隔D减小。
先进的封装采用较小的间距尺寸（P）和较小的凸块宽度（W）。减小的凸块间间隔D使得先进的封装更具挑战性。图2B表明，当焊料总厚度T为约45μm时，对于最小的凸块间距P和宽度W（20μm的P和10μm的W）来说，凸块间间隔D几乎为零（短路）。相比而言，对于凸块间距（P）为40μm和铜层宽度W为20μm的凸块来说，当焊料总厚度T为约45μm时，凸块间间隔D约为8μm。图2B表明，允许的焊料层总厚度将随着间距尺寸和凸块宽度的减小而减小。
图2B也是当C1（凸块121的铜层高度）和C2（凸块126的铜层高度）二者都是15μm时，间隔S相对于三个铜柱宽度的焊料总厚度（T1+T2）的曲线图。曲线240的铜柱宽度是20μm。曲线250的铜柱宽度是15μm以及曲线260的铜柱宽度是10μm。对于全部三条曲线来说，间隔随着焊料层总厚度的增加而增加。然而，因为更多焊料可用于增加凸块结构的间隔（总高度），所以具有较大铜柱宽度的凸块的增长率更大。
图3A是根据一些实施例的阿尔法（α）比率作为焊料层总厚度（T1+T2）的函数的曲线图。α比率定义为C1+C2（铜层总高度）与S（间隔）的比率。图3A包括三条α比率曲线。在图3A的实例中，C1=C2=15μm。曲线310是计算用于铜层宽度20μm的α比率的结果。曲线320是计算用于铜层宽度15μm的α比率的结果。曲线330是计算用于铜层宽度10μm的α比率的结果。当焊料层的总厚度T1+T2增加时，由于间隔高度S增加，α比率减小。图3A中也示出了图2B中间隔的曲线240、250和260。由于具有较大宽度的铜层的S增加较快，曲线330在曲线310和320上方。当焊料总厚度等于或小于约40μm时，图3A中的所有α比率都大于约0.6。如上所述，当焊料总厚度约为45μm时，具有较小间距和宽度（P=20μm及W=10μm）的凸块存在短路（或零凸块间间隔）的风险。甚至对于具有较小间距和宽度（P=20μm及W=10μm）的凸块来说，当焊料总厚度等于或小于约40μm时，短路风险也降低。
图3B是根据一些实施例的（对于铜柱宽度为20μm、15μm及10μm来说）的α比率和间隔S的曲线图。对于图3B中的间隔S，C1=C2=10μm。曲线270是计算用于铜层宽度20μm的间隔。曲线280是计算用于铜层宽度15μm的S的结果。曲线290是计算用于铜层宽度10μm的S的结果。图3B也包括作为焊料总厚度的函数的α比率。在图3B中，曲线340是用于宽度为20μm的铜柱的α比率。曲线350是用于宽度为15μm的铜柱的α比率结果。曲线360是用于宽度为10μm的铜柱的α比率。图3B中的较低的铜层高度（C1=C2=10μm）的α比率低于图3A（C1=C2=15μm）中的α比率。虽然图3A和图3B中所示的结果用于具有圆形俯视图的铜柱，但是结果趋势与具有不同俯视图形状的铜柱的结果趋势类似。
图2B中的结果说明，具有较小宽度W的凸块结构的焊料总厚度T低于具有较大宽度W的凸块结构的焊料总厚度。通过曲线240高于曲线260说明了这种情况，因为随着焊料总厚度T的增加，间隔S也增加。如上所述，对于小如20μm间距和10μm宽度的凸块，将焊料总厚度T1+T2设置为等于或小于40μm以避免短路。图3A和图3B中的结果说明，对于具有较小间距的凸块结构来说，凸块结构的α比率比较高。在一些实施例中，0比率等于或大于约0.6以避免短路。α比率的上限为1.0。在一些实施例中，α比率等于或大于约0.55。如上所述，α比率的下限取决于铜柱的宽度和高度。当α比率太低时，短路风险增加。
除了限定焊料总厚度T和α比率的极限值以外，间隔（S）的极限值也很重要。图4A是根据一些实施例，具有较大芯片的封装件A（曲线410）和具有较小芯片的封装件B（曲线420）的助焊剂清洗残留物作为间隔S的函数的曲线图。封装件B的总表面积小于封装件A的总表面积。在助焊剂去除期间，如果间隔太小，则芯片和衬底之间的助焊剂不能完全去除且留下残留物。因为清洗溶液更容易到达芯片和衬底之间的空间，所以具有较高间隔的封装件更容易清洗。
除了间隔以外，助焊剂清洗还受封装件上的芯片尺寸的影响。对于较大的封装件（或具有较大表面积的封装件）来说，助焊剂清洗液和/或漂洗液需要进一步进入芯片和衬底之间的空间以去除封装件中心附近的助焊剂。相比而言，对于较小的封装件来说，助焊剂清洗液和/或漂洗液不需要长距离流动以到达封装件中心附近的助焊剂。如图4A所示，当两个封装件的间隔相同时，封装件A的助焊剂去除曲线410比封装件B的曲线420具有较多的残留物。助焊剂去除的目标是没有残留物。在一些实施例中，完全去除助焊剂的间隔S的极限值为等于或大于约30μm。在一些实施例中，完全去除助焊剂的间隔S的极限值为等于或大于约25μm。间隔的极限值取决于封装件尺寸。而且，间隔的极限值也受图案密度的影响。在一些实施例中，间隔的极限值随图案密度的增加而增大。
间隔也影响空隙的形成。较低间隔形成空隙的风险较大，这与助焊剂去除相关。如上所述，助焊剂残留物增大了形成底部填充物空隙的风险。在一些实施例中，为防止形成底部填充物空隙，间隔S的极限值等于或大于约30μm。在一些实施例中，间隔S的极限值等于或大于约25μm。间隔的极限值也取决于封装件尺寸和图案密度。
对于先进的封装来说，铜柱凸块的宽度和间距不断减小。在一些实施例中，铜柱的宽度（W）等于或小于约30μm。在一些实施例中，铜柱的间距（P）等于或小于约60μm。图4B示出了根据一些实施例的铜柱凸块的各种俯视图。铜柱凸块可以具有圆形、椭圆形、跑道形、圆角矩形（圆角）、圆角正方形等的俯视图。其他形状也是可能的。
此外，铜层（或导柱）的纵横比可能也很重要。如图1B所示，铜层的纵横比（A）限定铜层的高度H与铜层的宽度W的比率。纵横比的最小值降低了间隔低于间隔极限值的风险。在一些实施例中，纵横比等于或大于约0.45。
上述形成凸块结构的机制能够形成芯片和衬底之间的凸块结构，以消除或降低焊料短路、助焊剂残留物及底部填充物中的空隙风险。通过接合凸块结构中的铜柱的总高度除以接合凸块结构的间隔来定义α比率，可以建立α比率的下限值以避免短路。也可以建立芯片封装件的间隔的下限以避免助焊剂残留物和底部填充物空隙形成。而且，铜柱凸块的纵横比具有下限值，以避免间隔不足；以及上限值，由于制造工艺限制。通过遵循适当的凸块设计和工艺准则，芯片封装件的产量和可靠性可能增加。
根据一些实施例，提供芯片封装件。芯片封装件包括芯片上的第一铜柱，具有第一高度；以及衬底上的第二铜柱，具有第二高度。第二铜柱通过焊料层接合至第一铜柱，以形成芯片封装件的第一铜柱凸块结构，该第一铜柱凸块结构具有间隔。第一高度和第二高度的总和与间隔的比率等于或大于约0.6且小于1。
根据一些实施例，提供芯片封装件。芯片封装件包括芯片上的第一铜柱，具有第一高度；以及衬底上的第二铜柱，具有第二高度。第二铜柱通过焊料层接合至第一铜柱，以形成芯片封装件的第一铜柱凸块结构，第一铜柱凸块结构具有间隔。第一高度和第二高度的总和与间隔的比率等于或大于约0.6且小于1，以及第一铜柱的第一宽度等于或小于约30μm。
根据一些实施例，提供形成芯片封装件的方法。方法包括提供具有多个第一铜柱凸块的芯片，并且多个第一铜柱凸块具有第一铜柱高度。方法也包括提供具有多个第二铜柱凸块的衬底，并且多个第二铜柱凸块具有第二铜柱高度。方法进一步包括：通过在多个第一铜柱凸块和多个第二铜柱凸块上进行焊料层回流将多个第一铜柱凸块和多个第二铜柱凸块接合在一起，以形成芯片封装件的第一铜柱凸块结构。第一铜柱凸块结构具有间隔，其中，第一铜柱高度和第二铜柱高度的总和与间隔的比率等于或大于约0.6且小于1。
尽管已经详细地描述了本实施例及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变、替换和更改。而且，本申请的范围不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造、材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。此外，每条权利要求构成单独的实施例，并且多个权利要求和实施例的组合在本发明的范围内。

Claims (10)

1.一种芯片封装件，包括：
第一铜柱，位于芯片上方且具有第一高度；以及
第二铜柱，位于衬底上方且具有第二高度；其中，所述第二铜柱通过焊料层与所述第一铜柱接合，以形成具有间隔的所述芯片封装件的第一铜柱凸块结构，其中，所述第一高度和所述第二高度的总和与所述间隔的比率等于或大于约0.6且小于1。
2.根据权利要求1所述的芯片封装件，其中，所述第一铜柱的第一宽度等于或小于约30μm以及所述第二铜柱的第二宽度也等于或小于约30μm。
3.根据权利要求1所述的芯片封装件，进一步包括第二铜柱凸块结构，所述第二铜柱凸块结构紧挨着所述第一铜柱凸块结构形成，其中，所述第一铜柱凸块结构和第二铜柱凸块结构之间的间距等于或小于约60μm。
4.根据权利要求1所述的芯片封装件，其中，所述第一铜柱的纵横比等于或大于约0.45。
5.根据权利要求1所述的芯片封装件，其中，所述间隔等于或大于约30μm。
6.根据权利要求1所述的芯片封装件，其中，所述第一铜柱设置在金属焊盘上方，并且在所述第一铜柱和所述金属焊盘之间具有凸块底部金属化（UBM）层。
7.根据权利要求1所述的芯片封装件，其中，所述衬底是中介板。
8.根据权利要求7所述的芯片封装件，其中，所述中介板包括硅通孔。
9.一种芯片封装件，包括：
第一铜柱，位于芯片上方且具有第一高度；以及
第二铜柱，位于衬底上方且具有第二高度；其中，所述第二铜柱通过焊料层与所述第一铜柱接合，以形成具有间隔的所述芯片封装件的第一铜柱凸块结构，其中，所述第一高度和第二高度的总和与所述间隔的比率等于或大于约0.6且小于1，并且所述第一铜柱的第一宽度等于或小于约30μm。
10.一种形成芯片封装件的方法，包括：
提供具有多个第一铜柱凸块的芯片，其中，所述多个第一铜柱凸块具有第一铜柱高度；
提供具有多个第二铜柱凸块的衬底，其中，所述多个第二铜柱凸块具有第二铜柱高度；
通过在所述多个第一铜柱凸块和所述多个第二铜柱凸块上进行焊料层回流，将所述多个第一铜柱凸块和所述多个第二铜柱凸块接合在一起，以形成所述芯片封装件的第一铜柱凸块结构，其中，所述第一铜柱凸块结构具有间隔，其中，所述第一铜柱高度和所述第二铜柱高度的总和与所述间隔的比率等于或大于约0.6且小于1。
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