TWI269457B - Flip-chip package-on-package structure and method for making the same - Google Patents

Abstract

A flip-chip package-on-package structure comprises a first flip-chip package having a first substrate and a first semiconductor chip flip-chip mounted on the first substrate; and a second flip-chip package having a second substrate and a second semiconductor chip flip-chip mounted on the second substrate; wherein the first semiconductor chip and the second semiconductor chip are oppositely connected to each other by a plurality of metal bumps such that the first/second flip-chip package is oppositely stacked on the first/second flip-chip package, whereby forming a flip-chip package-on-package structure with low profile. The present invention also provides a method for making the flip-chip package-on-package structure.

Description

1269457 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a stacked package structure, a flip chip stacked package structure. [Prior Art]

With micro (the more common the package is. The increase and the increase in the multi-functional requirements on Package; POP) in the use of many electronic stacking and packaging devices more than two packages of packaged components of electrical work. In addition, the stacked package reduces the signal delay. Generally speaking, the stacked package structure stacks two or a single package component, thereby increasing the single month b 'and saving the space structure on the printed circuit board to shorten the package structure. Line length, and access time. However, for stacked package configurations, when two or more package configurations are stacked into a single-package component, the overall thickness of the package is increased, which may result in limitations in use. In view of the above, the present invention provides a flip chip stacked package structure having a low thickness, thereby solving the above problems. SUMMARY OF THE INVENTION One object of the present invention is to provide a flip chip package structure that can solve the problem of use limitation caused by the thickness of a self-known stacked package structure. In order to achieve the above object, the present invention provides a flip chip stacked package structure, which comprises a first flip chip package structure having a first substrate and a

ASE1478/01058-TW 5 1269457 The first half of the body wafer is flip-chip mounted on the second flip chip package structure, and has a 箆--the substrate and a second semiconductor wafer are disposed in the daytime manner On the second substrate; wherein the 曰^^, Dingshou version of the sun and the moon" *Haidi-semiconductor wafers are facing the ground phase by the double-double 1u to the convex bumps, so that the first/second flip chip package The structural system is stacked on the second / := mounting structure to form a stacked coating having a low thickness: a sealing and construction. • The flip chip stacked packaging structure according to the present invention may further have a reinforcing member. Connecting the first substrate of the first flip chip package structure to the second substrate of the second flip chip package structure, thereby reinforcing the fixed structure between the first substrate and the second substrate, and dispersing the flip chip The heat generated by the stacked package structure. Embodiment 1 is a cross-sectional view of a flip chip package structure 100 according to an embodiment of the present invention. The flip chip package structure 10 includes a first overlay _ Crystal package structure 102 and a second flip chip package The first flip-chip package structure 102 includes a substrate 〇6, and a half of the body wafer 108 is disposed in a fiip_chip bond manner. The upper surface i06a of the substrate 106. The semiconductor wafer 1 8 has an upper surface 10a, and a lower surface iosb opposite to the upper surface 108a. The upper surface 108a has a plurality of circuit contacts/pads 1〇7a For example, the 1/〇 contact or the pad is electrically connected to the pad 1〇9 of the upper surface 106a of the substrate 1 藉6 by a plurality of metal bumps 11 。. The lower surface 108b also has a plurality of

ASE1478/01058-TW 1269457 circuit contacts/pads 1 〇7b, electrically connected to the circuit contacts on the upper surface 1〇8a by a plurality of (only one) conductive via holes 112 / pads 107a. Alternatively, the lower surface 1 〇 8b is also formed with a plurality of conductive metal lines (not shown) through which the circuit contacts/pads i 〇 7b can pass through the conductive vias (via h〇le) The path of n2 is electrically connected to the circuit contact/pad 7a. In this embodiment, the conductive plated through hole 112 can form a through hole between the lower surfaces 10a and 108b of the semiconductor wafer 1 8 by etching, and then form a metal layer in the through hole. obtain. In addition, an underfill 114 is filled between the upper surface 106a of the substrate ι6 and the upper surface 〇8a of the semiconductor wafer 〇8. In the first flip chip package structure 102, the lower surface of the substrate 1 6 is further provided with a plurality of metal bumps 116 for electrically connecting to a circuit substrate such as a printed circuit board (not shown). )on. In addition, the plurality of metal bumps 116 can be formed by a plurality of conductive plated through holes (not shown) penetrating between the lower surfaces 106a and 106b of the substrate 1〇6, and a plurality of metals formed on the substrate 106. A conductive line (not shown) is electrically connected to the plurality of pads 1 〇 9 on the upper surface 106a. The second flip chip package structure 104 includes a substrate stack 18 and a half conductor wafer 120 disposed on the upper surface U8a of the substrate 118 in a flip-chip manner. The semiconductor wafer 12 has an upper surface 120a and a lower surface i20b with respect to the upper surface 12A. The upper surface 120a has a plurality of circuit contacts/pads i21a, such as: 1/〇 contacts or contacts, electrically connected to the upper surface 118a of the substrate workpiece 8 by a plurality of metal bumps 1 22 Pad 123. The lower surface 12〇b also has a plurality of circuit contacts/pads 1 2 1 b, respectively, opposite to the semiconductor wafer 1 〇 8

ASE1478/01058-TW 7 1269457 A plurality of circuit contacts/pads 1〇7b on surface 108b, and electrically connected to the plurality of circuit contacts/pads 1 〇 7 b by a plurality of metal bumps 12 4 . In addition, the plurality of circuit contacts/pads mb on the lower surface 120b are electrically connected to the circuit contacts/interfaces on the upper surface 120a by a plurality of (only one) conductive plated through holes 12 6 . I2ia. Alternatively, the lower surface 12 is formed with a plurality of conductive metal lines (not shown), such that the circuit contacts/pads 121b can be electrically connected to the conductive vias 126 via the metal lines. Circuit contact/pad 121a. In this embodiment, the conductive vias 126 are released by forming the conductive vias 112. In addition, an underfill 128 is filled between the upper surface 118a of the substrate 118 and the upper surface i2a of the semiconductor wafer 120, and a filler 129 is filled on the lower surface 1 of the semiconductor wafer 1? The rib is interposed between the lower surface i20b of the semiconductor wafer 120. In the first flip chip package structure 104, the lower surface Π 8b of the substrate 11 8 is further provided with a plurality of metal bumps 13 〇 for electrically connecting to other semiconductor components such as any package type semiconductor package. Construction or semiconductor wafer. In addition, the plurality of metal bumps 130 can be formed by a plurality of conductive plated through holes (not shown) extending through the upper surfaces 118a and 118b of the substrate 118, and a plurality of metals formed on the substrate 8 A conductive line (not shown) is electrically connected to the plurality of pads 123 on the upper surface 118a. It should be understood that, in other alternative embodiments, the plurality of metal bumps 13〇 are not required to be disposed on the lower surface 118b of the substrate 〇8, and only a plurality of electrical and circuit contacts/pads need to be formed. (not shown), and directly connected to a circuit substrate (not shown) by a bond (eg, a printed circuit board). ASE1478/01058-TW, 8 1269457 In the flip chip stacked package structure 100 of the present invention, the lower surfaces 1〇8b, 12〇b of the semiconductor wafers 108, 120 respectively have the plurality of circuit contacts/pads 107b and 121b And directly electrically connected to each other via the plurality of metal bumps 124. The flip chip stacked package structure 1 (10) of the present invention has a lower thickness (pr〇file) than the stacked structure of the package structure k having the encapsulant in the prior art, and thus can be applied to some In electronic products with space constraints. φ Figure 2 is a cross-sectional view of a flip chip package structure 100 in accordance with another embodiment of the present invention. The only difference between the first and second figures is that the flip chip package structure 100 shown in FIG. 2 is further provided with a reinforcing member 140 on the periphery of the two wafers 108 and 120, and is connected to the two substrates 1 and 6. The upper surface 106a and the upper surface U8a of the substrate 118 are used to strengthen the fixed structure between the two substrates 106 and 11 8 and to dissipate the heat generated by the flip chip package structure 100 itself. In the embodiment of the present invention, the reinforcing member 140 can be an annular ring-shaped reinforcing ring. As shown in the upper view of FIG. 3, the reinforcing ring 〇4 defines an opening 142, thereby Two semiconductor wafers 1 , 8 , 12 are housed therein. Alternatively, the reinforcing member 140 may be composed of a plurality of reinforcing columns 14A, 140b, 140c, and 140d and disposed on peripheral regions of the two semiconductor wafers 108, 120, respectively. 5 to 7 are views for explaining a method of manufacturing the flip chip package structure 1 of the embodiment of the present invention. As shown in Fig. 5, first, two overmolding structures I 02 '104 are formed by flip chip mounting techniques. The two flip-chip packages 丨〇2, 丨〇4 half ASE1478/01058-TW 9 1269457 The lower surfaces i 〇 8b and 120b of the conductor wafers 108 and 120 can be formed by a redistribution layer process. A plurality of metal conductive lines (not shown), and a plurality of circuit contacts/pads 107b and 1 2 1 b are respectively defined thereon. In accordance with an embodiment of the present invention, the plurality of circuit contacts/pads 107b are located on the semiconductor wafer 108 corresponding to the plurality of circuit contacts/pads 12 1b being located on the semiconductor wafer 120, respectively. φ Next, as shown in Fig. 6, a plurality of metal bumps 124 are formed on a plurality of circuit contacts/pads 107b of the semiconductor wafer 108. In this embodiment, the plurality of metal bumps 124 can be formed on the plurality of circuit contacts/pads 1 〇 7b by a screen printing process, but is not limited thereto. Alternatively, the plurality of metal bumps 124 may be formed on the plurality of circuit contacts/pads 121b of the semiconductor wafer 12 or simultaneously formed on the plurality of circuit contacts/pads 7b according to process requirements. With mb, it can achieve the same purpose of the present invention. ❿—Next, as shown in FIG. 7, the flip chip package structure 〇4 is stacked upside down on the flip chip package structure 102, and the plurality of circuit contacts/connections on the flip chip package structure 1〇4 The pads 121b are respectively aligned with the plurality of metal bumps 124 on the flip chip package structure 〇2, that is, aligned with the plurality of circuit contacts/pads 107b. Then, a reflow process is performed on the two flip chip package structures 1〇2 and 1〇4, so that the plurality of metal bumps 124 can be attached and electrically connected to the plurality of circuit contacts/pads 1071> between. Thereafter, a filler 129 is injected between the semiconductor wafer 1 8 and the semiconductor wafer. ASE1478/01058-TW 10 1269457 Take silly, from the one---~ 丨Shuangtian i〇6b, U8b, respectively, a plurality of metal bumps 116 and 130' are set to form a cover as shown in Fig. 1. The crystal stacked package structure 100.

The manufacturing method of the flip chip stacked package structure 100 shown in FIG. 2 is substantially the same as that described in FIGS. 5 to 7, which is only one reinforcement in FIG. 5 (that is, before the stacking and reflowing steps). The setting procedure of the ring 140 (as shown in Figures 2, 3, and 4). In this setting step, the reinforcing ring 14 can be disposed on the upper surface of the substrate 106 or one of the substrate = upper surface 118a (not shown) by means of an adhesive. Then, after the two flip-chip packages 102, 104 are stacked and reflowed, the reinforcing ring 14 can be supported between the upper surface 1〇6a of the substrate 1〇6 and the upper surface 118a of the substrate. As shown in Figure 2. The present invention has been disclosed in the foregoing embodiments, and is not intended to limit the scope of the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope is defined as defined in the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a flip chip stacked package structure in accordance with an embodiment of the present invention. Figure 2 is a cross-sectional view showing a flip chip stacked package structure in accordance with another embodiment of the present invention. ~ Fig. 3 is a top view of a reinforcing member according to an embodiment of the present invention. 〃 is a top view of a reinforcing member according to another embodiment of the present invention.

ASE1478/01058-TW 1269457

Figures 5 through 7 are diagrams for explaining the manufacturing method of the stacked package structure of the present invention. [Description of the number] 100 flip-chip stacked package structure 102 104 second flip chip package structure 106 106a upper surface 106b 107a, 107b circuit contact / pad 108 semiconductor wafer 108a 108b lower surface 109 110 metal bump 112 114 fill 116 118 substrate 118a 118b lower surface 120 120a upper surface 120b 121a, 121b circuit contact/pad 122 metal bump 123 124 metal bump 126 128 glue 129 130 metal bump 140 142 opening 140a, 140b, 140c, 140d reinforcement column The flip-chip first flip-chip package structure substrate of the first embodiment has a lower surface surface pad conductive plated through hole metal bump upper surface semiconductor wafer lower surface pad conductive plated through hole filling reinforcement member

ASE1478/01058-TW 12

Claims (1)

1269457 X. Patent Application Range: 1. A flip chip stacked package structure comprising: a first flip chip package structure having a first substrate and a first semiconductor wafer. The first semiconductor wafer has an upper surface a flip chip bonding is disposed on a substrate of a flute, and a lower surface is opposite to the upper surface; a second flip chip packaging structure is stacked on the first flip chip sealing structure, and the eighth substrate is provided And a second semiconductor wafer, the second semiconductor 曰μ has a μ main 《 "I day surface of the wafer is placed on the second substrate in a flip chip manner, and the lower surface is opposite to the upper surface; and A plurality of metal bumps are connected between the lower surface of the first semiconductor wafer and the lower surface of the second semiconductor wafer to electrically conduct the first tom, the body wafer and the second semiconductor wafer. And 2, according to the flip-chip stacked package structure of the application patent scope i, 3 a plurality of metal bumps connected between the first semiconductor and the first substrate. The top surface of the jin and the flip-chip stacking structure of the patent application scope 含i include a plurality of metal bumps connected between the second substrate and the second substrate. /, 4. The flip chip stack according to item i of the patent application scope contains an underfill between the first semiconductor and the lower surface of the second semiconductor wafer. Body...the lower surface and 5, according to the scope of the patent application! The structure of the flip chip stack 4 includes a reinforcing member connected between the first substrate and the ~' coil. ASE1478/01058-TW 13 1269457 6. The flip chip stacked package structure according to claim 5, wherein the δ hai reinforcement member is a reinforcement ring defining an opening for accommodating the first semiconductor wafer and the second semiconductor Wafer. 7. The flip chip stacked package structure according to claim 5, wherein the reinforcing member is composed of a plurality of reinforcing columns and is disposed at a periphery of the first semiconductor wafer and the second semiconductor wafer, respectively. In addition, the plurality of metal bumps are disposed on the lower surface of one of the first substrates, and are electrically connected to a circuit substrate. 9 Desc. 9, Γ Patent Application No. 8 of the flip-chip stacked package structure, wherein the lower surface of the Γ Γ plate has a plurality of circuit contacts, which can be electrically connected to the circuit substrate by wire bonding. 1 依, according to the scope of the patent application No. 1 曰 Containing the ageing gamma I Μ 曰 曰 曰 曰 封装 封装 封装 , , , , , 曰 曰 曰 曰 曰 曰 曰 柹ϋ 柹ϋ 柹ϋ 柹ϋ 柹ϋ 柹ϋ 柹ϋ 柹ϋ 柹ϋ 柹ϋ 柹ϋ 柹ϋ 柹ϋ 柹ϋ 之一 之一 之一 之一 之一 之一11 A method for manufacturing a flip chip package structure, comprising the steps of providing a first flip chip package structure, having a substrate and a first semiconductor chip, the brother a semiconductor wafer is disposed on the first substrate and has a top surface in a flip chip bonding manner, and a contact; the lower surface has a plurality of first circuits to provide a second flip chip package structure,曰U Today... /, a younger brother and a second half of the body, the second semiconductor wafer is /, the upper surface is placed on the second substrate by flip chip bonding, and _ i day The lower surface of the interface side has a plurality of second circuits ASE1478/01058-TW 14 1269457 a plurality of first circuit contacts of the contacts relative to the first semiconductor wafer; forming a plurality of first metal bumps in the plurality of first The second flip chip package structure is stacked on the first flip chip package structure, and the plurality of second circuit contacts are respectively aligned with the plurality of first circuit contacts; The two stacked ones - The plurality of first metal bumps are electrically connected to the plurality of first circuit bumps and the plurality of second circuit contacts between the plurality of first metal bumps and the second flip chip soldering structure 12. The method for fabricating a flip-chip stack package according to the scope of the patent application of the present application, further comprising: underfilling the underlying surface of the first semiconductor wafer and the second semiconductor wafer 13. The method for manufacturing a flip chip stacked package structure according to the scope of claim 5, further comprising: providing a plurality of second metal bumps on a lower surface of the first substrate. 14. According to the patent application scope The method of manufacturing the flip-chip stacked package structure further comprises: providing a plurality of second metal bumps on a lower surface of the second substrate. 1 5, manufacturing the flip chip stacked package structure according to claim 11 The method, before the stacking step, further comprises: providing a reinforcing member on the first substrate. 16. A method for manufacturing a flip chip package structure according to claim 15 of the patent application, wherein the reflow is performed After the step, the reinforcing member is connected between the first substrate and the second substrate. ASE1478 / 01058-TW 15 1269457 1 7. The method for manufacturing a flip chip package structure according to the scope of the patent application, Before the stacking step, the method further comprises: disposing a reinforcing member on the second substrate. 18, manufacturing the flip chip package structure according to claim 17 of the patent application, wherein the reinforcing member is after the reflow step Connected between the first substrate and the second substrate. 19. The method for manufacturing a flip chip package structure according to the scope of claim ii of the patent application, further comprising: forming a plurality of second metal bumps in the plurality of The second circuit is connected. ASE1478/01058-TW 16