CN104576585A - 形成连接至多个穿透硅通孔(tsv)的图案化金属焊盘的机制 - Google Patents

形成连接至多个穿透硅通孔(tsv)的图案化金属焊盘的机制 Download PDF

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Publication number
CN104576585A
CN104576585A CN201410529680.6A CN201410529680A CN104576585A CN 104576585 A CN104576585 A CN 104576585A CN 201410529680 A CN201410529680 A CN 201410529680A CN 104576585 A CN104576585 A CN 104576585A
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China
Prior art keywords
metal pad
tsv
dielectric structure
pattern metal
insert
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CN201410529680.6A
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CN104576585B (zh
Inventor
刘醇鸿
黄诗雯
吕宗育
胡宪斌
侯上勇
郑心圃
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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Abstract

本发明提供了用于形成三维集成电路(3DIC)结构的机制的各种实施例。该3DIC结构包括接合至管芯的插入件和衬底。插入件具有连接到图案化的金属焊盘的穿透硅通孔(TSV)的导电结构和位于TSV的相对端的导电结构。图案化的金属焊盘具有嵌入其中的介电结构以减少凹陷效应，并具有位于TSV上方的没有介电结构的区域。导电结构具有2个或多个TSV。通过使用图案化的金属焊盘和2个或更多的TSV，提高了导电结构和3DIC结构的可靠性和良品率。

Description

形成连接至多个穿透硅通孔(TSV)的图案化金属焊盘的机制
技术领域
本发明涉及半导体领域，更具体地，涉及形成连接至多个穿透硅通孔(TSV)的图案化金属焊盘的机制。
背景技术
半导体器件用于各种电子产品中，诸如个人电脑、手机、数码相机和其他电子设备。通常在半导体衬底上方依次沉积绝缘层或介电层、导电层和半导体材料，然后使用光刻图案化各种材料层以在其上形成电路组件和元件，从而典型地制造半导体器件。
半导体工业通过不断地减小最小部件的尺寸不断地提高各种电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成密度，以允许更多的组件能够集成到给定的区域内。在一些产品中，这些较小的电子部件还需要比过去的封装件使用更少面积的较小的封装件。
已经产生了三维集成电路(3DIC)以进一步缩小集成电路管芯和封装件。已经开始开发新的封装技术以使能3DIC。这些用于半导体的相对新型的封装技术面临着制造上的挑战。
发明内容
为解决上述问题，本发明提供了一种插入件结构，包括：两个或多个穿透硅通孔(TSV)；图案化金属焊盘，其中，两个或多个TSV物理连接至图案化金属焊盘，其中，图案化金属焊盘具有嵌入式介电结构，其中，嵌入式介电结构不在两个或多个TSV的上方；以及导电结构，物理连接至两个或多个TSV的与图案化金属焊盘相对的端。
其中，图案化金属焊盘的嵌入式介电结构具有位于图案化金属焊盘的中心的第一介电结构，其中，第一介电结构的宽度与图案化金属焊盘的宽度的比率在约1/4和约1/2的范围内。
其中，图案化金属焊盘包括多个没有嵌入式介电结构的区域，其中，多个没有嵌入式介电结构的区域位于各个TSV上方。
其中，多个没有嵌入式介电结构的区域位于图案化金属焊盘的各个角处。
其中，图案化金属焊盘被成形为正方形，且多个没有嵌入式介电结构的区域包括位于图案化金属焊盘的各个角处的四个区域。
其中，嵌入式介电结构包括位于多个没有嵌入式介电结构的区域的两个相邻区域之间的第二介电结构。
其中，嵌入式介电结构包括位于多个没有嵌入式介电结构的区域的两个相邻区域之间的多于1个的介电结构。
其中，图案化金属焊盘的嵌入式介电结构包括位于图案化金属焊盘的中心的第一介电结构，且包括位于多个没有嵌入式介电结构的区域的两个相邻区域之间的多于1个的介电结构。
其中，图案化金属焊盘的宽度对导电结构的宽度的比率在约1/3和约1/2的范围内。
其中，导电结构式凸块下金属(UBM)结构。
此外，还提供了一种封装件结构，包括：半导体管芯；插入件结构，连接至半导体管芯，插入件结构还包括：两个或多个穿透硅通孔(TSV)；图案化金属焊盘，其中，两个或多个TSV物理连接至图案化金属焊盘，其中，图案化金属焊盘具有嵌入式介电结构，其中，嵌入式介电结构没有超过两个或多个TSV，以及导电结构，物理连接至两个或多个TSV的与图案化金属焊盘相对的端；以及衬底，连接至插入件。
其中，图案化金属焊盘包括多个没有嵌入式介电结构的区域，其中，多个没有嵌入式介电结构的区域位于各个TSV上方。
其中，多个没有嵌入式介电结构的区域位于图案化金属焊盘的各个角处。
其中，图案化金属焊盘的嵌入式介电结构包括位于图案化金属焊盘的中心的第一介电结构，以及位于多个没有嵌入式介电结构的区域的两个相邻区域之间的多于1个的介电结构。
此外，还提供了一种形成插入件结构的方法，包括：在衬底中形成两个或多个穿透硅通孔(TSV)；形成图案化金属焊盘，其中，两个或多个TSV物理连接至图案化金属焊盘，其中，图案化金属焊盘具有嵌入式介电结构，其中，嵌入式介电结构不在两个或多个TSV上方；研磨衬底的背侧以暴露两个或多个TSV；以及在结构的背侧上形成导电结构，其中，导电结构物理连接至两个或多个TSV。
其中，形成图案化金属焊盘还包括：在两个或多个TSV上方形成介电层；图案化介电层以在介电层中形成开口；使用势垒晶种层覆盖开口；沉积导电层以填充开口；以及去除开口外侧的导电层和势垒晶种层，其中，在去除之后形成图案化金属焊盘。
其中，位于开口之间的介电层形成嵌入式介电结构。
其中，图案化金属焊盘包括多个没有嵌入式介电结构的区域，其中，多个没有嵌入式介电结构的区域位于各个TSV上方。
其中，多个没有嵌入式介电结构的区域位于图案化金属焊盘的各个角处。
其中，图案化金属焊盘的嵌入式介电结构包括位于图案化金属焊盘的中心的第一介电结构，以及位于多个没有嵌入式介电结构的区域的两个相邻区域之间的多于1个的介电结构。
附图说明
为了更全面地理解本发明及其优势，现将结合附图所进行的以下描述作为参考，其中：
图1A是根据一些实施例的封装结构的立体图。
图1B根据一些实施例示出了三维集成电路(3DIC)结构的截面图。
图1C根据一些实施例示出了管芯和插入件之间的连接件(或接合结构)。
图2A至图2D根据一些实施例示出了在穿透硅通孔(TSV)上方形成金属焊盘的连续工艺的截面图。
图3A根据一些实施例示出了金属焊盘的顶视图。
图3B根据一些其他实施例示出了金属焊盘的顶视图。
图4A根据一些实施例示出了导电结构的立体图。
图4B根据一些实施例示出了导电结构的顶视图。
图5根据一些实施例示出了形成3DIC结构的工艺流程。
具体实施方式
下面，详细讨论本发明各实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的发明构思。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式，而不用于限制本发明的范围。
随着集成电路的发明，由于各种电子部件(即，晶体管、二极管、电阻器、电容器等)集成密度的不断提高，半导体工业已经经历了持续快速地发展。在极大程度上，这种集成密度的提高来自于最小部件尺寸的不断减小，以允许更多的部件集成到给定区域中。
这种集成的改进基本上是二维(2D)的性质，这是因为由集成部件占据的体积基本上位于半导体晶圆的表面上。尽管在光刻中的引人注目的提高已经引起2D集成电路形成中的相当大的提高，但是二维中能够达到的密度存在物理限制。其中一个限制就是制造这些部件所需要的最小尺寸。并且，当将更多的器件放在一个芯片中，就需要更复杂的设计。
因此产生了三维集成电路(3DIC)以解决上述限制。在3DIC的形成工艺中，形成了两个或多个晶圆，其中，每一个晶圆都包括集成电路。锯切这些晶圆以形成管芯。封装具有不同器件的管芯，然后使器件对准以接合晶圆。将穿透硅通孔(TSV)和穿透封装件通孔(TPV)，也称作穿透模塑通孔(TMV)，越来越多地用作实现3DIC的方式。TSV和TPV经常用于3DIC和堆叠的管芯中，以提供电连接和/或有助于散热。
图1A是根据一些实施例的包括接合到插入件120且还接合到另一衬底130的管芯110的封装件结构100。在将管芯110接合到插入件120之后，可以将封装件结构锯切成单独的块，且插入件120将看起来是半导体管芯。每个管芯110和插入件120都包括应用于半导体集成电路制造中的半导体衬底，且集成电路可以形成在半导体衬底中和/或半导体衬底上。半导体衬底指的是包括半导体材料的任何结构，半导体材料包括但不限于体硅、半导体晶圆、绝缘体上硅(SOI)衬底或硅锗衬底。也可以使用包括III族、IV族、V族元素的其他半导体材料。半导体材料还可以包括多个隔离部件(未示出)，诸如浅沟槽隔离(STI)部件或硅的局部氧化(LOCOS)部件。隔离部件可以限定和隔离各个微电子元件。可以形成在半导体衬底中的各个微电子元件的实例包括晶体管(例如，金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极结型晶体管(BJT)、高压晶体管、高频晶体管、p沟道和/或n沟道场效应晶体管(PFET/NFET)等)；电阻器；二极管；电容器；电感器；熔断器；和其他合适的元件。实施包括沉积、蚀刻、注入、光刻、退火和/或其他合适的工艺的各种工艺以形成各种微电子元件。将微电子部件互连以形成集成电路器件，诸如逻辑器件、存储器件(例如，SRAM)、RF器件、输入/输出(I/O)器件、芯片上系统(SoC)器件、它们的组合、和其他合适的器件类型。根据一些实施例，插入件120包括起到插入件作用的穿透硅通孔(TSV)或穿透封装件通孔(TPV)。在一些实施例中，插入件120不包括有源器件。
可以由双马来酰亚胺三嗪(BT)树脂、FR-4(由具有环氧树脂粘合剂的耐火的编织玻璃纤维布组成的复合材料)、陶瓷、玻璃、塑料制品、胶带、薄膜、或可以支持需要接收导电端子的导电焊盘或导电地(lands)的其他支持材料。在一些实施例中，衬底130是多层电路板。在一些实施例中，衬底130包括互连结构。
管芯110通过连接件(或接合结构)115接合至插入件120，且插入件120通过连接件145接合至衬底130。如果将具有不同尺寸的连接件的两个或多个管芯(诸如，管芯110和其他管芯)接合至插入件120，则封装机制就会具有挑战性。插入件120中的TSV有助于电连接和散热。
图1B根据一些实施例示出了管芯封装件100’的截面图。管芯封装件100’包括管芯110A和管芯110B。例如，管芯110A可以是中央处理单元(CPU)或图像控制单元(GPU)，且管芯110B可以是存储器件，诸如静态随机存取存储器(SRAM)、动态随机存取存储器(DRAM)或其他类型的存储器件。管芯110A和110B分别通过连接件115A和115B连接到衬底(或插入件)120’。连接件115A和115B是接合结构，其通过接合管芯110A和110B的外部连接件与插入件120’的外部连接件形成。在一些实施例中，通过接合管芯110A和110B上的微凸块(或μ凸块)与插入件120’上的μ凸块112形成连接件(或接合结构)115A和115B。图1C根据一些实施例示出了用于形成连接件(或接合结构)115A的接合至插入件120’上的μ凸块112的管芯110A上的μ凸块111A。μ凸块111A包括铜柱113A、凸块下金属(UBM)层116A和焊料层，其中，焊料层接合到μ凸块112以形成焊料层118A。μ凸块112也包括铜柱114和UBM层117。μ凸块111A形成在金属焊盘109A上方，且μ凸块112形成在金属焊盘119上方。
在一些实施例中，UBM层116A和117包括由Ti形成的扩散势垒层和由Cu形成的晶种层。在一些实施例中，诸如Ti层的扩散势垒层和诸如Cu层的晶种层都是通过物理汽相沉积(PVD)(或溅射)方法沉积的。回流工艺之后，来自连接的μ凸块的焊料层接合以形成诸如焊料层118A的焊料层。μ凸块111A的一部分依靠于钝化层141且μ凸块112的一部分依靠于钝化层142。钝化层141和142由介电且可收缩性材料制成，其中，该材料提供绝缘且吸收接合应力。在一些实施例中，钝化层141和142由聚合物形成，诸如聚酰亚胺、聚苯并恶唑(PBO)或阻焊剂。
在2012年3月22日提交的标题为“Bump Structures for Multi-ChipPackaging”的序列号为13/427,753(代理人卷号为TSMC2011-1339)的美国专利申请、2011年12月28日提交的标题为“Packaged SemiconductorDevice and Method of Packaging the Semiconductor Device”的序列号为13/338,820(代理人卷号为TSMC2011-1368)的美国专利申请、和2012年11月2日提交的标题为“Bonded Structures for Package and Substrate”的序列号为13/667,306(代理人卷号为TSMC2012-0633)的美国专利申请中描述了接合结构的实例及其形成方法。上面提及的申请的全部内容结合于此作为参考。
图1B示出了包括具有TSV 125的硅衬底121的插入件120’。插入件120’包括位于硅衬底121的一侧上的互连结构122和位于互连结构122的相对侧上的凸块126。凸块126类似于图1A中的连接件145。互连结构122将TSV 125连接到外部连接件，μ凸块112。互连结构122包括导电互连结构，诸如金属焊盘、金属线和通孔。导电互连结构通过介电层绝缘。例如，导电互连结构包括诸如M1、M2和M3的金属线和诸如V1、V2和V3的的通孔。导电互连结构还包括金属焊盘，诸如金属焊盘127和119。在一些实施例中，金属焊盘127形成在M1水平面处。金属焊盘127连接到TSV125且金属焊盘119连接到μ凸块112。TSV 125连接到与凸块126连接的各个UBM结构(导电结构)129。在一些实施例中，凸块126是由焊料制成的C4凸块。UBM结构129由导电材料制成。可以由物理汽相沉积(PVD)工艺、原子层沉积(ALD)工艺、化学汽相沉积(CVD)工艺、电化学镀工艺或它们的组合形成导电材料。导电材料的实例包括但不限于钛、镍、铜、钨、铝、银、金或它们的组合。在一些实施例中，UBM结构由Ti制成。UBM结构129由钝化层124彼此隔开。在一些实施例中，钝化层124由聚合物制成，诸如聚酰亚胺、聚苯并恶唑(PBO)或阻焊剂。钝化层124由可收缩性材料制成，以保护插入件120’和凸块126’免受接合应力。
插入件120’通过凸块126连接到衬底130’。每个凸块126都连接到插入件120’上的UBM结构129和衬底130’上的金属焊盘131。金属焊盘131通过钝化层132彼此隔离。钝化层132由聚合物制成，诸如聚酰亚胺、聚苯并恶唑(PBO)或阻焊剂。钝化层132由可收缩性材料制成，以保护插入件120’和衬底130’免受由接合工艺产生的接合应力。
图1B至少示出了2个连接到插入件120’上的金属焊盘127和UBM结构129的TSV 125。相比于一个TSV 125，两个或多个连接到插入件120’上的金属焊盘127和UBM结构129的TSV 125的TSV 125是更令人满意的，这是因为它们提高了良品率，结果在连接TSV 125中存在问题。例如，TSV 125可能与金属焊盘127或UBM结构129具有较差的连接。具有两个或多个TSV以连接金属焊盘127和UBM结构129提高了容错性和良品率。
图1B也示出了形成在管芯110A、110B和插入件120’之间的底部填充胶143。底部填充胶146形成在插入件120’和衬底130’之间。底部填充胶143保护连接件(或接合结构)115A和115B。同样地，底部填充胶146保护凸块126。图1B也示出了模塑料144，形成模塑料144以环绕、覆盖和保护管芯110A、110B和插入件120’。
如上所述，TSV 125连接至金属焊盘127。在将TSV 125形成在衬底121中之后，将金属焊盘127形成在TSV 125上方。图2A至图2D根据一些实施例示出了在TSV 125上方形成金属焊盘127的连续工艺的截面图。图2A示出了形成在衬底121中的TSV 125。TSV 125的形成包括形成深沟槽。在一些实施例中，用于TSV 125的沟槽的宽度W1在约5μm到约15μm的范围内。在一些实施例中，用于TSV 125的沟槽的深度D1在约40μm到约120μm的范围内。如图2A所示，介电内衬层201用于划线于沟槽的壁和衬底121的表面。在一些实施例中，介电内衬层201由氧化硅制成。在一些实施例中，介电内衬层201的厚度在约0.3μm到约1.5μm的范围内。
然后，将势垒层202沉积在介电内衬层201上方。势垒层202由Ti、Ta、TiN、TaN或它们的组合制成。在一些实施例中，势垒层202的厚度在约0.05μm到约0.5μm的范围内。沟槽的剩余部分由导电层203填充，导电层203由具有较低电阻率的导电金属制成，诸如Cu、Cu合金、Al、Al合金或其他可应用的材料。在一些实施例中，导电层203的厚度(在衬底表面上测得)在约4μm到约14μm的范围内。然后，通过诸如化学机械抛光(CMP)工艺去除沟槽外的过量的导电层203和202。如图2A所示，形成了TSV 125。
形成TSV 125之后，在暴露的介电内衬层201和TSV 125的顶面上方形成介电堆叠件204。在一些实施例中，介电堆叠件204包括蚀刻停止层205和中间级(inter-level)介电(ILD)层206。在一些实施例中，蚀刻停止层205由SiC、SiN或SiON制成。在一些实施例中，蚀刻停止层205的厚度在约200nm到约800nm的范围内。ILD层206可以由氧化硅或具有低介电常数(低k)的介电材料制成。可以掺杂ILD层206。在一些实施例中，ILD层206的k值小于3.5。在一些实施例中，ILD层206的k值小于2.5。在一些实施例中，ILD层206的厚度在约700nm到约1000nm的范围内。
形成介电堆叠件204之后，图案化介电堆叠件204以形成用于金属焊盘127的开口208。图案化工艺包括在衬底201上方施加光刻胶层、光刻工艺和蚀刻工艺。图2A示出了图案化之后的介电堆叠件204。在一些实施例中，开口208的厚度W2在约10μm到约50μm的范围内。在一些实施例中，介电堆叠件204的高度D2在约100nm到约3000nm的范围内。
根据一些实施例，如图2B所示，图案化介电堆叠件204之后，形成势垒晶种层209以覆盖介电堆叠件204的表面并且覆盖(line)开口208。在一些实施例中，势垒晶种层209包括势垒子层和喷镀的晶种子层。势垒子层用于避免铜扩散，且晶种子层用于使能随后的镀铜。在一些实施例中，势垒子层由Ti、TiN、Ta、TaN或它们的组合制成。在一些实施例中，势垒子层的厚度在约10nm到约100nm的范围内。在一些实施例中，喷镀的晶种子层由Cu或Cu合金制成。在一些实施例中，喷镀的晶种子层在约100nm到约500nm的范围内。在一些实施例中，势垒子层和喷镀晶种层都是由物理汽相沉积(PVD)工艺、原子层沉积(ALD)工艺和其他可应用的工艺形成。
如图2C所示，形成势垒晶种层209之后，将铜层210沉积在势垒晶种层209上方且填充开口208的剩余部分。在一些实施例中，通过喷镀工艺形成铜层210。铜层210也沉积在开口208的外侧。需要去除铜层210。在一些实施例中，如图2D所示，通过化学机械抛光(CMP)工艺220去除位于开口208外侧的过量的铜层210和势垒晶种层209。去除开口208外侧的过量的铜层210和势垒晶种层209之后，形成金属焊盘127。
如上所述，在一些实施例中，开口208的厚度W2在约10μm到约50μm的范围内。开口208的宽度W2是金属焊盘127的宽度。如图2D所示，由于金属焊盘127的宽度，CMP工艺220能够引起金属焊盘127凹陷。图2D示出了金属焊盘127的中心由于CMP凹陷效应低于金属焊盘127的边缘。金属焊盘127的凹陷能够引起形成在金属焊盘127上方的通孔之间的金属纵梁，这将会引起短路和或降低良品率的可靠性问题。
形成金属焊盘127之后，实施额外的工艺以完成上述互连结构122和凸块结构(诸如，μ凸块112)的形成。然后，将衬底121的背侧接地以暴露TSV 125。之后，形成导电结构129和钝化层124。
为了减少凹陷效应，应该将介电结构插入金属焊盘，诸如金属焊盘127。图3A根据一些实施例示出了具有嵌入的介电结构212和213的金属焊盘127’。介电结构212和213由未蚀刻的介电堆叠件204制成。图3A示出了下面的TSV 125的4个可能的位置214(由虚线圆标出)。如上所述，在金属焊盘127和UBM结构129之间需要2个或更多TSV。对于每个金属焊盘127，两个或多个位置214连接到TSV 125。将位置124置于金属焊盘127’的角附近，这是因为角区域较少受到CMP凹陷效应的影响。环绕并包括金属焊盘127’的位置214的区域215(由虚线标出)不包括嵌入的介电结构以在连接至TSV 125中提供低的电阻率和好的导电性。
金属焊盘127’的中心最有可能受到凹陷效应的影响。因此，将大介电结构213嵌入到金属焊盘127’的中心区域。在一些实施例中，将金属焊盘127’成形为宽度为WM的正方形。金属焊盘127’需要足够大以覆盖TSV 125且为连接至其的结构提供足够低的电阻。在一些实施例中，WM在约30μm到约50μm的范围内。介电结构213的宽度是WD。为了避免金属焊盘127’的中心附近的凹陷效应，WD不能太小。在一些实施例中，WD/WM的比率在约1/4到约1/2的范围内。在一些实施例中，WD在约10μm到约25μm的范围内。
为了避免相邻的区域215之间的区域217的凹陷，将介电结构212嵌入。图3A示出了形成在每个区域127中的两个介电结构(条)212。在一些实施例中，每个介电结构(条)212的长度L212约等于介电结构213的宽度WD。然而，介电结构212的长度L212可以宽于或窄于介电结构213的宽度WD。介电结构212均匀地分布在区域217中。在一些实施例中，介电结构212的宽度W212在区域217的长度L217的约1/5到约1/4之间。在一些实施例中，W212在约2μm到约5μm的范围内。
所描述的具有嵌入的介电结构212、213的金属焊盘127’是一个实施例。其他实施例也是可能的。图3B根据一些其他实施例示出了金属焊盘127”。金属焊盘127”还包括介电结构以减少CMP凹陷效应。将介电结构配置为不同于金属焊盘127’。金属焊盘127”包括介电结构212”和213”。介电结构213”类似于介电结构213。每个区域217”包括一个介电结构212”，取代了图3A中的两个结构。介电结构212”宽于介电结构212。在一些实施例中，介电结构212”的宽度W212”在区域217”的长度L217”的约1/2和约2/3之间。在一些实施例中，W212”在约2μm到约5μm的范围内。在一些实施例中，每个介电结构(条)212”的宽度W212”约等于介电结构213”的宽度WD”。然而，介电结构212”的宽度W212”可以宽于或窄于介电结构213”的宽度WD”。图3A和图3B示出了分别位于区域217和217”中的一个或两个介电结构。在这些区域中，可以具有多于两个的介电结构。此外，可以将这些区域中的介电结构成形且布置为不同于上文所述。研究示出上文所述的嵌入式的介电结构将凹陷效应减少为不存在或几乎不存在。因此，消除了通孔之间的金属纵梁的危害。
图4A根据一些实施例示出了导电结构400的立体图。导电结构400包括用于TSV 125和UBM结构129的金属焊盘127。如上所述，凸块(126)(可以是C4凸块)连接到UBM结构129(未示出)。图4B根据一些实施例示出了导电结构400的顶视图。由于凸块126的大尺寸，与金属焊盘127相比，UBM结构129较大。图4B示出了具有顶视图为八角形的UBM结构129。在一些实施例中，UBM结构129的宽度WU在约80μm到约100μm的范围内。UBM结构129的宽度WU大于金属焊盘127的宽度WM。在一些实施例中，WM(金属焊盘的宽度)对WU(用于凸块126的UBM结构129的宽度)的比率在约1/3到约1/2的范围内。
在图4A和图4B中的导电结构400包括4个TSV 125。如上所述，连接金属焊盘127和用于凸块126的UBM结构129的TSV 125的数量应该是大于1以确保好的良品率。然而，根据制造的需要，TSV 125的数量可以是2、3或4。
图5根据一些实施例示出了形成3DIC结构的工艺流程。在形成插入件120’之后开始该工艺。在操作510中，将一个或多个管芯(诸如，管芯110A和/或110B)接合至具有插入件(诸如，插入件120’)的衬底。在将管芯110A和/或110B接合至具有插入件120’的衬底之后，施加底部填充胶143以填充管芯110A和/或110B和插入件120’之间的空间。形成底部填充胶143之后，形成模塑料144以覆盖插入件120’暴露的表面且填充管芯110A和/或110B之间的空间。然后，在操作520中，实施锯切以将具有接合的管芯的插入件分割为单独的管芯封装件。每个管芯封装件包括管芯110A和/或110B和插入件120’。然后，在操作530中，将管芯封装件接合至衬底130’。在将管芯封装件接合至衬底130’之后，将底部填充胶146填充在管芯封装件和衬底130’之间的空间以形成3DIC管芯封装件100’。
提供了用于形成三维集成电路(3DIC)结构的机制的各种实施例。3DIC结构包括接合至管芯的插入件和衬底。插入件具有连接到图案化的金属焊盘的穿透硅通孔(TSV)的导电结构和位于TSV的相对端的导电结构。图案化的金属焊盘具有嵌入其中的介电结构以减少凹陷效应，并具有位于TSV上方的没有介电结构的区域。导电结构具有2个或多个TSV。通过使用图案化的金属焊盘和2个或更多的TSV，提高了导电结构和3DIC结构的可靠性和良品率。
在一些实施例中，提供了一种插入件结构。该插入件结构包括两个或多个穿透硅通孔(TSV)和图案化的金属焊盘。两个或多个TSV物理连接至图案化的金属焊盘，且图案化的金属焊盘具有嵌入式的介电结构。嵌入式的介电结构不会超过两个或多个TSV。插入件结构还包括物理连接至两个或多个TSV的与图案化的金属焊盘相对的端的导电结构。
在一些实施例中，提供了一种封装件。该封装件结构包括半导体管芯和连接至半导体管芯的插入件结构。该插入件结构还包括两个或多个穿透硅通孔(TSV)和图案化的金属焊盘。两个或多个TSV物理连接至图案化的金属焊盘，且图案化的金属焊盘具有嵌入式的介电结构。嵌入式的介电结构没有位于两个或多个TSV上方。封装件结构还包括物理连接至两个或多个TSV的与图案化的金属焊盘相对的端的导电结构。此外，封装件结构包括连接至插入件的衬底。
在还有的一些其他实施例中，提供了一种形成插入件结构的方法。该方法包括形成位于衬底中的两个或多个穿透硅通孔(TSV)以及形成图案化的金属焊盘。两个或多个TSV物理连接至图案化的金属焊盘，且图案化的金属焊盘具有嵌入式的介电结构。嵌入式的介电结构没有位于两个或多个TSV上方。该方法还包括研磨衬底的背侧以暴露两个或多个TSV，且在结构的背侧上形成导电结构。该导电结构物理连接至两个或多个TSV。
尽管已经详细地描述了本发明的实施例及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、手段、方法和步骤的特定实施例。作为本领域普通技术人员应理解，根据本发明，可以使用现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造、材料组分、手段、方法或步骤。因此，所附权利要求意在包括这些工艺、机器、制造、材料组分、手段、方法或步骤的范围。此外，每个权利要求构成一个独立的实施例，且各个权利要求和实施例的组合在本发明的范围内。

Claims (10)

1.一种插入件结构，包括：
两个或多个穿透硅通孔(TSV)；
图案化金属焊盘，其中，所述两个或多个TSV物理连接至所述图案化金属焊盘，其中，所述图案化金属焊盘具有嵌入式介电结构，其中，所述嵌入式介电结构不在所述两个或多个TSV的上方；以及
导电结构，物理连接至所述两个或多个TSV的与所述图案化金属焊盘相对的端。
2.根据权利要求1所述的插入件结构，其中，所述图案化金属焊盘的所述嵌入式介电结构具有位于所述图案化金属焊盘的中心的第一介电结构，其中，所述第一介电结构的宽度与所述图案化金属焊盘的宽度的比率在约1/4和约1/2的范围内。
3.根据权利要求1所述的插入件结构，其中，所述图案化金属焊盘包括多个没有所述嵌入式介电结构的区域，其中，所述多个没有所述嵌入式介电结构的区域位于各个所述TSV上方。
4.根据权利要求3所述的插入件结构，其中，所述多个没有所述嵌入式介电结构的区域位于所述图案化金属焊盘的各个角处。
5.根据权利要求3所述的插入件结构，其中，所述图案化金属焊盘被成形为正方形，且所述多个没有所述嵌入式介电结构的区域包括位于所述图案化金属焊盘的各个角处的四个区域。
6.根据权利要求3所述的插入件结构，其中，所述嵌入式介电结构包括位于所述多个没有所述嵌入式介电结构的区域的两个相邻区域之间的第二介电结构。
7.根据权利要求3所述的插入件结构，其中，所述嵌入式介电结构包括位于所述多个没有所述嵌入式介电结构的区域的两个相邻区域之间的多于1个的介电结构。
8.根据权利要求3所述的插入件结构，其中，所述图案化金属焊盘的所述嵌入式介电结构包括位于所述图案化金属焊盘的中心的第一介电结构，且包括位于所述多个没有所述嵌入式介电结构的区域的两个相邻区域之间的多于1个的介电结构。
9.一种封装件结构，包括：
半导体管芯；
插入件结构，连接至所述半导体管芯，所述插入件结构还包括：
两个或多个穿透硅通孔(TSV)；
图案化金属焊盘，其中，所述两个或多个TSV物理连接至所述图案化金属焊盘，其中，所述图案化金属焊盘具有嵌入式介电结构，其中，所述嵌入式介电结构没有超过所述两个或多个TSV，以及
导电结构，物理连接至所述两个或多个TSV的与所述图案化金属焊盘相对的端；以及
衬底，连接至所述插入件。
10.一种形成插入件结构的方法，包括：
在衬底中形成两个或多个穿透硅通孔(TSV)；
形成图案化金属焊盘，其中，所述两个或多个TSV物理连接至所述图案化金属焊盘，其中，所述图案化金属焊盘具有嵌入式介电结构，其中，所述嵌入式介电结构不在所述两个或多个TSV上方；
研磨所述衬底的背侧以暴露所述两个或多个TSV；以及
在所述结构的背侧上形成导电结构，其中，所述导电结构物理连接至所述两个或多个TSV。
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