TW201515172A - 矽中介板結構、封裝體結構以及矽中介板結構的製造方法 - Google Patents

矽中介板結構、封裝體結構以及矽中介板結構的製造方法 Download PDF

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TW201515172A
TW201515172A TW103116197A TW103116197A TW201515172A TW 201515172 A TW201515172 A TW 201515172A TW 103116197 A TW103116197 A TW 103116197A TW 103116197 A TW103116197 A TW 103116197A TW 201515172 A TW201515172 A TW 201515172A
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Taiwan
Prior art keywords
metal pad
patterned metal
turns
dielectric
dielectric structures
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TW103116197A
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English (en)
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TWI553802B (zh
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Tzuan-Horng Liu
Shih-Wen Huang
Chung-Yu Lu
Hsien-Pin Hu
Shang-Yun Hou
Shin-Puu Jeng
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Taiwan Semiconductor Mfg Co Ltd
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Publication of TW201515172A publication Critical patent/TW201515172A/zh
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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Abstract

本發明提供三維積體電路(3DIC)結構及其製造方法的各種實施例。三維積體電路結構包括接合至一晶片與一基板的一矽中介板。矽中介板具有包含連接至一圖案化金屬墊的矽穿孔(through silicon vias,TSVs)的導電結構，以及位於矽穿孔相對端面的導電結構。於圖案化的金屬墊內嵌入介電結構以減少碟化效應，且圖案化的金屬墊具有不存在介電結構的區域，其位於矽穿孔之上。導電結構具有2個或多個矽穿孔。藉由使用圖案化的金屬墊與2個或多個矽穿孔，可改善導電結構與三維積體電路結構的可靠度及良率。

Description

矽中介板結構、封裝體結構以及矽中介板結構的製造方法
本發明係有關一種半導體技術，且特別有關一種連接至複數個矽穿孔的圖案化的金屬墊及其製造方法。
半導體裝置可用於各種電子應用，例如個人電腦、手機、數位相機以及其他的電子設備。一般來說，半導體裝置的製造係依序於半導體基板上沉積絕緣或是介電層、導電層與半導體層的材料，並藉由微影製程圖案化上述不同的材料層，以於半導體基板上形成電路部件與元件。
半導體產業藉由持續減少最小特徵尺寸來持續提昇各種電子部件(例如電晶體、二極體、電阻、電容等)的集積度，以使更多的部件可整合至既有的區域。在一些應用中，這些較小的電子部件亦需要較小的封裝體，其較先前的封裝體佔用較少的面積及/或具有較低的高度。
三維積體電路(3DICs)已被製造來進一步縮小集積的晶片及封裝體。已開始發展新的封裝技術，以使三維積體電路成為可能。這些用於半導體的相對新型的封裝技術將面臨製 造上的挑戰。
本發明之實施例係揭示一種矽中介板結構，包括：兩個或多個矽穿孔(TSVs)；一圖案化的金屬墊，其中矽穿孔物理連接至圖案化的金屬墊，其中圖案化的金屬墊具有複數個嵌入式介電結構，其中嵌入式介電結構不在矽穿孔之上；以及一導電結構，其物理連接至矽穿孔，且其位在圖案化的金屬墊的相對端面上。
本發明之另一實施例係揭示一種封裝體結構，包括：一半導體晶片；一矽中介板結構，其連接至半導體晶片，包括：兩個或多個矽穿孔(TSVs)；一圖案化的金屬墊，其中矽穿孔物理連接至圖案化的金屬墊，其中圖案化的金屬墊具有複數個嵌入式介電結構，其中嵌入式介電結構不在矽穿孔之上；以及一導電結構，其物理連接至矽穿孔，且其位在圖案化的金屬墊的相對端面上；以及一基板，其連接至矽中介板。
本發明之又另一實施例係揭示一種矽中介板結構的製造方法，包括：於一基板內形成兩個或多個矽穿孔(TSVs)；形成一圖案化的金屬墊，其中矽穿孔物理連接至圖案化的金屬墊，其中圖案化的金屬墊具有複數個嵌入式介電結構，其中嵌入式介電結構不在矽穿孔之上；研磨基板的一背側，以露出矽穿孔；以及於基板的背側上形成一導電結構，其中導電結構物理連接至矽穿孔。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳 細說明如下：
100、100’‧‧‧封裝結構
109A、119、127、127’、127”、131‧‧‧金屬墊
110、110A、110B‧‧‧晶片
111A、112‧‧‧微凸塊
113A、114‧‧‧銅柱
115、115A、115B‧‧‧連接體(或接合結構)
116A、117、129‧‧‧凸塊下金屬結構
118A‧‧‧焊料層
120、120’‧‧‧矽中介板
121‧‧‧矽基板
122‧‧‧內連結構
124、132、141、142‧‧‧鈍化護層
125‧‧‧矽穿孔
126‧‧‧凸塊
130、130’‧‧‧基板
143‧‧‧底膠
144‧‧‧模封化合物
201‧‧‧介電襯墊層
202‧‧‧阻障層
203‧‧‧導電層
204‧‧‧介電堆疊層
205‧‧‧蝕刻停止層
206‧‧‧內層介電層
208‧‧‧開口
209‧‧‧阻障-晶種層
210‧‧‧銅層
212、212”、213、213”‧‧‧嵌入式介電結構
214‧‧‧位置
215、217、217”‧‧‧區域
220‧‧‧化學機械研磨製程
400‧‧‧導電結構
500‧‧‧方法
510、520、530‧‧‧操作步驟
D1‧‧‧溝槽深度
D2‧‧‧介電堆疊層的高度
L212‧‧‧介電結構212的長度
L212”‧‧‧介電結構212”的長度
L217‧‧‧區域217的長度
L217”‧‧‧區域217”的長度
M1、M2、M3‧‧‧金屬線
V1、V2、V3‧‧‧介層窗
W1‧‧‧溝槽寬度
W2‧‧‧開口寬度
WD‧‧‧介電結構213的寬度
WD”‧‧‧介電結構213”的寬度
W212‧‧‧介電結構212的寬度
W212”‧‧‧介電結構212”的寬度
W217‧‧‧區域217的寬度
WM‧‧‧金屬墊的寬度
WU‧‧‧凸塊下金屬結構的寬度
第1A圖繪示出根據一些實施例之一封裝結構的立體示意圖。
第1B圖繪示出根據一些實施例之一三維積體電路(3DICs)結構的剖面示意圖。
第1C圖繪示出根據一些實施例之介於一晶片與一矽中介板(silicon interposer)之間的一連接體(或接合結構)的剖面示意圖。
第2A-2D圖繪示出根據一些實施例，於複數個矽穿孔上形成一金屬墊的連續製程的剖面示意圖。
第3A圖繪示出根據一些實施例之一金屬墊的平面示意圖。
第3B圖繪示出根據一些其他的實施例之一金屬墊的平面示意圖。
第4A圖繪示出根據一些實施例之一導電結構的立體示意圖。
第4B圖繪示出根據一些實施例之一導電結構的平面示意圖。
第5圖為根據一些實施例，一三維積體電路的製造流程圖。
以下將詳細說明本發明實施例之製造與使用方式。然而，應注意的是本發明提供許多可供應用的發明概念，其可以多種特定型式實施。這些特定的實施例僅為示例性，而 非用以限制本發明的範圍。
自積體電路發明以來，由於各種電子部件(即，電晶體、二極體、電阻、電容等)之集積度不斷的改良，半導體產業已經歷持續且快速的成長。主要來說，這些集積度的改良來自於最小特徵尺寸一再的微縮，使得更多部件能被整合至既有的區域。
由於集積部件所佔據的體積基本上位於半導體晶圓的表面，此種集積度的改良本質上為二維(2D)的形式。雖然微影製程的大幅進步使二維積體電路製造有顯著的改良，在二維中所能達到的密度仍有其物理限制。其中一種限制為製造這些部件所需的最小尺寸。此外，當更多裝置置於同一晶片中時，亦需要更複雜的設計。
三維積體電路(3DICs)因此被製造來解決上述限制。在一些三維積體電路的製程中，可形成兩個或多個的晶圓，其中每一晶圓包括一積體電路。接著，切割上述晶圓以形成複數個晶片。具有不同裝置的晶片將被封裝，並接著接合至已對準的裝置。矽穿孔(through silicon vias,TSVs)與封裝穿孔(through-package-vias,TPVs)(亦稱之為模封穿孔(through-molding-vias,TMVs))逐漸用以作為實施三維積體電路的方式。矽穿孔與封裝穿孔常用於三維積體電路與堆疊的晶片，其可提供電性連接及/或幫助熱量散出。
第1A圖繪示出根據一些實施例之一封裝結構100的立體示意圖，其包括接合至一矽中介板(silicon interposer)120的一晶片110，矽中介板120並進一步接合至其他 的基板130。在將晶片(die)110接合至矽中介板120之後，可將封裝結構切割成個別的部分，而矽中介板120將可視作為半導體晶粒。每一晶片110與矽中介板120包括用於半導體積體電路製造的一半導體基板，而積體電路可形成於半導體基板之中及/或之上。半導體基板所指為包括半導體材料的任何結構，其包括但不限於塊體(bulk)矽、半導體晶圓、絕緣層上覆矽(silicon-on-insulator,SOI)基板或矽鍺基板。亦可使用其他半導體材料，其包括III族、IV族與V族元素。半導體基板可更包括複數個絕緣特徵部件(未繪示)，例如淺溝槽絕緣(shallow trench isolation,STI)特徵部件或區域矽氧化物(local oxidation of silicon,LOCOS)特徵部件。絕緣特徵部件可定義及隔離不同的微電子元件。可形成於半導體基板內的各種微電子元件包括電晶體(如，金氧半場效電晶體(metal oxide semiconductor field effect transistor,MOSFET)、互補式金氧半(complementary metal oxide semiconductor,CMOS)電晶體、雙極性接面電晶體(bipolar junction transistor,BJT)、高壓電晶體、高頻電晶體、p通道及/或n通道場效電晶體(PFETs/NFETs)等)、電阻、二極體、電容、電感、熔絲及其他適合的元件。可實施不同製程以形成各種微電子元件，其包括沉積、蝕刻、佈植、微影、退火及/或其他適合的製程。可將微電子元件彼此連接以形成積體電路裝置，例如邏輯裝置、記憶體裝置(如，SRAM)、射頻裝置、開/關(I/O)裝置、系統單晶片(system-on-chip，SoC)裝置、上述之組合及其他適合的裝置種類。根據一些實施例，矽中介板120包括矽穿孔(TSVs)或封裝穿孔(TPVs)，其可用於轉接其 他部件。在一些實施例中，矽中介板120不包括主動元件。
基板130可由雙順丁烯二酸醯亞胺(bismaleimide triazine,BT)樹脂、FR-4(一種由具有耐火(flame resistant)的環氧樹脂黏結劑(binder)的玻璃纖維織物所構成的複合材料)、陶瓷、玻璃、塑膠、膠帶、薄膜或其他可承載用於連接導電端子的導電墊或區域的支撐材料。在一些實施例中，基板130為多層電路板。在一些實施例中，基板130包括內連結構。
晶片110藉由連接體(或接合結構)115接合至矽中介板120，且矽中介板120藉由連接體145接合至基板130。若將具有不同尺寸的連接體的兩個或多個晶片(如晶片110與其他(複數個)晶片)接合至矽中介板120，其封裝方式將是一大挑戰。矽中介板120內的矽穿孔有助於電性連接與熱量散出。
第1B圖繪示出根據一些實施例，一晶片封裝體100’的剖面示意圖。晶片封裝體100’包括一晶片110A與一晶片110B。舉例來說，晶片110A可為中央處理器(central processing unit,CPU)或繪圖處理器(graphic processing unit,GPU)，且晶片110B可為記憶體裝置，如靜態隨機存取記憶體(static random-access memory,SRAM)、動態隨機存取記憶體(dynamic random-access memory,DRAM)或其他類型的記憶體裝置。晶片110A與110B可分別藉由連接體115A與115B連接至基板(或矽中介板)120’。連接體115A與115B為接合結構，其藉由將用於晶片110A與110B的外部連接體接合至矽中介板120’的外部連接體來形成。在一些實施例中，連接體(或接合結構)115A與115B可藉由接合晶片110A與110B上的微凸塊(μ-bumps)與矽中介板 120’的微凸塊112來形成。第1C圖繪示出根據一些實施例，將晶片110A上的微凸塊111A接合至矽中介板120’的微凸塊112以形成連接體(或接合結構)115A。微凸塊111A包括一銅柱113A、一凸塊下金屬(under-bump metallurgy,UBM)層116A與一焊料層，焊料層接合至微凸塊112的焊料層以形成焊料層118A。微凸塊112亦包括一銅柱114與一凸塊下金屬層117。微凸塊111A係形成於金屬墊109A上，且微凸塊112係形成於金屬墊119上。
在一些實施例中，凸塊下金屬層116A與117包括由鈦所形成的擴散阻障層以及由銅所形成的晶種層。在一些實施例中，可藉由物理氣相沉積(physical vapor deposition,PVD)(或濺鍍)來沉積擴散阻障層(例如鈦層)與晶種層(例如銅層)兩者。在回流製程之後，將連接於微凸塊上的焊料層彼此接合，以形成一焊料層，例如焊料層118A。微凸塊111A的一部份位於鈍化護層141上，且微凸塊112的一部份位於鈍化護層142上。鈍化護層141與142由介電材料所構成，其可提供隔離且能吸收接合應力。在一些實施例中，鈍化護層141與142由高分子所構成，例如聚亞醯胺、聚苯噁唑(polybenzoxazole，PBO)或防焊層。
接合結構及其製造方法的範例詳述於美國專利申請號13/427,753(名稱「用於多晶片封裝之凸塊結構」，申請日2012年3月22日)、美國專利申請號13/338,820(名稱「半導體封裝裝置與封裝半導體裝置的方法」，申請日2011年12月28日)以及美國專利申請號13/667,306(名稱「用於封裝體與基板的接合結構」，申請日2012年11月2日)。上述專利案的全部內容在 此引用作為參考。
第1B圖繪示出矽中介板120’包括具有矽穿孔125的矽基板121。矽中介板120’包括位於矽基板121一側的內連結構122，以及位於內連結構122相對側的凸塊126。凸塊126類似於第1A圖的連接體145。內連結構122將矽穿孔125連接至外部連接體(如，微凸塊112)。內連結構包括導電內連結構，例如金屬墊、金屬線與介層窗。可藉由介電層來隔離導電內連結構。舉例來說，導電內連結構包括金屬線(例如M1、M2與M3)以及介層窗(例如V1、V2與V3)。導電內連結構亦包括金屬墊，例如金屬墊127與119。在一些實施例中，金屬墊127形成於M1層位。金屬墊127連接至矽穿孔125，且金屬墊119連接至微凸塊112。矽穿孔125連接至各自的凸塊下金屬結構(導電結構)129，其中凸塊下金屬結構(導電結構)129連接至凸塊126。在一些實施例中，凸塊126為C4凸塊，其由焊料所構成。凸塊下金屬結構129由導電材料所構成。導電材料可藉由物理氣相沉積(PVD)、原子層沉積(atomic layer deposition,ALD)、化學氣相沉積(chemical vapor deposition,CVD)、電化學電鍍或上述之組合來形成。舉例來說，導電材料包括但不限於鈦、鎳、銅、鎢、鋁、銀、金或上述之組合。在一些實施例中，凸塊下金屬結構由鈦所構成。凸塊下金屬結構129可藉由鈍化護層124而彼此分隔。在一些實施例中，鈍化護層124可由高分子所構成，例如聚亞醯胺、聚苯噁唑(PBO)或防焊層。鈍化護層124可由介電或高分子材料所構成，藉此可保護矽中介板120’與凸塊126免於受到接合應力的影響。
矽中介板120’可藉由凸塊126連接至基板130’。每一凸塊126連接至矽中介板120'上的凸塊下金屬結構129，且每一凸塊126連接至基板130'上的金屬墊131。金屬墊131可藉由鈍化護層132而彼此分隔。鈍化護層132可由高分子所構成，例如聚亞醯胺、聚苯噁唑(PBO)或防焊層。鈍化護層132可由介電或高分子材料所構成，藉此保護矽中介板120’與基板130’免於受到來自接合製程的接合應力的影響。
第1B圖繪示出至少兩個矽穿孔125連接至矽中介板120’上的金屬墊127與凸塊下金屬結構129。兩個或多個連接至矽中介板120’上的金屬墊127與凸塊下金屬結構129的多重矽穿孔(multiple TSVs)125較一個矽穿孔125更為理想，因其改善了當其中一個所連接的矽穿孔125出錯時的良率。舉例來說，矽穿孔125可能與金屬墊127或凸塊下金屬結構129接觸不良。使用兩個或多個矽穿孔來連接金屬墊127與凸塊下金屬結構129可改善錯誤容忍度及良率。
第1B圖亦繪示出形成於晶片110A、110B與矽中介板120’之間的底膠(underfill)143。底膠146可形成於矽中介板120’與基板130’之間。底膠143可保護連接體(或接合結構)115A與115B。類似地，底膠146可保護凸塊126。第1B圖亦繪示出形成模封化合物(molding compound)144以圍繞、覆蓋並保護晶片110A、110B及矽中介板120’。
如上所述，矽穿孔125連接至金屬墊127。於基板121內形成矽穿孔125之後，於矽穿孔125上形成金屬墊127。第2A-2D圖繪示出根據一些實施例，於矽穿孔125上形成金屬墊 127的連續製程的剖面示意圖。第2A圖繪示出於基板121內形成矽穿孔125。矽穿孔125的製造包括形成深溝槽。根據一些實施例，用於矽穿孔125的溝槽寬度W1介於約5μm至15μm之間。根據一些實施例，用於矽穿孔125的溝槽深度D1介於約40μm至120μm之間。接著，沿著溝槽的側壁與基板121的表面形成介電襯墊層201，如第2A圖所示。在一些實施例中，介電襯墊層201由氧化矽所構成。在一些實施例中，介電襯墊層201的厚度介於約0.3μm至1.5μm之間。
接著，於介電襯墊層201上沉積一阻障層202。阻障層202可由鈦、鉭、氮化鈦、氮化鉭或上述之組合所構成。在一些實施例中，阻障層202的厚度介於約0.05μm至0.5μm之間。接著，將導電層203填入溝槽的剩餘部分，導電層203可由具有低電阻值的導電材料所構成，例如銅、銅合金、鋁、鋁合金或其他合適的材料。在一些實施例中，(在基板表面上方的)導電層203的厚度介於約4μm至14μm之間。接著，藉由例如化學機械研磨(chemical mechanical polishing,CMP)製程以去除在溝槽外側的多餘的導電層203與202。矽穿孔125係形成如第2A圖所示。
在形成矽穿孔125之後，於露出的介電襯墊層201與矽穿孔125的上表面上形成介電堆疊層204。在一些實施例中，介電堆疊層204包括蝕刻停止層205與內層介電(inter-level dielectric,ILD)層206。在一些實施例中，蝕刻停止層205由碳化矽、氮化矽或氮氧化矽所構成。在一些實施例中，蝕刻停止層205的厚度介於約200nm至800nm之間。內層介電層206可由 氧化矽或具有低介電常數(low-k)的介電材料所構成。內層介電層206中可具有摻雜物。在一些實施例中，內層介電層206的k值小於3.5。在一些實施例中，內層介電層206的k值小於2.5。在一些實施例中，內層介電層206的厚度介於約700nm至1000nm之間。
在形成介電堆疊層204之後，圖案化介電堆疊層204以形成用於金屬墊127的開口208。圖案化製程包括於基板201上施加光阻層、微影製程與蝕刻製程。第2A圖繪示出圖案化之後的介電堆疊層204。在一些實施例中，開口208的寬度W2介於約10μm至50μm之間。在一些實施例中，介電堆疊層204的高度D2介於約100nm至3000nm之間。
根據一些實施例，在圖案化介電堆疊層204之後，形成阻障-晶種層209以覆蓋介電堆疊層204的表面，阻障-晶種層209亦是沿著開口208形成，如第2B圖所示。在一些實施例中，阻障-晶種層209包括一阻障次層與一電鍍晶種次層。阻障次層係用於防止銅擴散，而晶種次層係用於後續的銅電鍍製程。在一些實施例中，阻障次層由鈦、氮化鈦、鉭、氮化鉭或上述之組合所構成。在一些實施例中，阻障次層的厚度介於約10nm至100nm之間。在一些實施例中，電鍍晶種次層由銅或銅合金所構成。在一些實施例中，電鍍晶種次層的厚度介於約100nm至500nm之間。在一些實施例中，每一阻障次層與電鍍晶種層可藉由物理氣相沉積(PVD)、原子層沉積(ALD)或其他合適的製程來形成。
在形成阻障-晶種層200之後，於阻障-晶種層209 上沉積銅層210，並將其填入開口208的剩餘部分，如第2C圖所示。在一些實施例中，銅層210可藉由電鍍法來形成。銅層210亦會沉積於開口208外側。上述的銅層210需要將其去除。在一些實施例中，在開口208外側的多餘的銅層210與阻障-晶種層209可藉由化學機械研磨(CMP)製程220來去除，如第2D圖所示。在去除在開口208外側的多餘的銅層210與阻障-晶種層209之後，將形成金屬墊127。
如上所述，在一些實施例中，開口208的寬度W2介於約10μm至50μm之間。開口208的寬度W2即金屬墊127的寬度。如第2D圖所示，化學機械研磨製程220可能受到金屬墊127的寬度影響，而使金屬墊127呈現碟化(dishing)。第2D圖繪示出由於化學機械研磨的碟化效應，金屬墊127的中央低於金屬墊127的邊緣。碟化的金屬墊127可能導致形成於金屬墊上的介層窗之間有金屬殘留(metal residue)現象，其可能造成短路及/或可靠度問題而降低良率。
在形成金屬墊127之後，實施額外的製程以完成內連結構122與凸塊結構(如，上述之微凸塊112)的製造。接著，研磨基板121的背側以露出矽穿孔125。接著，形成導電結構129與鈍化護層124。
為了減少碟化效應，可於金屬墊(如，金屬墊127)中插入介電結構。第3A圖繪示出根據一些實施例，具有嵌入式介電結構212與213的金屬墊127’。介電結構212與213可由未蝕刻掉的介電堆疊層204所構成。第3A圖繪示出下方具有矽穿孔125的的4個可能的位置214(標示為虛線圓圈)。如上所述，金屬 墊127與凸塊下金屬結構129之間需要2個或多個矽穿孔。對每一金屬墊127而言，兩個或多個位置214係連接於矽穿孔125。由於金屬墊127’的角落區域較不易受化學機械研磨的碟化效應影響，位置214係設置於靠近金屬墊127’的角落。金屬墊127’中圍繞且包括位置214的區域215(標示為虛線直線)不包括嵌入式介電結構，以提供低電阻與良好的導電性來連接矽穿孔125。
金屬墊127’的中央最可能受到碟化效應的影響。因此，大的介電結構213將嵌入至金屬墊127’的中央區域。在一些實施例中，金屬墊127’的形狀為寬度WM的正方形。金屬墊127’需要夠大以覆蓋矽穿孔125，且能為其所連接的結構提供夠低的電阻。在一些實施例中，WM介於約30μm至50μm之間。介電結構213的寬度為WD。為了避免靠近金屬墊127’中央的碟化效應，WD不能太小。在一些實施例中，WD/WM的比值介於約1/4至1/2之間。在一些實施例中，WD介於約10μm至25μm之間。
為了避免相鄰區域215之間的區域217受到碟化效應的影響，可將介電結構212嵌入其中。第3A圖繪示出在每一區域217內形成兩個介電結構(長方塊)212。在一些實施例中，每一介電結構(長方塊)212的長度L212約等於介電結構213的寬度WD。然而，介電結構212的長度L212可較介電結構213的寬度WD更寬或更窄。介電結構212係平均分配在區域217內。在一些實施例中，介電結構212的寬度W212介於約1/5至1/4的區域217的長度L217。在一些實施例中，W212介於約2μm至5μm之間。
上述之具有嵌入式介電結構212、213的金屬墊127’ 為本發明的一種實施例。其他類型的實施例亦可能存在。第3B圖繪示出根據一些其他的實施例之金屬墊127”。金屬墊127”亦包括介電結構以減少化學機械研磨的碟化效應。上述介電結構的設置不同於金屬墊127’。金屬墊127”包括介電結構212”與213”。介電結構213”類似於介電結構213。每一區域217”包括一個介電結構212”，而非第3A圖所繪示之兩個結構。介電結構212”較介電結構212更寬。在一些實施例中，介電結構212”的寬度W212”介於約1/2至2/3的區域217”的長度L217”。在一些實施例中，W212”介於約2μm至5μm之間。在一些實施例中，每一介電結構(長方塊)212”的長度L212”約等於介電結構213”的寬度WD”。然而，介電結構212”的長度L212”可較介電結構213”的寬度WD”更寬或更窄。
第3A與3B圖繪示出在區域217與217”內分別具有一個或兩個介電結構。這些區域內亦可存在多於兩個介電結構。此外，這些區域內的介電結構的外型與配置可不同於上述之介電結構。研究顯示上述之嵌入式介電結構可降低碟化效應至不存在或幾乎不存在。因此，可消除介層窗之間的金屬殘留(metal residue)。
第4A圖繪示出根據一些實施例之導電結構400的立體示意圖。導電結構400包括金屬墊127、四個矽穿孔125與凸塊下金屬結構129。如上所述，凸塊126可為C4凸塊，且其可連接至凸塊下金屬結構129(未繪示)。第4B圖繪示出根據一些實施例之導電結構400的平面示意圖。由於凸塊126有大的尺寸，凸塊下金屬結構129較金屬墊127更大。第4B圖繪示出凸塊 下金屬結構129自上方俯視的形狀為八邊型。在一些實施例中，凸塊下金屬結構129的寬度WU介於約80μm至100μm之間。凸塊下金屬結構129的寬度WU大於金屬墊127的寬度WM。在一些實施例中，金屬墊的寬度WM與用於凸塊126的凸塊下金屬結構129的寬度WU的比值介於約1/3至1/2。
第4A與4B圖的導電結構400包括四個矽穿孔125。如上所述，連接金屬墊127與用於凸塊126的凸塊下金屬結構129的矽穿孔125的數量應多於一個，以確保有好的良率。然而，矽穿孔125的數量可為2、3或4個，其取決於製程需求。
第5圖為根據一些實施例之形成三維積體電路結構的流程圖。製程起始於形成矽中介板120’之後。在操作步驟510中，將一個或多個晶片(例如晶片110A及/或110B)接合至具有矽中介板(例如矽中介板120’)的基板。在晶片110A及/或110B接合至具有矽中介板120’的基板之後，施加底膠143以填入晶片110A及/或110B與矽中介板120’之間的空隙。在形成底膠143之後，形成模封化合物144以覆蓋矽中介板120’所露出的表面，且將模封化合物144填入晶片110A及/或110B之間的空隙。接著，在操作步驟520中，實施切割製程以將具有晶片接合於其上的矽中介板分割成個別的晶片封裝體。每一晶片封裝體包括晶片110A及/或110B與矽中介板120’。接著，在操作步驟530中，將晶片封裝體接合至基板130’。在晶片封裝體接合至基板130’之後，將底膠146填入晶片封裝體與基板130’之間的空隙，以形成三維積體電路晶片封裝體100’。
在此所提供為三維積體電路(3DIC)的不同製造方 法實施例。三維積體電路結構包括接合至晶片與基板的矽中介板。矽中介板具有包含連接至圖案化的金屬墊的矽穿孔(TSVs)的導電結構，以及位在圖案化的金屬墊的相對端面上的導電結構。於圖案化的金屬墊內嵌入介電結構以減少碟化效應，且圖案化的金屬墊具有不存在介電結構的區域，其位於矽穿孔之上。導電結構具有兩個或多個矽穿孔。藉由使用圖案化的金屬墊與兩個或多個矽穿孔，可改善導電結構與三維積體電路結構的可靠度與良率。
在一些實施例中，提供一種矽中介板結構。矽中介板結構包括兩個或多個矽穿孔(TSVs)以及圖案化的金屬墊。兩個或多個矽穿孔物理連接至圖案化的金屬墊，且圖案化的金屬墊具有複數個嵌入式介電結構。嵌入式介電結構不在兩個或多個矽穿孔之上。矽中介板亦包括一導電結構，其物理連接至兩個或多個矽穿孔，且其位在圖案化的金屬墊的相對端面上。
在一些其他的實施例中，提供一種封裝體結構。封裝體結構包括一半導體晶片以及連接至半導體晶片的一矽中介板結構。矽中介板結構包括兩個或多個矽穿孔(TSVs)以及一圖案化的金屬墊。兩個或多個矽穿孔物理連接至圖案化的金屬墊，且圖案化的金屬墊具有複數個嵌入式介電結構。嵌入式介電結構不在兩個或多個矽穿孔之上。封裝體結構亦包括一導電結構，其物理連接至兩個或多個矽穿孔，且其位在圖案化的金屬墊的相對端面上。此外，封裝體結構包括連接至矽中介板的一基板。
在另一些其他的實施例中，提供一種矽中介板結構的製造方法。矽中介板結構的製造方法包括於一基板內形成兩個或多個矽穿孔(TSVs)，以及形成一圖案化的金屬墊。兩個或多個矽穿孔物理連接至圖案化的金屬墊，且圖案化的金屬墊具有複數個嵌入式介電結構。嵌入式介電結構不在兩個或多個矽穿孔之上。矽中介板結構的製造方法亦包括研磨基板的一背側，以露出兩個或多個矽穿孔，且於基板的背側上形成一導電結構。導電結構物理連接至兩個或多個矽穿孔。
儘管以上已詳細敘述本發明實施例及其優點，可理解的是在不脫離實施例的精神與範圍內當可做出不同更動、替代與潤飾，如後附請求項所定義。再者，本發明的範圍不意圖以說明書所述之製程、機器、製造、物質組成、裝置、方法及步驟的特定實施例加以限制。所屬技術領域中具有通常知識者可從本發明揭示內容中輕易理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一請求項構成個別的實施例，且本發明之保護範圍也包括各個請求項及實施例的組合。
127’‧‧‧金屬墊
212、213‧‧‧嵌入式介電結構
214‧‧‧位置
215、217‧‧‧區域
L212‧‧‧介電結構212的長度
L217‧‧‧區域217的長度
WD‧‧‧介電結構213的寬度
W212‧‧‧介電結構212的寬度
W217‧‧‧區域217的寬度
WM‧‧‧金屬墊的寬度

Claims (10)

  1. 一種矽中介板結構，包括：兩個或多個矽穿孔(TSVs)；一圖案化的金屬墊，其中該兩個或多個矽穿孔物理連接至該圖案化的金屬墊，其中該圖案化的金屬墊具有複數個嵌入式介電結構，其中該些嵌入式介電結構不在該兩個或多個矽穿孔之上；以及一導電結構，其物理連接至該兩個或多個矽穿孔，且其位在該圖案化的金屬墊的相對端面上。
  2. 如申請專利範圍第1項所述之矽中介板結構，其中該圖案化的金屬墊的該些嵌入式介電結構包括位在該圖案化的金屬墊中央的一第一介電結構，其中該第一介電結構的一寬度與該圖案化的金屬墊的一寬度的比值介於1/4至1/2之間。
  3. 如申請專利範圍第1項所述之矽中介板結構，其中該圖案化的金屬墊包括不存在該些嵌入式介電結構的複數個區域，其中不存在該些嵌入式介電結構的該些區域位於各自的矽穿孔之上，其中不存在該些嵌入式介電結構的該些區域位在該圖案化的金屬墊的各個角落。
  4. 如申請專利範圍第3項所述之矽中介板結構，其中該些嵌入式介電結構包括多於一個的介電結構，介於相鄰的不存在該些嵌入式介電結構的該些區域之間。
  5. 一種封裝體結構，包括：一半導體晶片；以及一矽中介板結構，其連接至該半導體晶片，包括： 兩個或多個矽穿孔(TSVs)；一圖案化的金屬墊，其中該兩個或多個矽穿孔物理連接至該圖案化的金屬墊，其中該圖案化的金屬墊具有複數個嵌入式介電結構，其中該些嵌入式介電結構不在該兩個或多個矽穿孔之上；一導電結構，其物理連接至該兩個或多個矽穿孔，且其位在該圖案化的金屬墊的相對端面上；以及一基板，其連接至該矽中介板。
  6. 如申請專利範圍第5項所述之封裝體結構，其中該圖案化的金屬墊包括不存在該些嵌入式介電結構的複數個區域，其中不存在該些嵌入式介電結構的該些區域位於各自的矽穿孔之上且位在該圖案化的金屬墊的各個角落。
  7. 如申請專利範圍第6項所述之封裝體結構，其中該圖案化的金屬墊的該些嵌入式介電結構包括一第一介電結構，位於該圖案化的金屬墊中央，以及多於一個的介電結構，介於相鄰的不存在該些嵌入式介電結構的該些區域之間。
  8. 一種矽中介板結構的製造方法，包括：於一基板內形成兩個或多個矽穿孔(TSVs)；形成一圖案化的金屬墊，其中該兩個或多個矽穿孔物理連接至該圖案化的金屬墊，其中該圖案化的金屬墊具有複數個嵌入式介電結構，其中該些嵌入式介電結構不在該兩個或多個矽穿孔之上；研磨該基板的一背側，以露出該兩個或多個矽穿孔；以及於該基板的該背側上形成一導電結構，其中該導電結構物 理連接至該兩個或多個矽穿孔。
  9. 如申請專利範圍第8項所述之矽中介板結構的製造方法，其中形成該圖案化的金屬墊更包括：於該兩個或多個矽穿孔上形成一介電層；圖案化該介電層，以於該介電層內形成複數個開口；順沿著該些開口形成一阻障-晶種層；沉積一導電層以填入該些開口內；以及去除在該些開口外側的該導電層與該阻障-晶種層，其中在該去除步驟之後形成該圖案化的金屬墊。
  10. 如申請專利範圍第8項所述之矽中介板結構的製造方法，其中該圖案化的金屬墊包括不存在該些嵌入式介電結構的複數個區域，其中不存在該些嵌入式介電結構的該些區域位於各自的矽穿孔之上且位在該圖案化的金屬墊的各個角落。
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