CN203312275U - 形成嵌入式sop扇出型封装的半导体器件 - Google Patents

形成嵌入式sop扇出型封装的半导体器件 Download PDF

Info

Publication number
CN203312275U
CN203312275U CN2013202314131U CN201320231413U CN203312275U CN 203312275 U CN203312275 U CN 203312275U CN 2013202314131 U CN2013202314131 U CN 2013202314131U CN 201320231413 U CN201320231413 U CN 201320231413U CN 203312275 U CN203312275 U CN 203312275U
Authority
CN
China
Prior art keywords
encapsulation
semiconductor element
sealant
projection
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN2013202314131U
Other languages
English (en)
Inventor
林耀剑
陈康
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changdian Integrated Circuit Shaoxing Co ltd
Stats Chippac Shanghai Co Ltd
Stats Chippac Pte Ltd
Original Assignee
Stats Chippac Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Pte Ltd filed Critical Stats Chippac Pte Ltd
Application granted granted Critical
Publication of CN203312275U publication Critical patent/CN203312275U/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06133—Square or rectangular array with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/2101—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/215—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401—Structure
    • H01L2224/24011—Deposited, e.g. MCM-D type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401—Structure
    • H01L2224/2402—Laminated, e.g. MCM-L type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/245—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2733—Manufacturing methods by local deposition of the material of the layer connector in solid form
    • H01L2224/27334—Manufacturing methods by local deposition of the material of the layer connector in solid form using preformed layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48801—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/48811—Tin (Sn) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48817—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48824—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48839—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48844—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48847—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48855—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H01L2224/82104—Forming a build-up interconnect by additive methods, e.g. direct writing using screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82106—Forming a build-up interconnect by subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/83132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85401—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/85411—Tin (Sn) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/85424—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85447—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85455—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Abstract

本实用新型涉及形成嵌入式SoP扇出型封装的半导体器件。一种半导体器件，包括球栅阵列（BGA）封装，球栅阵列（BGA）封装包括第一凸块。在第一凸块之间将第一半导体管芯安装至BGA封装。将BGA封装和第一半导体管芯安装至载体。将第一密封剂沉积在载体之上以及BGA封装和第一半导体管芯周围。移除载体，以暴露第一凸块和第一半导体管芯。将互连结构电连接至第一凸块和第一半导体管芯。BGA封装还包括衬底和第二半导体管芯，第二半导体管芯被安装且电连接至衬底。将第二密封剂沉积在第二半导体管芯和衬底之上。在衬底之上与第二半导体管芯相对地形成第一凸块。在BGA封装之上形成翘曲平衡层。

Description

形成嵌入式SOP扇出型封装的半导体器件
技术领域
本实用新型总体涉及半导体器件，并且更具体地，涉及一种形成薄嵌入式封装上硅（Si）（silicon on package, SoP）扇出型封装的半导体器件和方法。
背景技术
半导体器件常见于现代电子产品中。半导体器件在电气组件的数目和密度上不同。分立的半导体器件一般包含一种类型的电气组件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器和功率金属氧化物半导体场效应晶体管（MOSFET）。典型地，集成的半导体器件包含数百个至数百万个电气组件。集成的半导体器件的示例包括微控制器、微处理器、电荷耦合器件（CCD）、太阳能电池和数字微镜器件（DMD）。
半导体器件执行多种多样的功能，例如信号处理、高速计算、发送和接收电磁信号、控制电子器件、将太阳光变换为电以及创建电视显示的视觉投影。半导体器件见于娱乐、通信、功率转换、网络、计算机和消费品的领域中。半导体器件也见于军事应用、航空、汽车、工业控制器和办公设备中。
半导体器件利用了半导体材料的电气属性。半导体材料的原子结构允许通过施加电场或基电流或者通过掺杂工艺来操纵其电导率。掺杂将杂质引入到半导体材料中，以操纵和控制半导体器件的电导率。
半导体器件包含有源和无源电气结构。包括双极和场效应晶体管的有源结构控制电流的流动。通过改变掺杂水平并施加电场或基电流，晶体管促进或限制电流的流动。包括电阻器、电容器和电感器的无源结构创建执行多种电气功能所必需的电压和电流之间的关系。无源和有源结构电连接以形成电路，这些电路使半导体器件能够执行高速计算和其他有用功能。
半导体器件一般是使用两种复杂制造工艺（即，前端制造和后端制造）来制造的，每一种制造工艺潜在地涉及数百个步骤。前端制造涉及在半导体晶片的表面上形成多个管芯。典型地，每个半导体管芯是相同的，并包含通过将有源和无源组件电连接而形成的电路。后端制造涉及从抛光的晶片单体化（singulating）个体半导体管芯并对管芯进行封装，以提供结构支撑和环境隔离。如本文所使用的术语“半导体管芯”指代单数和复数形式的词语，并且相应地，可以指代单个半导体器件和多个半导体器件。
半导体制造的一个目标是生产更小的半导体器件。典型地，更小的器件消耗更低功率，具有更高性能，并可以被更高效地生产。此外，更小的半导体器件具有更小的占位空间（footprint），这对更小最终产品来说是期望的。可以通过前端工艺中的改进来实现更小的半导体管芯大小，从而得到具有更小、更高密度的有源和无源组件的半导体管芯。后端工艺可以通过电气互连和封装材料中的改进来得到具有更小占位空间的半导体器件封装。
更小半导体器件的制造依赖于实现对多个级别上的多个半导体器件之间的水平和垂直电气互连（3-D器件集成）的改进。水平电气互连包括作为扇出型晶片级芯片尺寸封装（fo-WLCSP）或嵌入式晶片级球栅阵列（eWLB）的一部分而形成的重分布层（RDL），其提供了半导体管芯与封装外部的点之间的电连接。垂直互连可以是利用导电过硅通孔（through silicon via, TSV）或过孔通孔（through hole via, THV）来实现的。然而，典型地，对TSV和THV的使用涉及相当多的时间和器件，这减少了每小时单位（UPH）生产并提高了成本。此外，通孔形成可以包括对降低器件可靠性的空洞的形成，并可能提出半导体管芯安置精度和翘曲控制的问题。在图1a和1b中示出了一种用于解决3-D器件集成的水平和垂直互连的问题的方案，如本领域公知。
图1a示出了eWLB模塑激光封装（MLP）封装10，其使用包括RDL的互连结构12来提供用于半导体管芯14的扇出型水平电连接。eWLB-MLP封装10还包括通过激光钻孔在密封剂20中形成的开口18。垂直互连或导电凸块22布置在开口18内，以在不使用TSV或THV的情况下提供互连结构12与eWLB-MLP封装10的同该互连结构相对的表面之间的垂直互连。相应地，eWLB-MLP封装10提供与在半导体管芯14的占位空间外形成的垂直互连22的互连I/O阵列的水平和垂直电气互连，以便后续安装附加半导体器件或封装，以形成3-D eWLB-MLP封装。
图1b示出了球栅阵列（BGA）封装或凸起半导体器件24布置在来自图1a的eWLB-MLP封装10之上，其中，凸块26布置在凸块22之上且定向凸块22。在图1c中，利用表面安装技术（SMT）将BGA封装24安装至eWLB-MLP封装10，以形成3-D eWLB-MLP封装28。在将BGA封装24安装至eWLB-MLP封装10之后，对3-D eWLB-MLP封装28进行加热，以回焊来自BGA封装24的凸块26和垂直互连22，从而形成凸块或互连结构30。因此，形成3-D eWLB-MLP封装28，并且3-D eWLB-MLP封装28提供水平和垂直互连，作为3-D集成半导体器件。然而，3-D eWLB-MLP封装28的形成需要导致高工艺成本的复杂工艺流程。3-D eWLB-MLP封装28的工艺流程由于利用激光钻孔形成开口18和使用两个凸块工艺而变得复杂。第一凸块工艺用于形成凸块26作为BGA封装24的一部分，并且第二凸块工艺用于如图1a所示在开口18中形成凸块22，随后将凸块26和凸块22结合以形成凸块30。3-D eWLB-MLP封装28的形成还提供了针对在背面激光钻孔期间处理封装以及形成开口18和凸块30的挑战。使用SMT将BGA 24安装至eWLB-MLP封装10引入了降低器件可靠性和封装产量的附加挑战，例如处理问题和潜在晶片损坏。最后，3-D eWLB-MLP封装28提供了在控制封装的总体高度时的有限灵活性。
实用新型内容
存在对提供封装的高效水平和垂直互连的3-D半导体封装的需要。相应地，在一个实施例中，本实用新型是一种包括BGA封装的半导体器件，所述BGA封装包括多个第一凸块。第一半导体管芯布置在所述BGA封装之上所述第一凸块之间。第一密封剂沉积在所述BGA封装和第一半导体管芯之上。在所述第一凸块和第一半导体管芯之上形成扇出型互连结构，并将所述扇出型互连结构电连接至所述第一凸块和第一半导体管芯。
在另一实施例中，本实用新型是一种包括半导体封装的半导体器件，所述半导体封装包括多个第一互连结构。第一半导体管芯布置在所述半导体封装之上所述第一互连结构之间。第一密封剂沉积在所述半导体封装和第一半导体管芯之上。在所述第一互连结构和第一半导体管芯之上形成第二互连结构，并将所述第二互连结构电连接至所述第一互连结构和第一半导体管芯。
在另一实施例中，本实用新型是一种包括半导体封装的半导体器件，所述半导体封装包括多个第一互连结构。第一半导体管芯布置在所述半导体封装之上所述第一互连结构之间。在所述第一互连结构和第一半导体管芯之上形成第二互连结构，并将所述第二互连结构电连接至所述第一互连结构和第一半导体管芯。
附图说明
图1a-1c示意了eWLB-MLP半导体封装；
图2示意了具有安装至其表面的不同类型封装的印刷电路板（PCB）；
图3a-3c示意了安装至PCB的代表性半导体封装的进一步细节；
图4a-4c示意了具有由划片街区（saw street）分离的多个半导体管芯的半导体晶片；
图5a-5q示意了形成嵌入式SOP扇出型封装的工艺；
图6a-6b示意了具有翘曲平衡层的嵌入式SOP扇出型封装；
图7示意了具有翘曲平衡层的嵌入式SOP扇出型封装的另一实施例；
图8示意了嵌入式SOP扇出型封装的另一实施例；
图9示意了具有管芯附着粘合剂的嵌入式SOP扇出型封装；
图10示意了包括BGA封装的嵌入式SOP扇出型封装的实施例；
图11a-11b示意了包括多个密封剂的嵌入式SOP扇出型封装的实施例；
图12a-12c示意了包括布置在BGA封装之上的导电层的嵌入式SOP扇出型封装的实施例；
图13a-13d示意了包括布置在BGA封装之上的导电层的嵌入式SOP扇出型封装的另一实施例；
图14示意了包括铜凸块的嵌入式SOP扇出型封装的实施例；
图15示意了包括附着在封装之上的金属膜的嵌入式SOP扇出型封装的实施例；
图16示意了包括在封装中形成的开口以提供应力消除的嵌入式SOP扇出型封装的实施例；
图17示意了包括微凸块的嵌入式SOP扇出型封装的另一实施例；
图18示意了包括螺柱凸块（stud bump）的嵌入式SOP扇出型封装的另一实施例；
图19a-19i示意了形成嵌入式SOP扇出型封装的另一工艺；以及
图20示意了包括腔的嵌入式SOP扇出型封装的另一实施例。
具体实施方式
参照附图，在以下描述中的一个或多个实施例中描述本实用新型，在附图中，相似的数字表示相同或相似的元件。尽管在用于实现本实用新型的目的的最佳模式的方面描述了本实用新型，但是本领域技术人员将意识到，本实用新型意在覆盖可包括在由所附权利要求及其等同物限定、由以下公开和附图支持的本实用新型的精神和范围内的替换、修改和等同物。
半导体器件一般是使用以下两种复杂制造工艺来制造的：前端制造和后端制造。前端制造涉及在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包含有源和无源电气组件，有源和无源电气组件电连接以形成功能电路。有源电气组件（例如，晶体管和二极管）具有控制电流的流动的能力。无源电气组件（例如，电容器、电感器、电阻器和变压器）创建执行电路功能所必需的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、蚀刻和平坦化在内的一系列工艺步骤，在半导体晶片的表面之上形成无源和有源组件。掺杂通过诸如离子注入或热扩散之类的技术，将杂质引入到半导体材料中。掺杂工艺修改了有源器件中的半导体材料的电导率，从而将半导体材料变换为绝缘体、导体或者响应于电场或基电流而动态地改变半导体材料电导率。晶体管包含不同类型和掺杂程度的区，这些不同类型和掺杂程度在必要时被布置为使晶体管能够在施加电场或基电流时促进或限制电流的流动。
有源和无源组件由具有不同电气属性的材料的层形成。这些层可以通过部分地由所沉积的材料的类型确定的多种沉积技术而形成。例如，薄膜沉积可以涉及化学气相沉积（CVD）、物理气相沉积（PVD）、电解电镀和无电电镀工艺。一般地，对每个层进行图案化，以形成有源组件、无源组件或组件之间的电连接的部分。
可以使用光刻来对这些层进行图案化，光刻涉及将光敏材料（例如，光致抗蚀剂）沉积在要图案化的层之上。使用光将图案从光掩模传送至光致抗蚀剂。在一个实施例中，使用溶剂来移除光致抗蚀剂图案的经受光的部分，从而暴露要图案化的下层的部分。在另一实施例中，使用溶剂来移除光致抗蚀剂图案的未经受光的部分（负性光致抗蚀剂），从而暴露要图案化的下层的部分。移除光致抗蚀剂的其余部分，从而留下图案化层。可替换地，通过直接将材料沉积到由使用诸如无电和电解电镀之类的技术的先前沉积/蚀刻工艺形成的区域或空洞中，对一些类型的材料进行图案化。
图案化是通过其移除半导体晶片表面上的顶层的部分的基本操作。可以使用光刻、光掩模、掩模、氧化物或金属移除、照相术和丝网印刷（stenciling）、以及显微光刻来移除半导体晶片的部分。光刻包括：在光罩（reticle）或光掩模中形成图案并将该图案传送至半导体晶片的表面层中。光刻在两步骤工艺中在半导体晶片的表面上形成有源和无源组件的水平尺寸。首先，将光罩或掩模上的图案传送至光致抗蚀剂的层中。光致抗蚀剂是在暴露于光时经历结构和属性的改变的光敏材料。改变光致抗蚀剂的结构和属性的工艺作为负性作用光致抗蚀剂或正性作用光致抗蚀剂而出现。其次，将光致抗蚀剂层传送至晶片表面中。当蚀刻移除了半导体晶片的顶层的未被光致抗蚀剂覆盖的部分时，进行该传送。光致抗蚀剂的化学性质使得光致抗蚀剂保持实质上完整无缺并抵抗由化学蚀刻溶液进行的移除，同时移除了半导体晶片的顶层的未被光致抗蚀剂覆盖的部分。可以根据所使用的特定抗蚀剂和期望结果来修改形成、暴露和移除光致抗蚀剂的工艺以及移除半导体晶片的部分的工艺。
在负性作用光致抗蚀剂中，在被称为聚合的工艺中，将光致抗蚀剂暴露于光并将其从可溶状况改变至不可溶状况。在聚合中，未聚合材料暴露于光或能源，并且聚合物形成抗蚀的交联材料。在大多数负性抗蚀剂中，聚合物是聚异戊二烯。利用化学溶剂或显影剂移除可溶部分（即，未暴露于光的部分）在抗蚀剂层中留下与光罩上的不透明图案相对应的孔。其图案存在于不透明区中的掩模被称为亮场掩模。
在正性作用光致抗蚀剂中，在被称为光溶解的工艺中，将光致抗蚀剂暴露于光并将其从相对不可溶的状况改变至可溶得多的状况。在光溶解中，将相对不可溶的抗蚀剂暴露于适当的光能，并将其转换至更可溶的状态。可以在显影工艺中通过溶剂来移除抗蚀剂的光溶解后的部分。基本正性光致抗蚀剂聚合物是酚醛树脂聚合物，也被称为酚醛清漆树脂。利用化学溶剂或显影剂移除可溶部分（即，暴露于光的部分）在抗蚀剂层中留下与光罩上的透明图案相对应的孔。其图案存在于透明区中的掩模被称为暗场掩模。
在移除了半导体晶片的未被光致抗蚀剂覆盖的顶部分之后，移除光致抗蚀剂的其余部分，从而留下图案化层。可替换地，通过直接将材料沉积到由使用诸如无电和电解电镀之类的技术的先前沉积/蚀刻工艺形成的区域或空洞中，对一些类型的材料进行图案化。
将材料的薄膜沉积在现有图案之上可以扩大下层图案并创建非均匀地平坦的表面。需要均匀地平坦的表面来生产更小且更密集包装的有源和无源组件。平坦化可以用于从晶片的表面移除材料并生产均匀地平坦的表面。平坦化涉及利用抛光垫来对晶片的表面进行抛光。在抛光期间将研磨材料和腐蚀性化学品添加至晶片的表面。研磨料的机械动作和化学品的腐蚀性动作的组合移除了任何不规则构形，从而得到非均匀地平坦的表面。
后端制造指代：将抛光的晶片切割或单体化为个体半导体管芯，并且然后，对半导体管芯进行封装以用于结构支撑和环境隔离。为了单体化半导体管芯，沿被称为划片街区或划线（scribe）的晶片的非功能区对晶片进行刻痕并打碎晶片。使用激光切割工具或锯片来单体化晶片。在单体化后，将个体半导体管芯安装至封装衬底，该封装衬底包括用于与其他系统组件互连的管脚或接触焊盘。然后，将在半导体管芯之上形成的接触焊盘连接至封装内的接触焊盘。可以利用焊料凸块、螺柱凸块、导电浆料或线接合来制成电连接。将密封剂或其他模塑材料沉积在封装之上，以提供物理支撑和电隔离。然后，将抛光的封装插入到电气系统中，并使半导体器件的功能对其他系统组件来说可用。
图2示意了具有芯片载体衬底或PCB 52的电子器件50，芯片载体衬底或PCB 52具有安装至其表面的多个半导体封装。根据应用，电子器件50可以具有一种类型的半导体封装或多种类型的半导体封装。出于示意的目的，在图2中示出了不同类型的半导体封装。
电子器件50可以是使用半导体封装执行一个或多个电气功能的独立系统。可替换地，电子器件50可以是大型系统的子组件。例如，电子器件50可以是蜂窝电话、个人数字助理（PDA）、数字视频摄像机（DVC）或其他电子通信设备的一部分。可替换地，电子器件50可以是图形卡、网络接口卡、或者可插入到计算机中的其他信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、RF电路、分立器件、或者其他半导体管芯或电气组件。为了使这些产品被市场接受，小型化和重量减小是必要的。必须减小半导体器件之间的距离以实现更高密度。
在图2中，PCB 52提供了用于结构支撑的一般衬底和在PCB上安装的半导体封装的电气互连。使用蒸发、电解电镀、无电电镀、丝网印刷或其他合适金属沉积工艺，在PCB 52的表面之上或在PCB 52的层内形成导电信号迹线54。信号迹线54提供了半导体封装、所安装的组件和其他外部系统组件中的每一个之间的电气通信。迹线54还给半导体封装中的每一个提供功率和接地连接。
在一些实施例中，半导体器件具有两个封装级。第一级封装是用于将半导体管芯机械和电气附着至中间载体的技术。第二级封装涉及将中间载体机械和电气附着至PCB。在其他实施例中，半导体器件可以仅具有第一级封装，其中，直接将管芯机械和电气安装至PCB。
出于示意的目的，在PCB 52上示出了多种类型的第一级封装，包括接合线封装56和倒装芯片（flipchip）58。此外，在PCB 52上示出安装多种类型的第二级封装，包括BGA 60、凸块芯片载体（BCC）62、双列直插式封装（DIP）64、接点栅格阵列（land grid array, LGA）66、多芯片模块（MCM）68、四边扁平无引脚封装（QFN）70和四边扁平封装72。根据系统需求，利用第一和第二级封装样式的任意组合配置的半导体封装以及其他电子组件的任意组合可以连接至PCB 52。在一些实施例中，电子器件50包括单个附着半导体封装，而其他实施例要求多个互连封装。通过在单个衬底之上组合一个或多个半导体封装，制造商可以将预先制成的组件并入到电子器件和系统中。由于半导体封装包括完善的功能，因此可以使用更便宜的组件和精简的制造工艺来制造电子器件。所得到的器件更不可能发生故障并在制造上更便宜，从而使得对于消费者来说成本更低。
图3a-3c示出了示例性半导体封装。图3a示意了在PCB 52上安装的DIP 64的进一步细节。半导体管芯74包括有源区，有源区包含被实现为在管芯内形成的有源器件、无源器件、导电层和介电层的模拟或数字电路，并根据管芯的电气设计而电气互连。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器以及在半导体管芯74的有源区内形成的其他电路元件。接触焊盘76是一层或多层的导电材料（例如，铝（Al）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）或银（Ag）），并电连接至在半导体管芯74内形成的电路元件。在DIP 64的组装期间，使用金-硅共晶层或粘合材料（例如，热环氧化物或环氧树脂）将半导体管芯74安装至中间载体78。封装体包括绝缘封装材料，例如聚合物或陶瓷。导电引线80和接合线82提供了半导体管芯74与PCB 52之间的电气互连。通过防止水汽和颗粒进入该封装并污染半导体管芯74或接合线82，将密封剂84沉积在该封装之上以用于环境保护。
图3b示意了在PCB 52上安装的BCC 62的进一步细节。使用底部填充或环氧树脂粘合材料92将半导体管芯88安装在载体90之上。接合线94提供了接触焊盘96和98之间的第一级封装互连。将模塑料或密封剂100沉积在半导体管芯88和接合线94之上，以提供针对该器件的物理支撑和电隔离。使用合适的金属沉积工艺（例如，电解电镀或无电电镀）在PCB 52的表面之上形成接触焊盘102，以防止氧化。将接触焊盘102电连接至PCB 52中的一个或多个导电信号迹线54。在BCC 62的接触焊盘98与PCB 52的接触焊盘102之间形成凸块104。
在图3c中，利用倒装芯片样式第一级封装将半导体管芯58面朝下安装至中间载体106。半导体管芯58的有源区108包含被实现为根据管芯的电气设计而形成的有源器件、无源器件、导电层和介电层的模拟或数字电路。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及有源区108内的其他电路元件。通过凸块110将半导体管芯58电气和机械连接至载体106。
利用BGA样式第二级封装、使用凸块112将BGA 60电气和机械连接至PCB 52。通过凸块110、信号线114和凸块112将半导体管芯58电连接至PCB 52中的导电信号迹线54。将模塑料或密封剂116沉积在半导体管芯58和载体106之上，以提供针对该器件的物理支撑和电隔离。倒装芯片半导体器件提供了从半导体管芯58上的有源器件至PCB 52上的导电迹线的短导电路径，以便减小信号传播距离、降低电容并改进总体电路性能。在另一实施例中，可以在没有中间载体106的情况下使用倒装芯片样式第一级封装直接将半导体管芯58机械和电气连接至PCB 52。
图4a示出了具有用于结构支撑的基衬底材料122（例如，硅、锗、砷化镓、磷化铟或碳化硅）的半导体晶片120。在由如上所述的非有源的管芯间晶片区域或划片街区126分离的晶片120上形成多个半导体管芯或组件124。划片街区126提供了切割区域，以将半导体晶片120单体化为半导体管芯的条或个体半导体管芯124。
图4b示出了半导体晶片120的部分的横截面视图。每个半导体管芯124具有背表面128和有源表面130，有源表面130包含被实现为在管芯内形成且根据管芯的电气设计和功能而电气互连的有源器件、无源器件、导电层和介电层的模拟或数字电路。例如，该电路可以包括一个或多个晶体管、二极管、以及在有源表面130内形成的其他电路元件，以实现模拟电路或数字电路，例如数字信号处理器（DSP）、ASIC、存储器或其他信号处理电路。半导体管芯124还可以包含用于RF信号处理的集成无源器件（IPD），例如电感器、电容器和电阻器。在一个实施例中，半导体管芯124是倒装芯片类型器件。
使用PVD、CVD、电解电镀、无电电镀工艺或其他合适金属沉积工艺，在有源表面130之上形成导电层132。导电层132可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其他合适导电材料。导电层132作为与有源表面130上的电路电连接的接触焊盘进行操作。可以将导电层132形成为与半导体管芯124的边缘相距第一距离并排布置的接触焊盘，如图4b所示。可替换地，可以将导电层132形成为在多个行中偏置的接触焊盘，使得与管芯的边缘相距第一距离布置接触焊盘的第一行，并与管芯的边缘相距第二距离布置与第一行交替的接触焊盘的第二行。
在图4c中，使用锯片或激光切割工具136、通过划片街区126将半导体晶片120单体化为半导体管芯的条或个体半导体管芯124。
图5a-5q与图2和3a-3c相关地示意了高效地形成包括水平和垂直互连的3-D SOP扇出型封装的工艺。图5a示出了衬底或PCB 144的包括第一表面146和与第一表面相对的第二表面148的部分的横截面视图。衬底144包括结构或基材料150，结构或基材料150包括一个或多个层压绝缘或介电层，例如硅、锗、砷化镓、磷化铟、碳化硅、聚合物、聚合物复合材料、陶瓷、玻璃、玻璃环氧化物、氧化铍、或者用于结构支撑的其他合适低成本刚性材料或散装半导体材料。衬底144还可以是多层柔性层压、陶瓷或引线框。
导电层或RDL 154被形成为衬底144的一部分，并包括一层或多层的Al、Cu、Sn、Ni、Au、Ag或其他合适导电材料。导电层154包括在衬底144内且通过衬底144形成的部分154a，以在整个衬底中提供电气互连，该电气互连包括相对的第一和第二表面146和148相应之间的垂直电气互连。导电层154还包括在第一表面146上或处形成的部分154b，部分154b作为导电层154与后续安装的半导体器件之间的电气互连的接触焊盘或迹线进行操作。类似地，导电层154还包括在第二表面148上或处形成的部分154c，部分154c作为接触焊盘或迹线进行操作用于导电层154与后续安装的半导体器件之间的电气互连。衬底144根据后续安装的半导体管芯的配置和设计、通过导电层154在衬底上垂直和横向地提供电气互连。根据后续安装的半导体器件的设计和功能，导电层154的部分是电气公共的或电隔离的。
在图5b中，以背表面128定向衬底144的第一表面146的方式将来自图4c的半导体管芯124安装至衬底144。使用管芯附着粘合剂或其他合适材料，将背表面128附着至衬底的第一表面146。在多个接触焊盘154b横向偏置和布置在半导体管芯的外周周围以供后续电气互连的情况下，将半导体管芯124安装至衬底144。
在图5c中，在半导体管芯124的导电层132与接触焊盘或迹线154b之间形成多个接合线158。使用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压或其他合适涂敷器，将密封剂160沉积在半导体管芯124之上和周围、在衬底144之上、以及在接合线158周围。密封剂160可以是聚合物复合材料，例如，具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯或具有适当填充物的聚合物。在一个实施例中，密封剂160内包括的填充物包括液相、粉末相或晶粒相下的大小小于或等于约100微米（μm）的颗粒。密封剂160是不导电的，提供物理支撑，并在环境上保护半导体器件免于外部元件和污染物。在一个实施例中，使用膜辅助模塑工艺来沉积密封剂160。
在图5d中，使用蒸发、电解电镀、无电电镀、球落（ball drop）或丝网印刷工艺，将导电凸块材料沉积在接触焊盘154c之上。在可选的熔剂溶液的情况下，凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸块材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。使用合适的附着或接合工艺将凸块材料接合至导电层154c。在一个实施例中，通过将材料加热至高于其熔点来回焊凸块材料，以形成球或凸块164。在一些应用中，第二次回焊凸块164，以改进与接触焊盘154c的电接触。还可以将凸块164压缩接合或热压缩接合至接触焊盘154c。凸块164表示可在接触焊盘154c之上形成的一种类型的互连结构。互连结构还可以使用螺柱凸块、微凸块、导电柱、复合互连或其他电气互连。凸块164的高度由期望最终封装高度以及其他因素确定。半导体管芯124、衬底144、密封剂160和凸块164一起形成BGA封装或半导体封装166。
图5e示出了包括背表面172和与该背表面相对的有源表面174的与来自图4c的半导体管芯124类似的半导体管芯170。有源表面174包括使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化而共形地涂敷在有源表面之上的绝缘或钝化层180和接触焊盘176。绝缘层180包含一层或多层的二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、五氧化二钽（Ta2O5）、氧化铝（Al2O3）或具有类似绝缘和结构属性的其他材料。通过使用激光器181的激光直接消融（LDA）、蚀刻或其他工艺来移除绝缘层180的部分，以在绝缘层180中形成开口182，从而暴露接触焊盘176。以背表面172定向衬底144的第二表面148且有源表面174定向远离衬底144的方式将半导体管芯170安装至衬底144。
在将半导体管芯170 安装至衬底144之前，可选地，半导体管芯经历具有抛光的背面研磨工艺，以从背表面172移除散装半导体材料，从而减小半导体管芯的厚度。在背面研磨和可选的抛光之后，在单体化半导体管芯之前将管芯附着带或粘合剂178布置在半导体管芯170的背表面172之上。可替换地，在单体化半导体管芯之后将管芯附着带或粘合剂178布置在半导体管芯170的背表面172之上。使用拾取和放置操作将半导体管芯170安装至衬底144，其中，由于在BGA封装166的衬底上存在基准对齐标记，便于衬底上的半导体管芯的适当对齐。将半导体管芯170单独安装至衬底144，或者可替换地，以条级别将半导体管芯170安装至衬底。在多个凸块164横向偏置和布置在所安装的半导体管芯170的外周周围的情况下将半导体管芯170安装至衬底144的第二表面148。在一个实施例中，半导体管芯170具有比半导体管芯124的面积或占位空间大的面积或占位空间，使得半导体管芯124布置在衬底144的第二表面148之上半导体管芯170的占位空间内。可替换地，半导体管芯170具有等于或小于半导体管芯124的面积或占位空间的面积或占位空间。
在将半导体管芯170安装至衬底144之后，对半导体管芯170和BGA封装166应用B阶段固化，以进一步固化管芯附着带或粘合剂178。此外，可以在已经将半导体管芯安装至衬底144之后对半导体管芯170应用优化的退火工艺，以控制翘曲并维持BGA封装166的可接受平坦度。
与图5e类似，图5f示出了以背表面172定向衬底144的第二表面148的方式将半导体管芯170安装至衬底144。不同于如图5e中示出管芯附着带或粘合剂178初始布置在半导体管芯170的背表面172之上，图5f示出了管芯附着粘合剂190初始布置在衬底144之上并接触衬底144，同时与半导体管芯170分离。由于裸半导体管芯170（即，没有管芯附着粘合剂）被安装至衬底144，因此粘合剂190与半导体管芯的背表面172以及半导体管芯的在背表面172与有源表面174之间延伸的侧表面相接触。
图5g示出了将半导体管芯170安装至BGA封装166以形成SoP封装196。使用锯片或激光切割工具198，通过衬底144、通过密封剂160以及在BGA封装166的凸块164、半导体管芯124和半导体管芯170之间单体化SoP封装196，以形成个体SoP封装196。
与图5e-5g类似，图5h示出了以背表面172定向衬底144的第二表面148的方式将半导体管芯170安装至衬底144。不同于如图5e和5f中示出将半导体管芯170安装至未单体化的衬底144，图5h示出了在已经将凸块164安装至衬底之后以及在已经如以上在图5g中所述单体化衬底之后与半导体管芯124相对地将半导体管芯170安装至衬底144。在如图5e所示管芯附着带或粘合剂178初始布置在半导体管芯170的背表面172之上的情况下，或者在如图5f所示管芯附着粘合剂190初始布置在衬底144之上并接触衬底144的情况下，将半导体管芯170安装至单体化后的BGA封装166。通过将半导体管芯170安装至单体化后的BGA封装166，可以在附着半导体管芯之前测试BGA封装，使得半导体管芯仅被安装至已知的良好BGA封装166，从而提高SoP封装196的产量。
图5i示出了包含牺牲或可回收基材料（例如，硅、钢、聚合物、氧化铍、或者用于结构支撑的其他合适低成本刚性材料）的临时衬底或载体200的部分的横截面视图。在载体200之上形成或层压了界面层或载体带202，作为临时粘合剂接合膜和支撑层。在载体带202上以及在载体200之上形成或层压热可释放层204。热可释放层204被配置为接纳后续安装的SoP封装196，并在密封剂沉积在SoP封装周围之后移除。可替换地，在载体200之上形成单层的载体带或粘合剂，而不是使用载体带202和热可释放层204的两层结构。
以半导体管芯170的有源表面174定向载体的方式将来自图5g或5h的SoP封装196定位于载体200、载体带202和热可释放层204之上。使用具有精确且准确对准的拾取和放置操作将SoP封装196安装至载体200、载体带202和热可释放层204，该对准提供了SoP封装之间的间隔或间隙206，以便于后续在SoP封装之上形成扇出型互连结构或衬底。凸块164的高度小于或等于半导体管芯170和管芯附着带178或管芯附着粘合剂190的组合高度。换句话说，半导体管芯170的高度近似等于凸块164和管芯附着带178或管芯附着粘合剂190的高度之差。可替换地，凸块164的高度稍稍大于半导体管芯170和管芯附着带178或管芯附着粘合剂190的组合高度。在一个实施例中，凸块164的高度比半导体管芯170和管芯附着带178或管芯附着粘合剂190的组合高度大10 μm，凸块164的高度随管芯附着带178或管芯附着粘合剂190的厚度而变化。相应地，凸块164的部分沉积在热可释放层204的部分的厚度内并被热可释放层204的部分包围。类似地，半导体管芯170的包括例如绝缘层180和接触焊盘176的部分也沉积在可释放层204或者单层载体带或粘合剂的厚度内并被其包围。
图5j示出了如图5i所述利用热可释放层204将SoP封装196安装至载体200的平面或俯视图。间隙206布置在SoP封装196的外周周围并布置在相邻SoP封装之间。图5j还示出了在四个相邻SoP封装196的角处形成的、两个间隙206之间的交点208。
图5k示出了在载体200、载体带202、热可释放层204之上以及在SoP封装196之上和周围预先分配或层压密封剂或模塑料210。可替换地，可以使用传递模塑或其他合适工艺来涂敷模塑料210。密封剂210可以是聚合物复合材料，例如，具有填充物或纤维的环氧树脂、具有填充物或纤维的环氧丙烯酸酯、或者具有适当填充物或纤维的聚合物。在一个实施例中，密封剂210中的填充物包括液相、粉末相或晶粒相下的大小小于或等于约100 μm的颗粒，并被选择为具有便于填充间隙206和填充BGA封装166与载体200之间的凸块164周围的区域的含量水平和特性。密封剂210中的填充物还被选择为控制翘曲并改进封装可靠性。在热可释放层204上分配密封剂210，并且在一个实施例中，在载体200上的中央位置处（例如，在四个相邻SoP封装196的角处间隙206的交点208处）分配密封剂210。因此，形成了包括嵌入式SoP封装196和密封剂210的重构晶片或扇出型衬底214。将SoP封装196一起嵌入到密封剂210中，密封剂210是不导电的，并在环境上保护SoP封装免于外部元件和污染物。
图5l示出了将冲切模具（chase mold）218与载体200、载体带202和热可释放层204集合在一起（bring together），以将重构晶片214围在用于密封的模具内。通过在SoP封装196和密封剂210周围移动冲切模具218，或者可替换地，通过将SoP封装和密封剂移动至模具中，将冲切模具218与载体200、载体带202和热可释放层204集合在一起。在一个实施例中，冲切模具218仅包括与载体200、载体带202和热可释放层204集合在一起的第一或顶部分，而不具有第二或底模具部分。载体200、载体带202和热可释放层204充当用于密封工艺的底模具部分。可替换地，可以将半导体管芯SoP封装196、载体200、载体带202和热可释放层204布置在包括多个部分（例如，顶和底部分）的模具内。在将SoP封装196和密封剂210布置在冲切模具218内之后，可以部分或完全对密封剂进行固化。在将SoP封装196嵌入到密封剂210内以形成重构晶片214之后，从冲切模具218移除重构晶片。
图5m示出了从冲切模具218移除重构晶片214。通过激活热可释放层204，从凸块164、半导体管芯170和密封剂210完全脱接合和移除载体200、载体带202和热可释放层204。可替换地，通过化学蚀刻、机械剥离、CMP、机械研磨、热焙烧、UV光、激光扫描或湿脱模来完成脱接合。对载体200、载体带202和热可释放层204的移除暴露了密封剂210的表面，并进一步暴露了凸块164、绝缘层180和接触焊盘176。
在一个实施例中，在SoP封装196的背表面222之上形成密封剂的期望厚度，并且不需要背面研磨。可替换地，密封剂210的表面224经历利用研磨机226的研磨操作，以对表面进行平坦化并减小密封剂的厚度，以辅助控制SoP封装196的翘曲。研磨操作移除了密封剂210，以暴露密封剂的表面228。在一个实施例中，表面228相对于SoP封装196的背表面222垂直偏移。可替换地，表面228相对于SoP封装196的背表面222共面。还可以使用化学蚀刻来对密封剂210进行移除和平坦化。尽管图5m示出了在形成将凸块164和接触焊盘176相连接的互连结构之前进行密封剂210的背面研磨，还可以在形成互连结构期间或之后进行密封剂的背面研磨，例如在图5o-5q处。密封剂210的背面研磨便于根据最终封装的设计来调整总体封装高度。
在移除了载体200、载体带202和热可释放层204之后，在凸块164上应用浅激光钻孔或清洗，以清洗凸块164的表面并改进凸块的接触电阻。还使用利用激光器229的LDA、RF蚀刻、等离子清洗或湿法清洗，清洗了凸块164并移除了氧化物累积（oxide buildup）。在一个实施例中，凸块164是Cu，并且，通过RF蚀刻来移除在铜凸块164上形成的自然出现的氧化物。
图5n示出了可选的翘曲平衡层234在密封剂210的表面224或228之上形成并接触密封剂210的表面224或228。使用印刷、旋涂、喷涂、丝网印刷、层压、浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压或其他合适的涂敷器来形成翘曲平衡层234。翘曲平衡层234可以是一层或多层的具有或不具有填充物的光敏聚合物介电膜、非光敏聚合物介电膜、环氧化物、环氧树脂、聚合材料、聚合物复合材料（例如，具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯或具有适当填充物的聚合物）、热固性塑料层压板、或者具有类似绝缘和结构属性的其他材料。在最终对密封剂210进行移除或背面研磨之后，形成并固化翘曲平衡层234。翘曲平衡层234提供针对SoP封装196的结构支撑，对封装上的应力进行平衡，并减少在后续处理和加工期间封装的翘曲或破裂。根据总体封装配置和设计来调整翘曲平衡层234的翘曲特性，包括翘曲平衡层的厚度以及材料属性。在一个实施例中，翘曲平衡层234具有10至60 μm的范围内的厚度和10至150 ppm/摄氏度的范围内的CTE。
图5o示出了在移除了载体200、载体带202和热可释放层204之后，通过绝缘或钝化层230的沉积和图案化以及导电层232的沉积和图案化，在重构晶片214之上形成扇出型多互连RDL的第一部分。绝缘层230被共形地涂敷至以下各项并具有遵循以下各项的轮廓的第一表面：密封剂210、绝缘层180、开口182、接触焊盘176和凸块164。绝缘层230具有与第一表面相对的第二平表面。绝缘层230包含一层或多层的光敏低固化温度介电抗蚀剂、光敏复合抗蚀剂、液晶聚合物（LCP）、层压复合膜、具有填充物的绝缘浆料、焊接掩模抗蚀膜、液体模塑料、颗粒模塑料、聚酰亚胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3、或者具有类似绝缘和结构属性的其他材料。使用印刷、旋涂、喷涂、层压或其他合适工艺来沉积绝缘层230。随后，使用UV曝光之后紧跟显影或其他合适工艺，对绝缘层230进行图案化和固化。通过LDA、蚀刻或其他合适工艺来移除绝缘层230的部分，以形成暴露半导体管芯170的接触焊盘176和凸块164的开口。还可以在移除绝缘层230的部分期间或之后清洗凸块164和接触焊盘176，如先前关于图5m中的凸块164所描述。
对导电层232进行图案化并将导电层232沉积在密封剂210、半导体管芯170和绝缘层230之上。导电层232可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或者不会导致凸块164与导电层232之间的脱层的其他合适导电材料或合金。在一个实施例中，例如当凸块164是焊料时，导电层232包括粘合层和阻挡层，阻挡层是焊料可湿材料，例如铬铜（CrCu）、Au、钛铜（TiCu）合金、Ni或镍钒（NiV）合金。导电层232的沉积使用PVD、CVD、电解电镀、无电电镀或其他合适工艺。导电层232沉积在绝缘层230中的开口内，并完全延伸通过绝缘层以接触凸块164和接触焊盘176。相应地，导电层232接合至凸块164，以用于在不回焊凸块的情况下的后续电气互连。还可以使用LDA或其他合适工艺来对导电层232进行图案化，并且导电层232作为RDL进行操作，以将电连接从半导体管芯124和170延伸至半导体管芯124和170外部的点。
图5p示出了绝缘或钝化层236共形地涂敷至绝缘层230和导电层232并遵循绝缘层230和导电层232的轮廓。绝缘层236包含一层或多层的光敏低固化温度介电抗蚀剂、光敏复合抗蚀剂、LCP、层压复合膜、具有填充物的绝缘浆料、焊接掩模抗蚀膜、液体模塑料、颗粒模塑料、聚酰亚胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3、或者具有类似绝缘和结构属性的其他材料。使用印刷、旋涂、喷涂、层压或其他合适工艺来沉积绝缘层236。随后，使用UV曝光之后紧跟显影或其他合适工艺，对绝缘层236进行图案化和固化。通过LDA、蚀刻或其他合适工艺来移除绝缘层236的部分，以暴露导电层232的部分。在一个实施例中，在形成绝缘层236之后，如图5n所述形成翘曲平衡层234。
对导电层238进行图案化并将导电层238沉积在导电层232、绝缘层236、SoP封装196和密封剂210之上。导电层238可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或者其他合适导电材料。导电层238的沉积使用PVD、CVD、电解电镀、无电电镀或其他合适工艺。导电层238布置在绝缘层236中的开口中，并完全延伸通过绝缘层以接触导电层232。还可以使用LDA或其他合适工艺来对导电层进行图案化，并且导电层238作为RDL进行操作，以将电连接从半导体管芯124和170延伸通过导电层232至半导体管芯124和170外部的点。根据电信号完整性需求以及半导体管芯124和176的一般配置和设计，将附加导电或RDL层添加至导电层232和238。
图5q示出了绝缘或钝化层242共形地涂敷至绝缘层236和导电层238并遵循绝缘层236和导电层238的轮廓。绝缘层242包含一层或多层的光敏低温度固化介电抗蚀剂、光敏复合抗蚀剂、LCP、层压复合膜、具有填充物的绝缘浆料、焊接掩模抗蚀膜、液体模塑料、颗粒模塑料、聚酰亚胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3、或者具有类似绝缘和结构属性的其他材料。使用印刷、旋涂、喷涂、层压或其他合适工艺来沉积绝缘层242。随后，利用UV曝光之后紧跟显影或其他合适工艺，对绝缘层242进行图案化和固化。通过LDA、蚀刻或其他合适工艺来移除绝缘层242的部分，以暴露导电层238的部分。
使用蒸发、电解电镀、无电电镀、球落或丝网印刷工艺将导电凸块材料沉积在导电层238和绝缘层242之上。在可选的熔剂溶液的情况下，凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸块材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。使用合适的附着或接合工艺将凸块材料接合至导电层238。在一个实施例中，通过将材料加热至高于其熔点来回焊凸块材料，以形成球形的球或凸块244。在一些应用中，第二次回焊凸块244，以改进与接触层238的电接触。在一个实施例中，在具有湿润层、阻挡层和粘合层的UBM之上形成凸块244。还可以将凸块压缩接合或热压缩接合至接触层238。凸块244表示可在导电层238之上形成的一种类型的互连结构。互连结构还可以使用导电浆料、螺柱凸块、微凸块、导电柱、复合互连或其他电气互连。绝缘层230、236和242以及导电层232、238和凸块244一起形成互连结构或扇出型多互连RDL 246。
一并考虑，重构晶片214、翘曲平衡层234和互连结构246形成重构晶片248。使用锯片或激光切割工具250，在凸块244之间、在SoP封装196之间以及通过密封剂210和互连结构246来单体化重构晶片248。在完成互连结构246之后，SoP封装196不需要任何附加激光钻孔或其他加工以形成3-D垂直互连。
图6a示出了由图5q所示的重构晶片248的单体化产生的个体嵌入式SoP扇出型封装252。嵌入式SoP扇出型封装252提供了针对半导体管芯170和包括半导体管芯124的BGA封装166的水平和垂直电气互连，并供应了相比于现有技术公知的封装（例如，图1c所示的3-D eWLB-MLP封装28）的多个优势。例如，嵌入式SoP扇出型封装252不需要使用例如用于eWLB-MLP封装10的如关于图1a所述的激光器在半导体管芯170的占位空间外的外围区中形成穿过密封剂210的开口。通过形成凸块164作为BGA封装166的一部分，以及随后在凸块周围形成密封剂210而不是形成穿过密封剂的开口（例如，激光器形成的开口18），降低了生产嵌入式SoP扇出型封装252的成本。此外，通过经由使用单个凸块工艺形成凸块164而不是使用如关于图1b和1c所述的第一和第二凸块工艺来提供BGA封装166与半导体管芯170之间的垂直互连，减少了加工时间并降低了成本。此外，由于在完成互连结构246之后单体化重构晶片248以使得嵌入式SoP扇出型封装252不需要任何附加激光钻孔或其他加工以形成3-D垂直互连结构，因此减少了加工时间以及成本。通过在沉积密封剂210之前以及在形成互连结构246之前将半导体管芯170安装在BGA封装166之上，在处理期间以及在使用例如关于图1c讨论的SMT将半导体管芯170安装至BGA封装166的同时，降低了损坏晶片的风险。
与如关于图1c讨论的控制3-D eWLB-MLP封装28的总体高度的有限灵活性相比，可以容易地控制嵌入式SoP扇出型封装252的总高度。通过调整BGA封装166、半导体管芯170、密封剂210和互连结构246的高度或厚度来控制嵌入式SoP扇出型封装252的总高度。在一个实施例中，嵌入式SoP扇出型封装252的总厚度或高度小于或等于约1毫米（mm）、或者小于或等于约800 μm，或者小于约600 μm。
图6b示出了包括如先前在图6a中的横截面视图中示出的扇出型封装252内嵌入的SoP封装196的嵌入式SoP扇出型封装252的俯视或平面图。SoP封装196的总体宽度W1小于嵌入式SoP扇出型封装252的总体宽度W2。类似地，SoP封装196的总体长度L1小于嵌入式SoP扇出型封装252的总体长度L2。相应地，SoP封装196的边缘253相对于嵌入式SoP扇出型封装252的边缘254偏移，并且凹陷在封装内并被密封剂210覆盖。在一个实施例中，SoP封装196的宽度W1和长度L1均分别比嵌入式SoP扇出型封装252的宽度W2和长度L2小至少50 μm。
图7示出了与来自图6a的嵌入式SoP扇出型封装252类似的个体嵌入式SoP扇出型封装256。图7包括与来自图6a的翘曲平衡层234类似的翘曲平衡层258。嵌入式SoP扇出型封装256与嵌入式SoP扇出型封装252的不同之处在于：将翘曲平衡层258安装至SoP封装196的背表面222，而不是将翘曲平衡层安装至密封剂210的布置在翘曲平衡层与SoP封装之间的部分。翘曲平衡层258在密封剂210的表面224或228和SoP封装196的背表面222之上形成并接触密封剂210的表面224或228和SoP封装196的背表面222。翘曲平衡层258提供针对嵌入式SoP扇出型封装252的结构支撑，对封装上的应力进行平衡，并减少在后续处理和加工期间封装的翘曲或破裂。根据总体封装配置和设计来调整翘曲平衡层258的翘曲特性，包括翘曲平衡层的厚度以及材料属性。在一个实施例中，翘曲平衡层258具有10至60 μm的范围内的厚度和10至150 ppm/摄氏度的范围内的CTE。在密封剂210和密封剂160的暴露密封剂160的最终背面研磨之后，形成翘曲平衡层258。在形成互连结构246之前、期间或之后形成翘曲平衡层258。
相应地，嵌入式SoP扇出型封装256高效地提供了针对3-D扇出型半导体封装内嵌入的多个半导体管芯的水平和垂直电气互连。嵌入式SoP扇出型封装256还提供了在控制总体封装高度时的灵活性。由于嵌入式SoP扇出型封装256不需要附加激光钻孔或其他加工以在完成RDL互连结构之后形成3-D垂直互连，因此减少了加工时间以及在附加加工的处理期间损坏晶片的风险。此外，通过在单个凸块工艺中形成凸块作为BGA封装的一部分并随后在凸块周围形成密封剂，相对于在通过先前提供的密封剂形成的开口中包括使用多个凸块工艺而形成的凸块的封装，简化了封装形成并使封装形成更便宜。
图8示出了与来自图7的嵌入式SoP扇出型封装256类似的个体嵌入式SoP扇出型封装262。嵌入式SoP扇出型封装262与嵌入式SoP扇出型封装256的不同之处在于：包括密封剂160的被暴露的背表面222，作为最终嵌入式SoP扇出型封装262的一部分。通过对密封剂210和密封剂160进行背面研磨来暴露密封剂160的背表面222，背面研磨在形成互连结构246之前、期间或之后进行。
相应地，嵌入式SoP扇出型封装262高效地提供了针对3-D扇出型半导体封装内嵌入的多个半导体管芯的水平和垂直电气互连。嵌入式SoP扇出型封装262还提供了在控制总体封装高度时的灵活性。由于嵌入式SoP扇出型封装262不需要附加激光钻孔或其他加工以在完成RDL互连结构之后形成3-D垂直互连，因此减少了加工时间以及在附加加工的处理期间损坏晶片的风险。此外，通过在单个凸块工艺中形成凸块作为BGA封装的一部分并随后在凸块周围形成密封剂，相对于在通过先前提供的密封剂形成的开口中包括使用多个凸块工艺而形成的凸块的封装，简化了封装形成并使封装形成更便宜。
图9示出了与来自图8的嵌入式SoP扇出型封装262类似的个体嵌入式SoP扇出型封装266。在嵌入式SoP扇出型封装266中，暴露密封剂160的背表面222，作为最终嵌入式SoP扇出型封装266的一部分。通过在形成互连结构246之前、期间或之后对密封剂210和密封剂160进行背面研磨来暴露密封剂160的背表面222。
嵌入式SoP扇出型封装266与嵌入式SoP扇出型封装262的不同之处在于：包括管芯附着粘合剂190。管芯附着粘合剂190初始布置在衬底144之上并接触衬底144，同时与半导体管芯170分离。管芯附着粘合剂190不像图5e所示且图8中包括的管芯附着带或粘合剂178那样初始布置在半导体管芯170的背表面172之上。由于半导体管芯170被安装至衬底144，因此粘合剂190与半导体管芯的背表面172以及半导体管芯的侧表面相接触，从而接触背表面172与有源表面174之间的半导体管芯。
相应地，嵌入式SoP扇出型封装266高效地提供了针对3-D扇出型半导体封装内嵌入的多个半导体管芯的水平和垂直电气互连。嵌入式SoP扇出型封装266还提供了在控制总体封装高度时的灵活性。由于嵌入式SoP扇出型封装266不需要附加激光钻孔或其他加工以在完成RDL互连结构之后形成3-D垂直互连，因此减少了加工时间以及在附加加工的处理期间损坏晶片的风险。此外，通过在单个凸块工艺中形成凸块作为BGA封装的一部分并随后在凸块周围形成密封剂，相对于在通过先前提供的密封剂形成的开口中包括使用多个凸块工艺而形成的凸块的封装，简化了封装形成并使封装形成更便宜。
图10示出了与来自图6a的嵌入式SoP扇出型封装252类似的个体嵌入式SoP扇出型封装270。在嵌入式SoP扇出型封装270中，密封剂160的背表面222被密封剂210覆盖，作为最终嵌入式SoP扇出型封装270的一部分。可替换地，可以相对于密封剂210暴露背表面222。嵌入式SoP扇出型封装270包括与图5d所示的BGA封装166类似的BGA封装272。BGA封装272与BGA封装166或SoP封装196的不同之处在于：具有实质上与嵌入式SoP扇出型封装270的总体宽度相等的宽度。由此，BGA封装272的侧表面274与嵌入式SoP扇出型封装270的表面的部分同延且同边界。侧表面274不是利用密封剂210覆盖的，而是相对于嵌入式SoP扇出型封装270暴露，这是由于BGA封装272具有实质上与嵌入式SoP扇出型封装270的面积或占位空间相等的面积或占位空间。
相应地，嵌入式SoP扇出型封装270高效地提供了针对3-D扇出型半导体封装内嵌入的多个半导体管芯的水平和垂直电气互连。嵌入式SoP扇出型封装270还提供了在控制总体封装高度时的灵活性。由于嵌入式SoP扇出型封装270不需要附加激光钻孔或其他加工以在完成RDL互连结构之后形成3-D垂直互连，因此减少了加工时间以及在附加加工的处理期间损坏晶片的风险。此外，通过在单个凸块工艺中形成凸块作为BGA封装的一部分并随后在凸块周围形成密封剂，相对于在通过先前提供的密封剂形成的开口中包括使用多个凸块工艺而形成的凸块的封装，简化了封装形成并使封装形成更便宜。
从图5e或5f继续，图11a示出了与以背表面172定向衬底144的第二表面148的方式将半导体管芯170安装至衬底144的BGA封装166类似的BGA封装280。使用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压或其他合适涂敷器，将密封剂模塑料或底部填充278沉积在半导体管芯170周围、在衬底144之上、以及在凸块164周围。密封剂278可以是聚合物复合材料，例如，具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯或具有适当填充物的聚合物。在一个实施例中，密封剂278内包括的填充物包括液相、粉末相或晶粒相下的大小小于或等于约100 μm的颗粒。密封剂278是不导电的，提供物理支撑，并在环境上保护半导体器件免于外部元件和污染物。在一个实施例中，使用膜辅助模塑工艺来沉积密封剂278。在将半导体管芯170安装至BGA封装280之后沉积密封剂278，并且，密封剂278不覆盖有源表面174、接触焊盘176或者绝缘层180的顶表面。在对密封剂278回焊或固化之后，通过衬底144、密封剂160和密封剂278来进行单体化，并且还使用锯片或激光切割工具282在凸块164、半导体管芯124和半导体管芯170之间进行单体化至个体BGA封装280。
图11b示出了作为嵌入式SoP扇出型封装286的一部分而包括的来自图11a的BGA封装280。在如图11a所示的BGA封装280的单体化之后，根据针对如图5i-5q所述的SoP封装252概述的工艺，将BGA封装形成为嵌入式SoP扇出型封装286。可以利用或不利用与图6a所示的翘曲平衡层234类似的翘曲平衡层制成嵌入式SoP扇出型封装286。相应地，嵌入式SoP扇出型封装280高效地提供了针对3-D扇出型半导体封装内嵌入的多个半导体管芯的水平和垂直电气互连。嵌入式SoP扇出型封装280还提供了在控制总体封装高度时的灵活性。由于嵌入式SoP扇出型封装280不需要附加激光钻孔或其他加工以在完成RDL互连结构之后形成3-D垂直互连，因此减少了加工时间以及在附加加工的处理期间损坏晶片的风险。此外，通过在单个凸块工艺中形成凸块作为BGA封装的一部分并随后在凸块周围形成密封剂，相对于在通过先前提供的密封剂形成的开口中包括使用多个凸块工艺而形成的凸块的封装，简化了封装形成并使封装形成更便宜。
与图5g类似，图12a示出了与以半导体管芯的背表面292定向衬底144的第二表面148的方式将半导体管芯290安装至衬底144的SoP封装196类似的SoP封装308。半导体管芯290与来自图5e的半导体管芯170类似，并包括与背表面292相对的有源表面294。有源表面294包括接触焊盘296以及共形地涂敷在有源表面之上的绝缘或钝化层298。通过LDA、蚀刻或其他工艺来移除绝缘层298的部分，以在绝缘层298中形成开口300，从而暴露接触焊盘296。
对导电层304进行图案化并将导电层304沉积在有源半导体管芯290、绝缘层298和接触焊盘296之上。导电层304可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或者其他合适导电材料。导电层304的沉积使用PVD、CVD、电解电镀、无电电镀或其他合适工艺。导电层304沉积在绝缘层298之上以及绝缘层298中的开口300内，并连接至接触焊盘296，以作为RDL进行操作并将电连接从半导体管芯290延伸至半导体管芯290外部的点。不同于接触焊盘296，导电层304未被绝缘层298覆盖，并因此在半导体管芯290被安装至衬底144时相对于绝缘层暴露。
[0082] 在与图5e和5f所述的工艺类似的工艺中将半导体管芯290安装至衬底144之后，使用锯片或激光切割工具306，在凸块164、半导体管芯124和半导体管芯290之间单体化衬底144和密封剂160，以形成个体SoP封装308。
在图12b中，示出了经历与图5i-5l中的SoP封装196所经历的步骤类似的附加封装的SoP封装308。图12b示出了将SoP封装308安装至分别与图5i所示的载体200、载体带202和热可释放层204类似的载体312、载体带314和热可释放层316。使用拾取和放置操作将SoP封装308安装在载体312之上，使得凸块164的部分沉积在热可释放层316的部分的厚度内并被热可释放层316的部分包围。类似地，半导体管芯290的包括绝缘层298和导电层304的部分也沉积在热可释放层316或者单层载体带或粘合剂的厚度内并被其包围。
图12b还示出了在载体312之上以及在SoP封装308之上和周围形成与密封剂或模塑料210类似的密封剂或模塑料320，类似于图5k和5l所示的工艺。在一个实施例中，在载体312之上预先分配或层压密封剂320，并且然后如与图5k和5l类似的工艺中所述使用压缩模塑来对密封剂320进行固化。在SoP封装308的密封之后，形成密封剂320的底表面322，并且底表面322沿密封剂与热可释放层316之间的界面延伸。密封剂320的底表面322凹陷或者相对于导电层304的底表面324垂直偏移，以产生底表面322与底表面324之间的相隔（stand-off）距离。以与如关于图5m所述对载体200、载体带202和热可释放层204的移除类似的方式移除载体312、载体带314和热可释放层316，使得暴露包括底表面324的导电层304，以便随后与后续形成的互连结构互连。
图12c示出了作为嵌入式SoP扇出型封装328的一部分而嵌入的来自图12b的密封SoP封装308。在如上所述形成密封剂320和移除载体312、载体带314和热可释放层316之后，根据针对如图5m-5q所述的SoP封装252概述的工艺来形成嵌入式SoP扇出型封装328。在嵌入式SoP扇出型封装328中，在与互连结构246的形成类似的工艺中形成互连结构330。如图12c所示，互连结构330包括与共形地涂敷至以下各项且具有遵循以下各项的轮廓的第一表面的来自图5o的绝缘层230类似的绝缘层331：密封剂320、绝缘层298、导电层304和凸块164。绝缘层331具有与第一表面相对的第二平表面。互连结构330还包括与通过导电层304而与半导体管芯290的接触焊盘296电连接的来自图5o的导电层232类似的导电层332。互连结构330操作以将电连接从半导体管芯124和290延伸至嵌入式SoP扇出型封装328外部的点。此外，可以利用或不利用与图6a所示的层234类似的翘曲平衡层制成嵌入式SoP扇出型封装328。
相应地，嵌入式SoP扇出型封装328高效地提供了针对3-D扇出型半导体封装内嵌入的多个半导体管芯的水平和垂直电气互连。嵌入式SoP扇出型封装328还提供了在控制总体封装高度时的灵活性。由于嵌入式SoP扇出型封装328不需要附加激光钻孔或其他加工以在完成RDL互连结构之后形成3-D垂直互连，因此减少了加工时间以及在附加加工的处理期间损坏晶片的风险。此外，通过在单个凸块工艺中形成凸块作为BGA封装的一部分并随后在凸块周围形成密封剂，相对于在通过先前提供的密封剂形成的开口中包括使用多个凸块工艺而形成的凸块的封装，简化了封装形成并使封装形成更便宜。
与图5g和12a类似，图13a示出了以半导体管芯的背表面336定向衬底144的第二表面148的方式将半导体管芯334安装至衬底144的BGA阵列封装166。半导体管芯334与来自图5e的半导体管芯170和来自图12a的半导体管芯290类似，并包括与背表面336相对的有源表面338。有源表面338包括接触焊盘340以及共形地涂敷在有源表面之上的绝缘或钝化层342。通过LDA、蚀刻或其他工艺来移除绝缘层342的部分，以在绝缘层342中形成开口，从而暴露接触焊盘340。
绝缘或钝化层344在半导体管芯334的有源表面338之上形成，并具有共形地涂敷至绝缘层342和接触焊盘340且遵循绝缘层342和接触焊盘340的轮廓的第一表面。绝缘层344具有与第一表面相对的第二平表面。绝缘层344包含一层或多层的光敏低固化温度介电抗蚀剂、光敏复合抗蚀剂、焊料掩模抗蚀膜、液体模塑料、SiO2、Si3N4、SiON、Ta2O5、Al2O3、或者具有类似绝缘和结构属性的其他材料。使用印刷、旋涂、喷涂、层压或其他合适工艺来沉积绝缘层344。随后，使用UV曝光之后紧跟显影或其他合适工艺，对绝缘层344进行图案化和固化。通过LDA、蚀刻或其他合适工艺来移除绝缘层344的部分，以形成暴露半导体管芯334的接触焊盘340和绝缘层342的部分的开口，以便包含后续沉积的导电材料。
对导电层346进行图案化并将导电层346沉积在绝缘层344中的开口内以及绝缘层342和接触焊盘340之上。导电层346可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或者其他合适导电材料。导电层346的沉积使用PVD、CVD、电解电镀、无电电镀或其他合适工艺。在一个实施例中，导电层346是通过镀Cu来形成的，并包括电镀种子层。导电层346作为RDL进行操作，以将电连接从半导体管芯334延伸至半导体管芯334外部的点。不同于接触焊盘340，导电层346的顶表面未被绝缘层342或绝缘层344覆盖，并因此在半导体管芯334被安装至BGA封装166时相对于绝缘层342和344暴露。
在与图5e和5f所述的工艺类似的工艺中将半导体管芯334安装至衬底144之后，使用锯片或激光切割工具350，在凸块164、半导体管芯124和半导体管芯334之间单体化衬底144和密封剂160，以分离被安装至BGA封装166的半导体管芯334，从而形成个体SoP封装354。
在图13b中，示出了经历与图5i-5l中的SoP封装196所经历的步骤类似的附加封装的SoP封装354。图13b示出了将SoP封装354安装至分别与图5i所示的载体200、载体带202和热可释放层204类似的载体358、载体带360和热可释放层362。使用拾取和放置操作将SoP封装354安装在载体358之上，使得凸块164的部分沉积在热可释放层362的部分的厚度内并被热可释放层362的部分包围。与热可释放层362的表面一样水平地安装绝缘层344和导电层346，并且在一个实施例中，绝缘层344和导电层346不延伸至热可释放层362或者单层载体带或粘合剂的部分的厚度内，并且不被热可释放层362或者单层载体带或粘合剂的部分包围。可替换地，绝缘层344和导电层346的部分在热可释放层362或者单层载体带或粘合剂的厚度内延伸并被其包围。
图13b还示出了在载体358之上以及在SoP封装354之上和周围形成与来自图5k的密封剂或模塑料210类似的密封剂或模塑料366，类似于图5k和5l所示的工艺。在一个实施例中，在载体358之上预先分配或层压密封剂366，并且然后在与关于图5k和5l所述的工艺类似的工艺中使用压缩模塑来对密封剂366进行固化。在SoP封装354的密封之后，形成密封剂366的底表面368，并且底表面368沿密封剂与热可释放层362之间的界面延伸。密封剂366的底表面368相对于导电层346的底表面370和绝缘层344的底表面372共面。在一个实施例中，绝缘层344的底表面372和导电层346的底表面370相对于密封剂366的底表面368垂直偏移。
在图13c中，与关于图5m所述对载体200、载体带202和热可释放层204的移除类似地，移除载体358、载体带360和热可释放层362。在移除了载体358、载体带360和热可释放层362的情况下，包括底表面370的导电层346和包括底表面372的绝缘层344暴露。在移除了载体358、载体带360和热可释放层362之后，通过利用溶剂的脱模以及等离子体或其他合适工艺来移除绝缘层344，并且通过蚀刻或其他合适工艺来移除导电层346的种子层。在一个实施例中，通过利用激光器374的LDA来移除绝缘层344以及导电层346的种子层。在移除了绝缘层344并移除了导电层346的种子层的情况下，可以相对于密封剂366的底表面368形成浅腔或凹陷。在随后在SoP封装354之上形成互连结构之前制成该腔。
图13d示出了作为嵌入式SoP扇出型封装376的一部分而包括的来自图13c的密封SoP封装354。在如上所述形成了密封剂366并移除了载体358、载体带360、热可释放层362和绝缘层344之后，根据针对如图5m-5q所述的嵌入式SoP封装252概述的工艺来形成嵌入式SoP扇出型封装376。在嵌入式SoP扇出型封装376中，在与互连结构246的形成类似的工艺中形成互连结构378。如图13d所示，互连结构378包括与共形地涂敷至以下各项且具有遵循以下各项的轮廓的第一表面的来自图5o的绝缘层230类似的绝缘层379：密封剂366、绝缘层342、导电层346和凸块164。绝缘层379具有与第一表面相对的第二平表面。互连结构378还包括与通过导电层346而与半导体管芯334的接触焊盘340电连接的来自图5o的导电层232类似的导电层380。互连结构378操作以将电连接从半导体管芯124和334延伸至嵌入式SoP扇出型封装376外部的点。此外，可以利用或不利用与图6a所示的层234类似的翘曲平衡层制成嵌入式SoP扇出型封装376。
相应地，嵌入式SoP扇出型封装376高效地提供了针对3-D扇出型半导体封装内嵌入的多个半导体管芯的水平和垂直电气互连。嵌入式SoP扇出型封装376还提供了在控制总体封装高度时的灵活性。由于嵌入式SoP扇出型封装376不需要附加激光钻孔或其他加工以在完成RDL互连结构之后形成3-D垂直互连，因此减少了加工时间以及在附加加工的处理期间损坏晶片的风险。此外，通过在单个凸块工艺中形成凸块作为BGA封装的一部分并随后在凸块周围形成密封剂，相对于在通过先前提供的密封剂形成的开口中包括使用多个凸块工艺而形成的凸块的封装，简化了封装形成并使封装形成更便宜。
图14示出了与来自图6a的嵌入式SoP扇出型封装252类似的个体嵌入式SoP扇出型封装382。嵌入式SoP扇出型封装382与SoP扇出型封装252的不同之处在于：包括作为SoP封装386的一部分且与来自如参照图6a描述的SoP封装196的凸块164类似的铜凸块384。铜凸块384接合至互连结构388，互连结构388与图6a中的互连结构246类似。在移除了载体200、载体带202和热可释放层204之后，在半导体管芯170之上、在密封剂210之上以及在铜凸块384之上形成互连结构388。在移除了载体200、载体带202和热可释放层204之后但在形成互连结构388之前，在凸块384上应用浅激光钻孔或清洗，以清洗凸块384的表面并改进凸块的接触电阻。通过使用RF蚀刻、LDA、等离子清洗、湿法清洗或其他合适工艺从铜凸块384移除自然出现的氧化物，清洗凸块384。
在半导体管芯170之上、在密封剂210之上以及在铜凸块384之上形成互连结构388。互连结构388包括与互连结构246中的导电层232类似的导电层400。导电层400是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或者不会导致凸块384与导电层400之间的脱层的其他合适导电材料或合金。在一个实施例中，导电层400包括粘合层和阻挡层，阻挡层是TiW、Ti、CrCu、Al或者其他合适金属或金属合金。通过形成与铜凸块384相接触的导电层400，可以将铜凸块384接合至导电层400，以用于在不回焊凸块的情况下的后续电气互连。
相应地，嵌入式SoP扇出型封装382高效地提供了针对3-D扇出型半导体封装内嵌入的多个半导体管芯的水平和垂直电气互连。嵌入式SoP扇出型封装382还提供了在控制总体封装高度时的灵活性。由于嵌入式SoP扇出型封装382不需要附加激光钻孔或其他加工以在完成RDL互连结构之后形成3-D垂直互连，因此减少了加工时间以及在附加加工的处理期间损坏晶片的风险。此外，通过在单个凸块工艺中形成凸块作为BGA封装的一部分并随后在凸块周围形成密封剂，相对于在通过先前提供的密封剂形成的开口中包括使用多个凸块工艺而形成的凸块的封装，简化了封装形成并使封装形成更便宜。
图15示出了与来自图8的嵌入式SoP扇出型封装262类似的个体嵌入式SoP扇出型封装404。在嵌入式SoP扇出型封装404中，从密封剂210暴露密封剂160的背表面222。通过从密封剂160之上移除密封剂210（例如，通过背面研磨）来暴露密封剂160的背表面222。在形成互连结构246之前、期间或之后进行背面研磨以暴露背表面222。可替换地，通过在密封剂210不覆盖密封剂160的背表面222的情况下在SoP封装196周围形成密封剂210，相对于密封剂210暴露密封剂160的背表面222。
利用粘合剂408将金属膜406附着至密封剂210以及密封剂160的背表面222。通过层压或其他合适工艺来形成金属膜406，以提高热性能或提供针对嵌入式SoP扇出型封装404的电磁干扰的屏蔽。
在一个实施例中，粘合剂408是热界面材料（TIM），例如热环氧化物、热环氧树脂、热导电浆料、氧化铝、氧化锌、氮化硼、粉状银、或者在密封剂210上和在密封剂160的背表面222上形成的热脂。金属膜406充当热连接至粘合剂或TIM 408且在密封剂210和密封剂160的背表面222之上安装的散热器。金属膜或散热器406可以是Cu、Al、或者具有高热导率的其他材料。金属膜或散热器406和粘合剂或TIM 408一起形成导热路径，该导热路径辅助由半导体管芯124和170生成的热量的分布和耗散，以提高嵌入式SoP扇出型封装404的热性能。
金属膜406还可以充当屏蔽层，并可以是Al、铁氧体或羰基铁、不锈钢、镍银、低碳钢、硅铁钢、箔、导电树脂、以及能够阻挡或吸收电磁干扰（EMI）、射频干扰（RFI）、谐波失真和其他器件间干扰的其他金属和复合材料。对金属膜406进行图案化，并使用电解电镀、无电电镀、溅射、PVD、CVD或其他合适金属沉积工艺来共形地沉积金属膜406。金属膜406还可以是非金属材料，例如，用于减小EMI和RFI效应的炭黑或薄铝片。对于非金属材料，可以通过层压、喷射或涂抹来涂敷金属膜406。
相应地，嵌入式SoP扇出型封装404高效地提供了针对3-D扇出型半导体封装内嵌入的多个半导体管芯的水平和垂直电气互连。嵌入式SoP扇出型封装404还提供了在控制总体封装高度时的灵活性。由于嵌入式SoP扇出型封装404不需要附加激光钻孔或其他加工以在完成RDL互连结构之后形成3-D垂直互连，因此减少了加工时间以及在附加加工的处理期间损坏晶片的风险。此外，通过在单个凸块工艺中形成凸块作为BGA封装的一部分并随后在凸块周围形成密封剂，相对于在通过先前提供的密封剂形成的开口中包括使用多个凸块工艺而形成的凸块的封装，简化了封装形成并使封装形成更便宜。
图16示出了与来自图8的嵌入式SoP扇出型封装262类似的个体嵌入式SoP扇出型封装412。在嵌入式SoP扇出型封装412中，从密封剂210暴露密封剂160的背表面222。通过从密封剂160之上移除密封剂210（例如，通过背面研磨）来暴露密封剂160的背表面222。在形成互连结构246之前、期间或之后进行背面研磨以暴露背表面222。可替换地，通过在密封剂210不覆盖密封剂160的背表面222的情况下在SoP封装196周围形成密封剂210，相对于密封剂210暴露密封剂160的背表面222。
在密封剂160或210中形成多个开口414，开口414从嵌入式SoP扇出型封装412的背表面222或外表面延伸，部分但不完全通过密封剂。可替换地，多个开口414完全延伸通过密封剂160以暴露衬底144。通过利用激光器416的LDA或浅激光钻孔来形成开口414。开口414包括在半导体管芯124和接合线158周围的外围区域中形成的多个开口414a以及在半导体管芯124和接合线158之上的密封剂160的中央区域中形成的多个开口414b。开口414包括锥形或垂直侧壁，并包括具有圆形、正方形、矩形或任何几何形状的横截面区域。在一个实施例中，开口414a具有比开口414b的深度大的深度，或者可替换地，开口414a和414b具有相等深度。在另一实施例中，开口414b具有比开口414a大的深度。开口414提供了应力消除并减小了嵌入式SoP扇出型封装412的有效厚度，并提供了板上温度循环（TCoB）测试的潜在改进。
相应地，嵌入式SoP扇出型封装412高效地提供了针对3-D扇出型半导体封装内嵌入的多个半导体管芯的水平和垂直电气互连。嵌入式SoP扇出型封装412还提供了在控制总体封装高度时的灵活性。由于嵌入式SoP扇出型封装412不需要附加激光钻孔或其他加工以在完成RDL互连结构之后形成3-D垂直互连，因此减少了加工时间以及在附加加工的处理期间损坏晶片的风险。此外，通过在单个凸块工艺中形成凸块作为BGA封装的一部分并随后在凸块周围形成密封剂，相对于在通过先前提供的密封剂形成的开口中包括使用多个凸块工艺而形成的凸块的封装，简化了封装形成并使封装形成更便宜。
图17示出了与来自图8的嵌入式SoP扇出型封装262类似的个体嵌入式SoP扇出型封装420。在嵌入式SoP扇出型封装420中，从密封剂210暴露密封剂160的背表面222。通过从密封剂160之上移除密封剂210（例如，通过背面研磨）来暴露密封剂160的背表面222。在形成互连结构246之前、期间或之后进行背面研磨以暴露背表面222。可替换地，通过在密封剂210不覆盖密封剂160的背表面222的情况下在SoP封装421周围形成密封剂210，相对于密封剂210暴露密封剂160的背表面222。
图17的嵌入式SoP扇出型封装420与图8的嵌入式SoP扇出型封装262的不同之处在于：利用凸块422而不是接合线158，将半导体管芯124安装至衬底144。通过使用蒸发、电解电镀、无电电镀、球落或丝网印刷工艺将导电凸块材料沉积在接触焊盘132之上，形成凸块422。在可选的熔剂溶液的情况下，凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸块材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。使用合适的附着或接合工艺将凸块材料接合至接触焊盘132。在一个实施例中，通过将材料加热至高于其熔点来回焊凸块材料，以形成球或凸块422。在一些应用中，第二次回焊凸块422，以改进与接触焊盘132的电接触。还可以将凸块422压缩接合或热压缩接合至接触焊盘132。在一个实施例中，凸块422是铜微凸块。利用凸块422以及以半导体管芯的有源表面130定向衬底的方式将半导体管芯124安装至衬底144。
相应地，嵌入式SoP扇出型封装420高效地提供了针对3-D扇出型半导体封装内嵌入的多个半导体管芯的水平和垂直电气互连。嵌入式SoP扇出型封装420还提供了在控制总体封装高度时的灵活性。由于嵌入式SoP扇出型封装420不需要附加激光钻孔或其他加工以在完成RDL互连结构之后形成3-D垂直互连，因此减少了加工时间以及在附加加工的处理期间损坏晶片的风险。此外，通过在单个凸块工艺中形成凸块作为BGA封装的一部分并随后在凸块周围形成密封剂，相对于在通过先前提供的密封剂形成的开口中包括使用多个凸块工艺而形成的凸块的封装，简化了封装形成并使封装形成更便宜。
图18示出了与来自图6a的嵌入式SoP扇出型封装252类似的个体嵌入式SoP扇出型封装430。嵌入式SoP扇出型封装430与SoP扇出型封装252的不同之处在于：包括螺柱线凸块或半切割楔形线接合部432，作为SoP封装434的一部分。螺柱凸块432包括Cu或Au螺柱线凸块、半切割楔形Cu线接合部、或者其他合适导电材料的螺柱凸块或线接合部。与来自图6a所述的SoP封装196的凸块164类似，螺柱凸块432提供了嵌入式SoP扇出型封装430内的垂直互连。螺柱凸块432接合至互连结构436，互连结构436与图6a中的互连结构246类似。在如关于图5m所述移除了载体、载体带和热可释放层之后，在半导体管芯170之上、在密封剂210之上以及在螺柱凸块432之上形成互连结构436。在移除了载体、载体带和热可释放层之后但在形成互连结构436之前，可以在螺柱凸块432上应用浅激光钻孔或清洗，以清洗螺柱凸块的表面并改进螺柱凸块的接触电阻。通过使用RF蚀刻、LDA、等离子清洗、湿法清洗或其他合适工艺移除自然出现的氧化物，清洗螺柱凸块432。
在半导体管芯170之上、在密封剂210之上以及在螺柱凸块432之上形成互连结构436。互连结构436包括与互连结构246中的导电层232类似的导电层438。导电层438是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或者不会导致螺柱凸块432与导电层438之间的脱层的其他合适导电材料或合金。在一个实施例中，导电层438包括粘合层和阻挡层，阻挡层是TiW、Ti、CrCu、Al或者其他合适金属或金属合金。通过形成与螺柱凸块432相接触的导电层438，将螺柱凸块432接合至导电层438，以用于在没有回焊步骤的情况下的后续电气互连。
相应地，嵌入式SoP扇出型封装430高效地提供了针对3-D扇出型半导体封装内嵌入的多个半导体管芯的水平和垂直电气互连。嵌入式SoP扇出型封装430还提供了在控制包括小于1 mm的总体封装高度的总体封装高度时的灵活性。SoP封装434的总体宽度和长度小于嵌入式SoP扇出型封装430的总体宽度和长度。在一个实施例中，与图6b所示的SoP封装196的布置类似，SoP封装434的宽度和长度均分别比嵌入式SoP扇出型封装430的宽度和长度小至少50 μm。螺柱凸块432的高度小于或等于半导体管芯170和管芯附着带178或管芯附着粘合剂190的组合高度。可替换地，螺柱凸块432的高度比半导体管芯170和管芯附着带178或管芯附着粘合剂190的组合高度稍大（例如，大10 μm）。由于嵌入式SoP扇出型封装430不需要附加激光钻孔或其他加工以在完成RDL互连结构之后形成3-D垂直互连，因此减少了加工时间以及在附加加工的处理期间损坏晶片的风险。此外，通过形成螺柱凸块作为BGA封装的一部分并随后在螺柱凸块周围形成密封剂，相对于在通过先前提供的密封剂形成的开口中包括使用多个凸块工艺而形成的凸块的封装，简化了封装形成并使封装形成更便宜。
在图19a-19i中，示意了高效地形成包括水平和垂直互连的3-D SOP扇出型封装的另一工艺。图19a示出了与以半导体管芯的背表面172定向衬底144的第二表面148的方式将半导体管芯170安装至衬底144的来自图5g的SoP封装196类似的SoP封装450。半导体管芯170包括与背表面172相对的有源表面174。有源表面174包括接触焊盘176以及共形地涂敷在有源表面之上的绝缘或钝化层180。通过LDA、蚀刻或其他工艺来移除绝缘层180的部分，以在绝缘层180中形成开口，从而暴露接触焊盘176。
在绝缘层180以及半导体管芯170的有源表面174之上形成绝缘或钝化层452。绝缘层452具有共形地涂敷至绝缘层180和接触焊盘176且遵循绝缘层180和接触焊盘176的轮廓的第一表面。绝缘层452具有与第一表面相对的第二平表面。绝缘层452包含一层或多层的光敏低固化温度介电抗蚀剂、光敏复合抗蚀剂、焊料掩模抗蚀膜、液体模塑料、SiO2、Si3N4、SiON、Ta2O5、Al2O3、或者具有类似绝缘和结构属性的其他材料。使用印刷、旋涂、喷涂、层压或其他合适工艺来沉积绝缘层452。绝缘层452是未经图案化的永久绝缘层，或者可替换地，绝缘层452是临时保护层。
利用布置在半导体管芯的外围区域周围和半导体管芯的占位空间外的凸块164，将半导体管芯170安装至衬底144。如以上参照图5d所述，将凸块164安装至衬底144，以形成由多个球栅阵列封装450组成的SoP封装面板454。凸块164的高度由最终总体封装高度以及其他考虑确定。在一个实施例中，在与图5e和5f所述的工艺类似的工艺中将半导体管芯170安装至衬底144之后，如图5g所示，使用锯片或激光切割工具，在凸块164、半导体管芯124和半导体管芯170之间单体化衬底144和密封剂160。然后，如图5i所示，使用拾取和放置操作，将单体化后的SoP封装450安装至具有载体带和热可释放层的临时载体，以用于如图5k-5q所示的后续加工。可替换地，SoP封装面板454不是在安装半导体管芯170之后立即单体化的，而是保持完整无缺以用于面板或晶片级的后续加工，如以下更详细描述。通过在晶片级将SoP封装450加工为未单体化的面板454，缓解了对临时载体的需要，从而简化了加工。SoP封装面板454还包括基准对齐标记，该基准对齐标记便于形成SoP封装450作为最终嵌入式SoP扇出型封装的一部分所需的附加加工。
图19b示出了在SoP封装面板454之上、在凸块164周围以及在半导体管芯170周围预先分配或层压密封剂或模塑料458。可替换地，可以使用传递模塑或其他合适工艺来涂敷密封剂458。密封剂458可以是聚合物复合材料，例如，具有填充物或纤维的环氧树脂、具有填充物或纤维的环氧丙烯酸酯、或者具有适当填充物或纤维的聚合物。在一个实施例中，密封剂458中的填充物包括液相、粉末相或晶粒相下的大小小于或等于约100 μm的颗粒，并被选择为具有便于在凸块164周围以及在半导体管芯170周围形成密封剂的含量水平和特性。密封剂458中的填充物还被选择为控制翘曲并改进封装可靠性。在SoP封装面板454上分配密封剂458，并且在一个实施例中，在该面板上的中央位置460处（例如，在与图5j所示的交点208类似的四个相邻SoP封装450的角处）分配密封剂458。密封剂458布置在SoP封装面板454之上、布置在绝缘层452之上以及布置在半导体管芯170的有源表面174之上，该有源表面定向远离衬底144，使得向着绝缘层452和有源表面174分配密封剂。因此，形成了包括嵌入式SoP封装450和密封剂458的重构晶片或扇出型衬底462。将SoP封装450一起嵌入到密封剂458中，密封剂458是不导电的，并在环境上保护SoP封装免于外部元件和污染物。
图19c示出了将重构晶片462加载至冲切模具464中。通过在重构晶片462和密封剂458周围移动冲切模具464，或者可替换地，通过将重构晶片462移动至模具中，将冲切模具464与重构晶片462集合在一起。在一个实施例中，冲切模具464仅包括与重构晶片462集合在一起的第一或顶部分，而不包括第二或底模具部分。可替换地，重构晶片462和密封剂458布置在包括多个部分（例如，顶和底部分）的模具内。如图19c所示，将重构晶片462布置在不具有临时载体、载体带或热可释放层的冲切模具464内。在将SoP封装面板454和密封剂458布置在冲切模具464内之后，可以部分或完全对密封剂进行固化。在部分或完全对密封剂458进行固化之后，从冲切模具464移除重构晶片462。
图19d示出了从冲切模具464移除重构晶片462。在一个实施例中，在SoP封装面板454之上形成密封剂458的期望厚度，使得密封剂未覆盖半导体管芯170的有源表面174和凸块164的表面。例如，可以采用膜辅助密封剂工艺，以防止密封剂458覆盖半导体管芯170的有源表面174和凸块164的表面，从而不需要对密封剂458的后续移除。可替换地，密封剂458包括布置在绝缘层452之上且覆盖绝缘层452的表面468、半导体管芯170的有源表面174、以及凸块164的表面。密封剂458的表面468经历利用研磨机470的研磨操作，以对表面进行平坦化并减小密封剂的厚度，以便辅助控制重构晶片462和SoP封装450的翘曲。可替换地，使用化学蚀刻、LDA或其他合适工艺来对密封剂458进行移除和平坦化并暴露凸块164的表面、密封剂的表面472和绝缘层452的表面。凸块164的被暴露的表面可以是锥形的或平面的。对密封剂458的部分的移除便于根据最终封装的设计来调整总体封装高度。在凸块164和绝缘层452上应用包括浅激光钻孔的附加清洗，以清洗凸块和绝缘层的表面，更完全地暴露凸块和绝缘层，并改进凸块的接触电阻。此外，还可以使用利用激光器的LDA、RF蚀刻、等离子清洗或湿法清洗来清洗凸块164并移除氧化物累积。在一个实施例中，凸块164是Cu，并且，通过RF蚀刻来移除在铜凸块164上形成的自然出现的氧化物。
从图19d继续，图19e示出了作为未经图案化的永久绝缘层452a而形成的未经图案化的绝缘层452。通过利用激光器476的LDA来移除永久绝缘层452a的部分，以形成开口478。还通过蚀刻或其他合适工艺来形成开口478。开口478完全延伸通过永久绝缘层452a以暴露半导体管芯170的接触焊盘176，并通过后续形成互连结构来提供与接触焊盘的后续电连接。
同样从图19d继续，图19f示出了作为临时保护层452b而形成的未经图案化的绝缘层452。通过利用激光器480的LDA来移除临时保护层452b，以形成开口、腔或凹陷482。还通过使用溶剂、蚀刻、湿法化学蚀刻或其他合适工艺对临时保护层452b进行移除或脱模，形成开口482。开口482暴露包括绝缘层180和接触焊盘176的半导体管芯170，并在半导体管芯170的占位空间内提供绝缘层180与密封剂458的表面472之间的垂直偏移。对临时保护层452b的移除还允许通过形成互连结构而在凸块164与接触焊盘176之间进行的后续电连接。
从图19e或19f继续，图19g-19i示出了与关于图5q描述的互连结构246类似的互连结构或扇出型多互连RDL的形成。图19g-19i的互连结构通过凸块164和接触焊盘176提供了半导体管芯124、半导体管芯170和半导体管芯外部的点之间的电气互连。在移除了绝缘层452的至少部分（例如，永久绝缘层452a或临时保护层452b）之后，图19g示出了通过绝缘或钝化层486的沉积和图案化以及导电层488的沉积和图案化，在重构晶片462之上形成互连结构的第一部分。
绝缘层486被共形地涂敷至以下各项并具有遵循以下各项的轮廓的第一表面：密封剂458、绝缘层452、绝缘层180、开口478、接触焊盘176和凸块164。绝缘层486具有与第一表面相对的第二平表面。绝缘层486包含一层或多层的光敏低固化温度介电抗蚀剂、光敏复合抗蚀剂、LCP、层压复合膜、具有填充物的绝缘浆料、焊接掩模抗蚀膜、液体模塑料、颗粒模塑料、聚酰亚胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3、或者具有类似绝缘和结构属性的其他材料。使用印刷、旋涂、喷涂、层压或其他合适工艺来沉积绝缘层486。随后，使用UV曝光之后紧跟显影或其他合适工艺，对绝缘层486进行图案化和固化。通过LDA、蚀刻或其他合适工艺来移除绝缘层486的部分，以形成暴露半导体管芯170的接触焊盘176和凸块164的开口。还可以在移除绝缘层486的部分期间或之后清洗凸块164和接触焊盘176，如先前关于图5m或19d中的凸块164所描述。
对导电层488进行图案化并将导电层488沉积在密封剂458、半导体管芯170、绝缘层180和绝缘层486之上。导电层488可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或者不会导致凸块164与导电层488之间的脱层的其他合适导电材料或合金。在一个实施例中，导电层488包括粘合层和阻挡层，阻挡层是焊料可湿材料，例如CrCu、Au、TiCu合金、Ni或NiV合金。导电层488的沉积使用PVD、CVD、电解电镀、无电电镀或其他合适工艺。导电层488沉积在绝缘层486中的开口内，并完全延伸通过绝缘层以接触凸块164和接触焊盘176。相应地，导电层488接合至凸块164，以用于在不回焊凸块的情况下的后续电气互连。还可以使用LDA或其他合适工艺来对导电层488进行图案化，并且导电层488作为RDL进行操作，以将电连接从半导体管芯124和170延伸至半导体管芯外部的点。
图19h示出了绝缘或钝化层490共形地涂敷至绝缘层486和导电层488并遵循绝缘层486和导电层488的轮廓。绝缘层490包含一层或多层的光敏低固化温度介电抗蚀剂、光敏复合抗蚀剂、LCP、层压复合膜、具有填充物的绝缘浆料、焊接掩模抗蚀膜、液体模塑料、颗粒模塑料、聚酰亚胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3、或者具有类似绝缘和结构属性的其他材料。使用印刷、旋涂、喷涂、层压或其他合适工艺来沉积绝缘层490。随后，使用UV曝光之后紧跟显影或其他合适工艺，对绝缘层490进行图案化和固化。通过LDA、蚀刻或其他合适工艺来移除绝缘层490的部分，以暴露导电层488的部分。
对导电层492进行图案化并将导电层492沉积在导电层488、绝缘层490、SoP封装450和密封剂458之上。导电层492可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或者其他合适导电材料。导电层492的沉积使用PVD、CVD、电解电镀、无电电镀或其他合适工艺。导电层492布置在绝缘层490中的开口中，并完全延伸通过绝缘层以接触导电层488。还可以使用LDA或其他合适工艺来对导电层492进行图案化，并且导电层492作为RDL进行操作，以将电连接从半导体管芯124和170延伸通过导电层488至半导体管芯124和170外部的点。根据电信号完整性需求以及半导体管芯124和176的一般配置和设计，将附加导电或RDL层添加至导电层488和492。
图19i示出了绝缘或钝化层494共形地涂敷至绝缘层490和导电层492并遵循绝缘层490和导电层492的轮廓。绝缘层494包含一层或多层的光敏低温度固化介电抗蚀剂、光敏复合抗蚀剂、LCP、层压复合膜、具有填充物的绝缘浆料、焊接掩模抗蚀膜、液体模塑料、颗粒模塑料、聚酰亚胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3、或者具有类似绝缘和结构属性的其他材料。使用印刷、旋涂、喷涂、层压或其他合适工艺来沉积绝缘层494。随后，利用UV曝光之后紧跟显影或其他合适工艺，对绝缘层494进行图案化和固化。通过LDA、蚀刻或其他合适工艺来移除绝缘层494的部分，以暴露导电层492的部分。
使用蒸发、电解电镀、无电电镀、球落或丝网印刷工艺将导电凸块材料沉积在导电层492和绝缘层494之上。在可选的熔剂溶液的情况下，凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸块材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。使用合适的附着或接合工艺将凸块材料接合至导电层492。在一个实施例中，通过将材料加热至高于其熔点来回焊凸块材料，以形成球形的球或凸块496。在一些应用中，第二次回焊凸块496，以改进与导电层492的电接触。在一个实施例中，在具有湿润层、阻挡层和粘合层的UBM之上形成凸块496。还可以将凸块压缩接合或热压缩接合至导电层492。凸块496表示可在导电层492之上形成的一种类型的互连结构。互连结构还可以使用导电浆料、螺柱凸块、微凸块、导电柱、复合互连或其他电气互连。绝缘层486、490和494以及导电层488、492和凸块496一起形成互连结构或扇出型多互连RDL 498。
使用锯片或激光切割工具500，在凸块496之间、在SoP封装450之间以及通过密封剂458和互连结构498单体化重构晶片462和互连结构498，以形成嵌入式SoP扇出型封装502。在完成互连结构498之后，SoP封装450不需要任何附加激光钻孔或其他加工以形成3-D垂直互连。在完成互连结构498和单体化之后，嵌入式SoP扇出型封装502经历针对质量控制和重量保证的最终检查，并且然后为下一级组装准备好。
相应地，嵌入式SoP扇出型封装502高效地提供了针对3-D扇出型半导体封装内嵌入的多个半导体管芯的水平和垂直电气互连。嵌入式SoP扇出型封装502还提供了在控制总体封装高度时的灵活性。由于嵌入式SoP扇出型封装502不需要附加激光钻孔或其他加工以在完成RDL互连结构之后形成3-D垂直互连，因此减少了加工时间以及在附加加工的处理期间损坏晶片的风险。此外，通过在单个凸块工艺中形成凸块作为BGA封装的一部分并随后在凸块周围形成密封剂，相对于在通过先前提供的密封剂形成的开口中包括使用多个凸块工艺而形成的凸块的封装，简化了封装形成并使封装形成更便宜。
图20示出作为嵌入式SoP扇出型封装504的一部分而嵌入的来自图19f的密封SoP封装450。在如以上关于图19f所述形成了密封剂458并移除了临时保护层452b之后，根据针对如图19g-19i所述的SoP封装502概述的工艺来形成嵌入式SoP扇出型封装504。在嵌入式SoP扇出型封装504中，在与互连结构498的形成类似的工艺中形成互连结构506。如图20所示，互连结构506包括与共形地涂敷至以下各项且具有遵循以下各项的轮廓的第一表面的来自图19g的绝缘层486类似的绝缘层508：密封剂458、绝缘层180、导电层176和凸块164。绝缘层508具有与第一表面相对的第二平表面。互连结构506还包括与电连接至半导体管芯170的接触焊盘176的来自图19g的导电层488类似的导电层510。互连结构506操作以将电连接从半导体管芯124和170延伸至嵌入式SoP扇出型封装504外部的点。
相应地，嵌入式SoP扇出型封装504高效地提供了针对3-D扇出型半导体封装内嵌入的多个半导体管芯的水平和垂直电气互连。嵌入式SoP扇出型封装504还提供了在控制总体封装高度时的灵活性。由于嵌入式SoP扇出型封装504不需要附加激光钻孔或其他加工以在完成RDL互连结构之后形成3-D垂直互连，因此减少了加工时间以及在附加加工的处理期间损坏晶片的风险。此外，通过在单个凸块工艺中形成凸块作为BGA封装的一部分并随后在凸块周围形成密封剂，相对于在通过先前提供的密封剂形成的开口中包括使用多个凸块工艺而形成的凸块的封装，简化了封装形成并使封装形成更便宜。
尽管详细示意了本实用新型的一个或多个实施例，但是本领域技术人员将意识到，在不脱离如权利要求中阐述的本实用新型的范围的前提下，可以进行对这些实施例的修改和变型。

Claims (15)

1.一种半导体器件，其特征在于包括：
球栅阵列封装，包括多个第一凸块；
第一半导体管芯，布置在所述球栅阵列封装之上所述第一凸块之间；
第一密封剂，沉积在所述球栅阵列封装和第一半导体管芯之上；以及
扇出型互连结构，在所述第一凸块和第一半导体管芯之上形成并电连接至所述第一凸块和第一半导体管芯。
2.根据权利要求1所述的半导体器件，其中，所述球栅阵列封装还包括：
衬底；
第二半导体管芯，布置在所述衬底之上并电连接至所述衬底，其中，所述第一凸块在所述衬底之上与所述第二半导体管芯相对地形成；以及
第二密封剂，沉积在所述第二半导体管芯和衬底之上。
3.根据权利要求1所述的半导体器件，其中，所述第一半导体管芯包括比所述第一凸块的高度小的高度。
4.根据权利要求1所述的半导体器件，还包括：翘曲平衡层，在所述球栅阵列封装之上形成。
5.一种半导体器件，其特征在于包括：
半导体封装，包括多个第一互连结构；
第一半导体管芯，布置在所述半导体封装之上所述第一互连结构之间；
第一密封剂，沉积在所述半导体封装和第一半导体管芯之上；以及
第二互连结构，在所述第一互连结构和第一半导体管芯之上形成并电连接至所述第一互连结构和第一半导体管芯。
6.根据权利要求5所述的半导体器件，其中，所述半导体封装还包括：
衬底；
第二半导体管芯，安装至所述衬底；以及
第二密封剂，与所述第一互连结构相对地布置在所述第二半导体管芯和衬底之上。
7.根据权利要求5所述的半导体器件，还包括：翘曲平衡层，在所述半导体封装之上形成。
8.根据权利要求5所述的半导体器件，其中，所述半导体封装的表面从所述第一密封剂暴露。
9.根据权利要求5所述的半导体器件，其中，所述第二互连结构包括：
第一绝缘层；
第一导电层，在所述第一绝缘层之上形成并电连接至所述第一互连结构和所述第一半导体管芯；
第二绝缘层，在所述第一导电层之上形成；以及
多个凸块，在所述第二绝缘层之上形成并电连接至所述第一导电层。
10.一种半导体器件，其特征在于包括：
半导体封装，包括多个第一互连结构；
第一半导体管芯，布置在所述半导体封装之上所述第一互连结构之间；以及
第二互连结构，在所述第一互连结构和第一半导体管芯之上形成并电连接至所述第一互连结构和第一半导体管芯。
11.根据权利要求10所述的半导体器件，其中，所述半导体封装还包括：
衬底；
第二半导体管芯，布置在所述衬底之上并电连接至所述衬底，其中，所述第一互连结构在所述衬底之上与所述第二半导体管芯相对地形成；以及
密封剂，沉积在所述第二半导体管芯和衬底之上。
12.根据权利要求10所述的半导体器件，其中，所述第一半导体管芯包括比所述第一互连结构的高度小的高度。
13.根据权利要求10所述的半导体器件，还包括：翘曲平衡层，在所述半导体封装之上形成。
14.根据权利要求10所述的半导体器件，还包括：屏蔽层或散热片，在所述半导体封装之上形成。
15.根据权利要求10所述的半导体器件，还包括：密封剂，沉积在所述半导体封装和第一半导体管芯之上，所述密封剂中具有处于所述半导体器件的外表面处的开口，以提供应力消除。
CN2013202314131U 2012-06-21 2013-05-02 形成嵌入式sop扇出型封装的半导体器件 Expired - Lifetime CN203312275U (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/529,918 2012-06-21
US13/529,918 US9385006B2 (en) 2012-06-21 2012-06-21 Semiconductor device and method of forming an embedded SOP fan-out package

Publications (1)

Publication Number Publication Date
CN203312275U true CN203312275U (zh) 2013-11-27

Family

ID=49618461

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201310158510.7A Active CN103515252B (zh) 2012-06-21 2013-05-02 形成嵌入式sop扇出型封装的半导体器件和方法
CN2013202314131U Expired - Lifetime CN203312275U (zh) 2012-06-21 2013-05-02 形成嵌入式sop扇出型封装的半导体器件

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201310158510.7A Active CN103515252B (zh) 2012-06-21 2013-05-02 形成嵌入式sop扇出型封装的半导体器件和方法

Country Status (4)

Country Link
US (2) US9385006B2 (zh)
CN (2) CN103515252B (zh)
SG (1) SG10201510232QA (zh)
TW (1) TWI590400B (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015149364A1 (zh) * 2014-04-04 2015-10-08 史利利 印制线路板
CN105261595A (zh) * 2014-04-22 2016-01-20 美国博通公司 用于半导体封装件的重构技术
CN109887890A (zh) * 2019-01-30 2019-06-14 杭州晶通科技有限公司 一种扇出型倒置封装结构及其制备方法
CN109940285A (zh) * 2019-03-22 2019-06-28 苏州福唐智能科技有限公司 一种扇出形晶圆激光隐形切割方法
CN110660809A (zh) * 2018-06-28 2020-01-07 西部数据技术公司 包含分支存储器裸芯模块的垂直互连的半导体装置
CN110880457A (zh) * 2018-09-05 2020-03-13 台湾积体电路制造股份有限公司 半导体封装件及其形成方法
US11309294B2 (en) 2018-09-05 2022-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out packages and methods of forming the same

Families Citing this family (105)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9196509B2 (en) * 2010-02-16 2015-11-24 Deca Technologies Inc Semiconductor device and method of adaptive patterning for panelized packaging
US9385006B2 (en) * 2012-06-21 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming an embedded SOP fan-out package
US10622310B2 (en) 2012-09-26 2020-04-14 Ping-Jung Yang Method for fabricating glass substrate package
US9184066B2 (en) * 2012-11-16 2015-11-10 Infineon Technologies Ag Chip arrangements and methods for manufacturing a chip arrangement
TWI490508B (zh) * 2012-12-17 2015-07-01 Princo Corp 軟性測試裝置及其測試方法
TWI499013B (zh) 2013-01-22 2015-09-01 矽品精密工業股份有限公司 半導體封裝件及其製法
US9953907B2 (en) * 2013-01-29 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. PoP device
US9016552B2 (en) * 2013-03-15 2015-04-28 Sanmina Corporation Method for forming interposers and stacked memory devices
TWI533421B (zh) * 2013-06-14 2016-05-11 日月光半導體製造股份有限公司 半導體封裝結構及半導體製程
US9478485B2 (en) 2013-06-28 2016-10-25 STATS ChipPAC Pte. Ltd. Semiconductor device and method of stacking semiconductor die on a fan-out WLCSP
US9093415B2 (en) * 2013-09-25 2015-07-28 Stats Chippac Ltd. Integrated circuit packaging system with heat spreader and method of manufacture thereof
US9406588B2 (en) * 2013-11-11 2016-08-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method thereof
US9224709B2 (en) * 2014-02-13 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including an embedded surface mount device and method of forming the same
CN104851868B (zh) * 2014-02-14 2017-08-11 恒劲科技股份有限公司 封装装置及其制作方法
CN104851869B (zh) * 2014-02-14 2017-09-22 恒劲科技股份有限公司 封装装置及其制作方法
US9318452B2 (en) * 2014-03-21 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US9735129B2 (en) 2014-03-21 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US20150279824A1 (en) * 2014-03-28 2015-10-01 Vijay K. Nair Electronic package and method of forming an electronic package
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
TWI555105B (zh) * 2014-03-31 2016-10-21 英凡薩斯公司 具延伸通過密封連接器所耦接之堆疊端子的微電子組件的製造
US9443806B2 (en) * 2014-05-09 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Chip packages and methods of manufacturing the same
TWI559477B (zh) * 2014-06-03 2016-11-21 力成科技股份有限公司 縮短支撐柱之金屬柱銲接晶片連接結構
US9859265B2 (en) 2014-06-06 2018-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and methods of forming the same
US20160013076A1 (en) * 2014-07-14 2016-01-14 Michael B. Vincent Three dimensional package assemblies and methods for the production thereof
US10157823B2 (en) * 2014-10-31 2018-12-18 Qualcomm Incorporated High density fan out package structure
US9589936B2 (en) * 2014-11-20 2017-03-07 Apple Inc. 3D integration of fanout wafer level packages
DE102015102535B4 (de) 2015-02-23 2023-08-03 Infineon Technologies Ag Verbundsystem und Verfahren zum haftenden Verbinden eines hygroskopischen Materials
US9786623B2 (en) * 2015-03-17 2017-10-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming PoP semiconductor device with RDL over top package
US10068862B2 (en) 2015-04-09 2018-09-04 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a package in-fan out package
US9502397B1 (en) * 2015-04-29 2016-11-22 Deca Technologies, Inc. 3D interconnect component for fully molded packages
US9881902B2 (en) 2015-08-05 2018-01-30 Mediatek Inc. Semiconductor package, semiconductor device using the same and manufacturing method thereof
TWI559419B (zh) * 2015-08-21 2016-11-21 力成科技股份有限公司 使用模封互連基板製程之柱頂互連（ｐｔｉ）型態半導體封裝構造及其製造方法
CN105020559A (zh) * 2015-08-24 2015-11-04 吴刚 一种太阳能供电且用于led显示装置的安装组件
CN106486453A (zh) * 2015-08-25 2017-03-08 力成科技股份有限公司 一种柱顶互连型态半导体封装构造及其制造方法
US10304769B2 (en) * 2015-08-27 2019-05-28 Intel Corporation Multi-die package
US20170098629A1 (en) 2015-10-05 2017-04-06 Mediatek Inc. Stacked fan-out package structure
US10056338B2 (en) * 2015-10-27 2018-08-21 Micron Technology, Inc. Methods of forming semiconductor packages including molding semiconductor chips of the semiconductor packages
TWI721026B (zh) * 2015-10-30 2021-03-11 日商半導體能源研究所股份有限公司 電容器、半導體裝置、模組以及電子裝置的製造方法
US10032727B2 (en) * 2015-11-24 2018-07-24 International Business Machines Corporation Electrical package including bimetal lid
US10319689B2 (en) * 2015-12-01 2019-06-11 Nxp Usa, Inc. Antenna assembly for wafer level packaging
KR20170067426A (ko) * 2015-12-08 2017-06-16 앰코 테크놀로지 코리아 주식회사 반도체 패키지의 제조 방법 및 이를 이용한 반도체 패키지
KR102045235B1 (ko) * 2016-03-31 2019-11-15 삼성전자주식회사 전자부품 패키지 및 그 제조방법
US9659911B1 (en) * 2016-04-20 2017-05-23 Powertech Technology Inc. Package structure and manufacturing method thereof
US9786515B1 (en) * 2016-06-01 2017-10-10 Nxp Usa, Inc. Semiconductor device package and methods of manufacture thereof
US10600748B2 (en) 2016-06-20 2020-03-24 Samsung Electronics Co., Ltd. Fan-out semiconductor package
US9935068B2 (en) * 2016-06-21 2018-04-03 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
US10312205B2 (en) 2016-06-23 2019-06-04 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
KR102005352B1 (ko) * 2016-06-23 2019-07-31 삼성전자주식회사 팬-아웃 반도체 패키지
US10186499B2 (en) * 2016-06-30 2019-01-22 Intel IP Corporation Integrated circuit package assemblies including a chip recess
US10141198B2 (en) * 2016-07-08 2018-11-27 Dyi-chung Hu Electronic package and manufacturing method thereof
US10229859B2 (en) * 2016-08-17 2019-03-12 Advanced Semiconductor Engineering, Inc. Semiconductor device package and a method of manufacturing the same
US10418341B2 (en) * 2016-08-31 2019-09-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming SIP with electrical component terminals extending out from encapsulant
KR101994748B1 (ko) * 2016-09-12 2019-07-01 삼성전기주식회사 팬-아웃 반도체 패키지
US10573601B2 (en) 2016-09-19 2020-02-25 Deca Technologies Inc. Semiconductor device and method of unit specific progressive alignment
US10157803B2 (en) 2016-09-19 2018-12-18 Deca Technologies Inc. Semiconductor device and method of unit specific progressive alignment
JP2018049938A (ja) 2016-09-21 2018-03-29 株式会社東芝 半導体装置
KR101973431B1 (ko) * 2016-09-29 2019-04-29 삼성전기주식회사 팬-아웃 반도체 패키지
KR20190067839A (ko) * 2016-10-04 2019-06-17 스카이워크스 솔루션즈, 인코포레이티드 오버몰드 구조를 갖는 양면 라디오-주파수 패키지
US10600679B2 (en) * 2016-11-17 2020-03-24 Samsung Electronics Co., Ltd. Fan-out semiconductor package
US11049734B2 (en) * 2016-11-29 2021-06-29 Pep Innovation Pte. Ltd. Method of packaging chip and chip package structure
CN108231607A (zh) * 2016-11-29 2018-06-29 Pep创新私人有限公司 芯片封装方法及封装结构
US11625523B2 (en) 2016-12-14 2023-04-11 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips
CN108288616B (zh) 2016-12-14 2023-04-07 成真股份有限公司 芯片封装
US10497650B2 (en) * 2017-04-13 2019-12-03 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US10447274B2 (en) 2017-07-11 2019-10-15 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
US10957679B2 (en) 2017-08-08 2021-03-23 iCometrue Company Ltd. Logic drive based on standardized commodity programmable logic semiconductor IC chips
US10636757B2 (en) * 2017-08-29 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit component package and method of fabricating the same
US10630296B2 (en) 2017-09-12 2020-04-21 iCometrue Company Ltd. Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
US10861814B2 (en) * 2017-11-02 2020-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out packages and methods of forming the same
US20190164948A1 (en) * 2017-11-27 2019-05-30 Powertech Technology Inc. Package structure and manufacturing method thereof
KR102179165B1 (ko) 2017-11-28 2020-11-16 삼성전자주식회사 캐리어 기판 및 상기 캐리어 기판을 이용한 반도체 패키지의 제조방법
US11114315B2 (en) 2017-11-29 2021-09-07 Pep Innovation Pte. Ltd. Chip packaging method and package structure
US11232957B2 (en) 2017-11-29 2022-01-25 Pep Inovation Pte. Ltd. Chip packaging method and package structure
US11610855B2 (en) 2017-11-29 2023-03-21 Pep Innovation Pte. Ltd. Chip packaging method and package structure
US11233028B2 (en) 2017-11-29 2022-01-25 Pep Inovation Pte. Ltd. Chip packaging method and chip structure
CN110729270A (zh) * 2019-03-04 2020-01-24 Pep创新私人有限公司 芯片封装方法及封装结构
US10468339B2 (en) 2018-01-19 2019-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. Heterogeneous fan-out structure and method of manufacture
US10504841B2 (en) * 2018-01-21 2019-12-10 Shun-Ping Huang Semiconductor package and method of forming the same
US10608642B2 (en) 2018-02-01 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells
US10623000B2 (en) 2018-02-14 2020-04-14 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
JP7046639B2 (ja) * 2018-02-21 2022-04-04 新光電気工業株式会社 配線基板及びその製造方法
US10608638B2 (en) 2018-05-24 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US11309334B2 (en) 2018-09-11 2022-04-19 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
CN109743846B (zh) * 2018-09-27 2021-08-20 常州市武进三维电子有限公司 新能源汽车的镂空柔性线路板的制作工艺
US11421316B2 (en) 2018-10-26 2022-08-23 Applied Materials, Inc. Methods and apparatus for controlling warpage in wafer level packaging processes
US11211334B2 (en) 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US10867929B2 (en) * 2018-12-05 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods of forming the same
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
KR20200142730A (ko) * 2019-06-13 2020-12-23 삼성전기주식회사 인쇄회로기판
US20200402958A1 (en) * 2019-06-20 2020-12-24 Advanced Semiconductor Engineering, Inc. Semiconductor device packages and methods of manufacturing the same
US11049844B2 (en) 2019-07-01 2021-06-29 International Business Machines Corporation Semiconductor wafer having trenches with varied dimensions for multi-chip modules
US10985154B2 (en) 2019-07-02 2021-04-20 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits
US11227838B2 (en) 2019-07-02 2022-01-18 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits
US11887930B2 (en) 2019-08-05 2024-01-30 iCometrue Company Ltd. Vertical interconnect elevator based on through silicon vias
US10834839B1 (en) * 2019-08-27 2020-11-10 International Business Machines Corporation Barrier for hybrid socket movement reduction
US10943883B1 (en) 2019-09-19 2021-03-09 International Business Machines Corporation Planar wafer level fan-out of multi-chip modules having different size chips
US11637056B2 (en) 2019-09-20 2023-04-25 iCometrue Company Ltd. 3D chip package based on through-silicon-via interconnection elevator
US11600526B2 (en) 2020-01-22 2023-03-07 iCometrue Company Ltd. Chip package based on through-silicon-via connector and silicon interconnection bridge
US11342282B2 (en) * 2020-02-21 2022-05-24 Advanced Semiconductor Engineering, Inc. Semiconductor device package including a reinforcement structure on an electronic component and method of manufacturing the same
KR20220014492A (ko) * 2020-07-29 2022-02-07 삼성전자주식회사 팬-아웃 반도체 패키지
US11830821B2 (en) 2020-10-19 2023-11-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of manufacture
US11842935B2 (en) * 2021-02-18 2023-12-12 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a reconstructed package substrate comprising substrates blocks
US20230137998A1 (en) * 2021-11-03 2023-05-04 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing electronic devices
CN114976623B (zh) * 2022-04-15 2023-09-19 盛合晶微半导体(江阴)有限公司 一种封装结构及其封装方法
US20230421117A1 (en) * 2022-06-24 2023-12-28 Wolfspeed, Inc. Packages with backside mounted die and exposed die interconnects and methods of fabricating the same

Family Cites Families (73)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US5844315A (en) * 1996-03-26 1998-12-01 Motorola Corporation Low-profile microelectronic package
US5841193A (en) * 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US5994166A (en) * 1997-03-10 1999-11-30 Micron Technology, Inc. Method of constructing stacked packages
JP3644662B2 (ja) * 1997-10-29 2005-05-11 株式会社ルネサステクノロジ 半導体モジュール
KR100533673B1 (ko) * 1999-09-03 2005-12-05 세이코 엡슨 가부시키가이샤 반도체 장치 및 그 제조 방법, 회로 기판 및 전자 기기
JP2002040095A (ja) * 2000-07-26 2002-02-06 Nec Corp 半導体装置及びその実装方法
CN2461240Y (zh) * 2000-12-13 2001-11-21 胜开科技股份有限公司 积体电路堆叠构造
CN2475142Y (zh) * 2001-02-26 2002-01-30 胜开科技股份有限公司 堆叠半导体
US6400007B1 (en) * 2001-04-16 2002-06-04 Kingpak Technology Inc. Stacked structure of semiconductor means and method for manufacturing the same
JP4126891B2 (ja) * 2001-08-03 2008-07-30 セイコーエプソン株式会社 半導体装置の製造方法
WO2003019654A1 (en) * 2001-08-22 2003-03-06 Tessera, Inc. Stacked chip assembly with stiffening layer
CN1257540C (zh) * 2002-02-10 2006-05-24 威宇科技测试封装有限公司 一种半导体芯片封装方法及其封装结构
JP2003273317A (ja) * 2002-03-19 2003-09-26 Nec Electronics Corp 半導体装置及びその製造方法
JP2003318361A (ja) * 2002-04-19 2003-11-07 Fujitsu Ltd 半導体装置及びその製造方法
US7132311B2 (en) * 2002-07-26 2006-11-07 Intel Corporation Encapsulation of a stack of semiconductor dice
TW567601B (en) * 2002-10-18 2003-12-21 Siliconware Precision Industries Co Ltd Module device of stacked semiconductor package and method for fabricating the same
KR20050001159A (ko) * 2003-06-27 2005-01-06 삼성전자주식회사 복수개의 플립 칩들을 갖는 멀티칩 패키지 및 그 제조방법
US7345361B2 (en) * 2003-12-04 2008-03-18 Intel Corporation Stackable integrated circuit packaging
US8970049B2 (en) * 2003-12-17 2015-03-03 Chippac, Inc. Multiple chip package module having inverted package stacked over die
DE10360708B4 (de) * 2003-12-19 2008-04-10 Infineon Technologies Ag Halbleitermodul mit einem Halbleiterstapel, Umverdrahtungsplatte, und Verfahren zur Herstellung derselben
US7187068B2 (en) * 2004-08-11 2007-03-06 Intel Corporation Methods and apparatuses for providing stacked-die devices
US8294279B2 (en) * 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
US7271496B2 (en) * 2005-02-04 2007-09-18 Stats Chippac Ltd. Integrated circuit package-in-package system
US7875966B2 (en) * 2005-02-14 2011-01-25 Stats Chippac Ltd. Stacked integrated circuit and package system
JP4509052B2 (ja) * 2005-03-29 2010-07-21 三洋電機株式会社 回路装置
US7364945B2 (en) * 2005-03-31 2008-04-29 Stats Chippac Ltd. Method of mounting an integrated circuit package in an encapsulant cavity
US7429786B2 (en) * 2005-04-29 2008-09-30 Stats Chippac Ltd. Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides
SG130055A1 (en) * 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
WO2007026392A1 (ja) * 2005-08-30 2007-03-08 Spansion Llc 半導体装置およびその製造方法
JP4473807B2 (ja) * 2005-10-27 2010-06-02 パナソニック株式会社 積層半導体装置及び積層半導体装置の下層モジュール
US20070141751A1 (en) * 2005-12-16 2007-06-21 Mistry Addi B Stackable molded packages and methods of making the same
US8120156B2 (en) * 2006-02-17 2012-02-21 Stats Chippac Ltd. Integrated circuit package system with die on base package
US7288835B2 (en) * 2006-03-17 2007-10-30 Stats Chippac Ltd. Integrated circuit package-in-package system
KR100800478B1 (ko) * 2006-07-18 2008-02-04 삼성전자주식회사 적층형 반도체 패키지 및 그의 제조방법
KR100809693B1 (ko) * 2006-08-01 2008-03-06 삼성전자주식회사 하부 반도체 칩에 대한 신뢰도가 개선된 수직 적층형멀티칩 패키지 및 그 제조방법
TWI317993B (en) * 2006-08-18 2009-12-01 Advanced Semiconductor Eng Stackable semiconductor package
US7868440B2 (en) * 2006-08-25 2011-01-11 Micron Technology, Inc. Packaged microdevices and methods for manufacturing packaged microdevices
US8193034B2 (en) * 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
US8198735B2 (en) * 2006-12-31 2012-06-12 Stats Chippac Ltd. Integrated circuit package with molded cavity
TWI335070B (en) * 2007-03-23 2010-12-21 Advanced Semiconductor Eng Semiconductor package and the method of making the same
US7812435B2 (en) * 2007-08-31 2010-10-12 Stats Chippac Ltd. Integrated circuit package-in-package system with side-by-side and offset stacking
US8129832B2 (en) * 2007-10-29 2012-03-06 Stats Chippac Ltd. Mountable integrated circuit package system with substrate having a conductor-free recess
US10074553B2 (en) * 2007-12-03 2018-09-11 STATS ChipPAC Pte. Ltd. Wafer level package integration and method
US20090170241A1 (en) * 2007-12-26 2009-07-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
US8067828B2 (en) * 2008-03-11 2011-11-29 Stats Chippac Ltd. System for solder ball inner stacking module connection
US7989269B2 (en) * 2008-03-13 2011-08-02 Stats Chippac, Ltd. Semiconductor package with penetrable encapsulant joining semiconductor die and method thereof
US20100109169A1 (en) * 2008-04-29 2010-05-06 United Test And Assembly Center Ltd Semiconductor package and method of making the same
US8283209B2 (en) 2008-06-10 2012-10-09 Stats Chippac, Ltd. Semiconductor device and method of forming PiP with inner known good die interconnected with conductive bumps
TWI473553B (zh) * 2008-07-03 2015-02-11 Advanced Semiconductor Eng 晶片封裝結構
US7808113B2 (en) * 2008-07-10 2010-10-05 Texas Instruments Incorporated Flip chip semiconductor device having workpiece adhesion promoter layer for improved underfill adhesion
US7750455B2 (en) * 2008-08-08 2010-07-06 Stats Chippac Ltd. Triple tier package on package system
US8270176B2 (en) * 2008-08-08 2012-09-18 Stats Chippac Ltd. Exposed interconnect for a package on package system
US7994625B2 (en) * 2008-11-18 2011-08-09 Stats Chippac Ltd. Integrated circuit packaging system having an internal structure protrusion and method of manufacture thereof
US7838337B2 (en) * 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
TWI413232B (zh) 2008-12-02 2013-10-21 Powertech Technology Inc 多晶片封裝結構
TWI371096B (en) 2008-12-09 2012-08-21 Powertech Technology Inc Multi-chip package structure and forming method thereof
US9082806B2 (en) 2008-12-12 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US9064936B2 (en) 2008-12-12 2015-06-23 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
JP2010147153A (ja) * 2008-12-17 2010-07-01 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US8110920B2 (en) * 2009-06-05 2012-02-07 Intel Corporation In-package microelectronic apparatus, and methods of using same
US8383457B2 (en) 2010-09-03 2013-02-26 Stats Chippac, Ltd. Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
US8264091B2 (en) * 2009-09-21 2012-09-11 Stats Chippac Ltd. Integrated circuit packaging system with encapsulated via and method of manufacture thereof
TW201114008A (en) 2009-10-02 2011-04-16 Powertech Technology Inc Fabricating method of back-to-back chip assembly with flip-chip and wire-bonding connections and its structure
TW201121011A (en) 2009-12-02 2011-06-16 Powertech Technology Inc Flip chip package having metal pillars soldered in through holes and method for fabricating the same
US8115293B2 (en) * 2009-12-08 2012-02-14 Stats Chippac Ltd. Integrated circuit packaging system with interconnect and method of manufacture thereof
US8884422B2 (en) * 2009-12-31 2014-11-11 Stmicroelectronics Pte Ltd. Flip-chip fan-out wafer level package for package-on-package applications, and method of manufacture
US8357564B2 (en) 2010-05-17 2013-01-22 Stats Chippac, Ltd. Semiconductor device and method of forming prefabricated multi-die leadframe for electrical interconnect of stacked semiconductor die
KR20110133945A (ko) * 2010-06-08 2011-12-14 삼성전자주식회사 스택 패키지 및 그의 제조 방법
US8461691B2 (en) * 2011-04-29 2013-06-11 Infineon Technologies Ag Chip-packaging module for a chip and a method for forming a chip-packaging module
US8816404B2 (en) * 2011-09-16 2014-08-26 Stats Chippac, Ltd. Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulant
US8779601B2 (en) * 2011-11-02 2014-07-15 Stmicroelectronics Pte Ltd Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
US9385006B2 (en) * 2012-06-21 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming an embedded SOP fan-out package

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015149364A1 (zh) * 2014-04-04 2015-10-08 史利利 印制线路板
CN105261595A (zh) * 2014-04-22 2016-01-20 美国博通公司 用于半导体封装件的重构技术
CN110660809A (zh) * 2018-06-28 2020-01-07 西部数据技术公司 包含分支存储器裸芯模块的垂直互连的半导体装置
CN110660809B (zh) * 2018-06-28 2023-06-16 西部数据技术公司 包含分支存储器裸芯模块的垂直互连的半导体装置
CN110880457A (zh) * 2018-09-05 2020-03-13 台湾积体电路制造股份有限公司 半导体封装件及其形成方法
US11309294B2 (en) 2018-09-05 2022-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out packages and methods of forming the same
CN109887890A (zh) * 2019-01-30 2019-06-14 杭州晶通科技有限公司 一种扇出型倒置封装结构及其制备方法
CN109887890B (zh) * 2019-01-30 2024-02-06 杭州晶通科技有限公司 一种扇出型倒置封装结构及其制备方法
CN109940285A (zh) * 2019-03-22 2019-06-28 苏州福唐智能科技有限公司 一种扇出形晶圆激光隐形切割方法

Also Published As

Publication number Publication date
US9385006B2 (en) 2016-07-05
US10217702B2 (en) 2019-02-26
TWI590400B (zh) 2017-07-01
US20160276258A1 (en) 2016-09-22
US20130341784A1 (en) 2013-12-26
TW201401466A (zh) 2014-01-01
SG10201510232QA (en) 2016-01-28
CN103515252B (zh) 2018-01-30
CN103515252A (zh) 2014-01-15

Similar Documents

Publication Publication Date Title
CN203312275U (zh) 形成嵌入式sop扇出型封装的半导体器件
CN101996894B (zh) 半导体器件和围绕管芯周边形成坝材料以减小翘曲的方法
CN101996895B (zh) 半导体器件及其制造方法
CN103633020B (zh) 半导体器件以及在晶片级封装上使用uv固化的导电油墨形成rdl的方法
US9257411B2 (en) Semiconductor device and method of embedding bumps formed on semiconductor die into penetrable adhesive layer to reduce die shifting during encapsulation
CN102237281B (zh) 半导体器件及其制造方法
CN103383923B (zh) 用于应用处理器和存储器集成的薄3d扇出嵌入式晶片级封装(ewlb)
US8236617B2 (en) Semiconductor device and method of forming thermally conductive layer between semiconductor die and build-up interconnect structure
CN102194718B (zh) 半导体器件及其制造方法
CN101989558B (zh) 半导体器件及其制造方法
US9082780B2 (en) Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layer
US8183087B2 (en) Semiconductor device and method of forming a fan-out structure with integrated passive device and discrete component
CN101996893B (zh) 半导体器件及其制造方法
CN102034718B (zh) 半导体器件和在tsv转接板中形成开口腔以在wlcsmp中容纳半导体裸片的方法
CN102403239B (zh) 半导体器件及形成用于在Fo‑WLCSP中安装半导体小片的引线上键合互连的方法
CN203312276U (zh) 控制半导体封装中的翘曲的半导体器件
CN108666214A (zh) 半导体器件以及用于形成低廓形嵌入式晶圆级球栅阵列模塑激光封装的方法
CN102637608A (zh) 半导体器件和形成用于3d fo-wlcsp的垂直互连结构的方法
CN103325727A (zh) 形成扇出封装体叠层器件的半导体方法和器件
CN102194740A (zh) 半导体器件及其形成方法
CN112005369A (zh) 制造无热界面材料气密平顶his/emi屏蔽封装的系统和方法

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20131203

Address after: Singapore Singapore

Patentee after: STATS ChipPAC Pte. Ltd.

Patentee after: Stats Chippac (shanghai) Ltd.

Address before: Singapore Singapore

Patentee before: STATS ChipPAC Pte. Ltd.

CP01 Change in the name or title of a patent holder

Address after: Singapore City

Co-patentee after: Stats Chippac (shanghai) Ltd.

Patentee after: STATS ChipPAC Pte. Ltd.

Address before: Singapore City

Co-patentee before: Stats Chippac (shanghai) Ltd.

Patentee before: STATS ChipPAC Pte. Ltd.

CP01 Change in the name or title of a patent holder
TR01 Transfer of patent right

Effective date of registration: 20200114

Address after: 312000 No.500 Linjiang Road, Yuecheng District, Shaoxing City, Zhejiang Province

Co-patentee after: Stats Chippac (shanghai) Ltd.

Patentee after: Changdian integrated circuit (Shaoxing) Co.,Ltd.

Address before: Singapore City

Co-patentee before: Stats Chippac (shanghai) Ltd.

Patentee before: STATS ChipPAC Pte. Ltd.

TR01 Transfer of patent right
CX01 Expiry of patent term

Granted publication date: 20131127

CX01 Expiry of patent term