JP4509052B2 - 回路装置 - Google Patents
回路装置 Download PDFInfo
- Publication number
- JP4509052B2 JP4509052B2 JP2006075340A JP2006075340A JP4509052B2 JP 4509052 B2 JP4509052 B2 JP 4509052B2 JP 2006075340 A JP2006075340 A JP 2006075340A JP 2006075340 A JP2006075340 A JP 2006075340A JP 4509052 B2 JP4509052 B2 JP 4509052B2
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- Prior art keywords
- circuit element
- circuit
- conductive layer
- layer
- ground
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- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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Description
図1は、実施形態1に係る回路装置の構成を示す断面図である。図2は、実施形態1に係る回路装置の平面図である。
基板20の上に回路素子を積層する方法について、以下に述べる。
図6は、実施形態2に係る回路装置500の構成を示す断面図である。図7は、実施形態2に係る回路装置500の平面図である。
図8は、実施形態3に係る回路装置600の構成を示す断面図である。以下に、実施形態1と異なる構成を中心に、実施形態3に係る回路装置600について説明する。回路装置600では、パッケージ化された第2の回路素子40が用いられている。基板20に搭載された第1の回路素子30およびパッケージ化された第2の回路素子40がさらにパッケージ化されている。
図9および図10は、実施形態3の回路装置600の製造方法を示す工程断面図である。まず、図9(A)に示すように、絶縁層50の上の銅箔を選択的にエッチングすることにより、電源用の導電層610および接地用の導電層60をパターニングする。さらに、導電層610の上にボンディングパッド620,640を形成する。また、導電層60の上にボンディングパッド62,64を形成する。
図11は、実施形態4に係る回路装置700の構成を示す断面図である。回路装置700は、第1の回路素子30が予めパッケージ化されている点、第2の回路素子から絶縁層50を除去した点、および配線層を含む基板20を備えていない点で、実施形態3と相違する。以下に、実施形態3と異なる構成を中心に、実施形態4に係る回路装置700について説明する。
図12は、実施形態4の回路装置700の製造方法を示す工程断面図である。まず、図12(A)に示すように、エポキシ樹脂などの基材702の上に接地配線21および電源配線22を形成する。接地配線21に、第1の回路素子30の接地に用いられるリード750および第2の回路素子40の接地に用いられるリード27を設ける。また、電源配線22に、第1の回路素子30の電源接続に用いられるリード720および第2の回路素子40の電源接続に用いられるリード28を設ける。接地配線21の所定領域に電源用のボンディングパッド730および接地用のボンディングパッド760を有する第1の回路素子30を図示しない接着剤を介して接地配線21の所定の位置に搭載する。第1の回路素子30に設けられたボンディングパッド730と電源配線22に設けられたリード720とを電源用ワイヤ740を用いてワイヤボンディングする。また、第1の回路素子30に設けられたボンディングパッド760と接地配線21に設けられたリード750とを接地用ワイヤ770によってワイヤボンディングする。
Claims (7)
- 接地配線が設けられた基板と、
前記基板の上に積層された複数の回路素子と、
前記複数の回路素子のうち、少なくとも一組の隣接する下層回路素子と上層回路素子との間に設けられた一対の絶縁層と、
前記一対の絶縁層に狭持された導電層と、
を備え、
前記上層回路素子と、前記一対の絶縁層のうち前記上層回路素子側の絶縁層と、前記導電層とによって容量成分を有するとともに、
前記下層回路素子と、前記一対の絶縁層のうち前記下層回路素子側の絶縁層と、前記導電層とによって容量成分を有し、
さらに、前記上層回路素子が、前記導電層を経由して前記接地配線に接続されていることを特徴とする回路装置。 - 前記複数の回路素子のうち、最下層の回路素子が前記基板にフリップチップ実装されていることを特徴とする請求項1に記載の回路装置。
- 接地配線と、
前記接地配線の上に積層された複数の回路素子と、
前記積層された複数の回路素子のうち、少なくとも一組の隣接する下層回路素子と上層回路素子との間に設けられた一対の絶縁層と、
前記一対の絶縁層に狭持された導電層と、
を備え、
前記上層回路素子と、前記一対の絶縁層のうち前記上層回路素子側の絶縁層と、前記導電層とによって容量成分を有するとともに、
前記下層回路素子と、前記一対の絶縁層のうち前記下層回路素子側の絶縁層と、前記導電層とによって容量成分を有し、
さらに、前記上層回路素子が、前記導電層を経由して前記接地配線に接続されていることを特徴とする回路装置。 - 2個の回路素子が積層された回路装置であって、
上側の回路素子が、上側の回路素子と下側の回路素子との間に設けられた前記導電層を経由して前記接地配線に接続されていることを特徴とする請求項1乃至請求項3のいずれか1項に記載の回路装置。 - 3個以上の回路素子が積層された回路装置であって、
下から2層目以上の各回路素子が、それぞれの下層の回路素子との間に設けられた導電層を経由して、前記接地配線に接続されていることを特徴とする請求項1乃至請求項4のいずれか1項に記載の回路装置。 - 前記回路素子の接地に利用される前記導電層の上側の絶縁層と、前記導電層との重なり部分が前記上側の絶縁層と面する回路素子の投影部分とほぼ等しいことを特徴とする請求項1乃至請求項5のいずれか1項に記載の回路装置。
- 前記回路素子の接地に利用される前記導電層の面積が、前記導電層の上側の絶縁層より大きいことを特徴とする請求項1乃至請求項6のいずれか1項に記載の回路装置。
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JP2006075340A JP4509052B2 (ja) | 2005-03-29 | 2006-03-17 | 回路装置 |
CN2006100898937A CN1855477B (zh) | 2005-03-29 | 2006-03-29 | 电路装置 |
US11/391,680 US7453153B2 (en) | 2005-03-29 | 2006-03-29 | Circuit device |
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JP4185499B2 (ja) * | 2005-02-18 | 2008-11-26 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置 |
WO2007147137A2 (en) | 2006-06-15 | 2007-12-21 | Sitime Corporation | Stacked die package for mems resonator system |
US7872356B2 (en) | 2007-05-16 | 2011-01-18 | Qualcomm Incorporated | Die stacking system and method |
JP5404000B2 (ja) * | 2007-11-14 | 2014-01-29 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 半導体モジュールおよび撮像装置 |
KR101003568B1 (ko) | 2007-11-14 | 2010-12-22 | 산요 세미컨덕터 컴퍼니 리미티드 | 반도체 모듈 및 촬상 장치 |
US7956449B2 (en) * | 2008-06-25 | 2011-06-07 | Stats Chippac Ltd. | Stacked integrated circuit package system |
JP2010199286A (ja) * | 2009-02-25 | 2010-09-09 | Elpida Memory Inc | 半導体装置 |
KR20110133945A (ko) * | 2010-06-08 | 2011-12-14 | 삼성전자주식회사 | 스택 패키지 및 그의 제조 방법 |
US9385006B2 (en) * | 2012-06-21 | 2016-07-05 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming an embedded SOP fan-out package |
US20150201515A1 (en) * | 2014-01-13 | 2015-07-16 | Rf Micro Devices, Inc. | Surface finish for conductive features on substrates |
WO2017000110A1 (zh) * | 2015-06-29 | 2017-01-05 | 深圳市柔宇科技有限公司 | 电路板结构及电子设备 |
US9972578B2 (en) * | 2016-03-29 | 2018-05-15 | Microchip Technology Incorporated | Stacked die ground shield |
US10787303B2 (en) | 2016-05-29 | 2020-09-29 | Cellulose Material Solutions, LLC | Packaging insulation products and methods of making and using same |
US11078007B2 (en) | 2016-06-27 | 2021-08-03 | Cellulose Material Solutions, LLC | Thermoplastic packaging insulation products and methods of making and using same |
CN107871732A (zh) * | 2016-09-23 | 2018-04-03 | 深圳市中兴微电子技术有限公司 | 封装结构 |
US10923444B1 (en) * | 2017-05-26 | 2021-02-16 | Mitsubishi Electric Corporation | Semiconductor device |
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WO2022249600A1 (ja) * | 2021-05-26 | 2022-12-01 | 株式会社村田製作所 | 電子回路モジュール |
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JP3481444B2 (ja) | 1998-01-14 | 2003-12-22 | シャープ株式会社 | 半導体装置及びその製造方法 |
US6472741B1 (en) * | 2001-07-14 | 2002-10-29 | Siliconware Precision Industries Co., Ltd. | Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same |
US6737750B1 (en) * | 2001-12-07 | 2004-05-18 | Amkor Technology, Inc. | Structures for improving heat dissipation in stacked semiconductor packages |
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US7205651B2 (en) * | 2004-04-16 | 2007-04-17 | St Assembly Test Services Ltd. | Thermally enhanced stacked die package and fabrication method |
US7245003B2 (en) * | 2004-06-30 | 2007-07-17 | Intel Corporation | Stacked package electronic device |
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US20060238961A1 (en) | 2006-10-26 |
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