CN2475142Y - 堆叠半导体 - Google Patents

堆叠半导体 Download PDF

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CN2475142Y
CN2475142Y CN01204313U CN01204313U CN2475142Y CN 2475142 Y CN2475142 Y CN 2475142Y CN 01204313 U CN01204313 U CN 01204313U CN 01204313 U CN01204313 U CN 01204313U CN 2475142 Y CN2475142 Y CN 2475142Y
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semiconductor wafer
substrate
lower floor
semiconductor
upper strata
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蔡孟儒
彭镇滨
叶乃华
吴志成
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Kingpak Technology Inc
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

一种堆叠半导体。为提供一种电传递性能好、制造方便、生产成本低、生产效率高的半导体元件,提出本实用新型,它包括形成讯号输入、出端的基板、设有上、下表面的下层半导体晶片、黏著层、复数条导线及上层半导体晶片;黏著层敷设于下层半导体晶片下表面与基板之间,并溢延形成设于下层半导体周边及上表面溢胶;复数条导线两端分别电连接于位于下层半导体晶片及基板的讯号输入端;上层半导体晶片堆叠于下层半导体晶片上方。

Description

堆叠半导体
本实用新型属于半导体元件，特别是一种堆叠半导体。
如图1所示，习知的堆叠半导体包括有基板10、下层半导体晶片12、上层半导体晶片14、复数条导线16及隔离层18。下层半导体晶片12系设于基板10上，上层半导体晶片14系藉由隔离层18叠合于下层半导体晶片12上方，使下层半导体晶片12与上层半导体晶片14形成适当之间距20，如此，复数条导线16即可电连接于下层半导体晶片12边缘，上层半导体晶片14叠合于下层半导体晶片12上时，不致于压损复数条导线16。
然而，此种结构在制造上必须先制作隔离层18；再将其黏著于下层半导体晶片12上；而后再将上层半导体晶片14黏著于隔离层18上，故其制造程序较为复杂，生产成本较高。
再者，若下层半导体晶片12的焊垫形成于中央部位时，则并无法以上述的方法实施堆叠。
如图2所示，当焊垫22形成于下层半导体晶片23中央部位的堆叠时，上层半导体晶片24将会压到导线25，使导线25接触到下层半导体晶片24边缘，以致造成电讯的传递不佳或短路的现象。
本实用新型的目的是提供一种电传递性能好、制造方便、生产成本低、生产效率高的堆叠半导体。
本实用新型包括基板、下层半导体晶片、黏著层、复数条导线及上层半导体晶片；基板具有分别形成讯号输入、输出端的第一、二表面；下层半导体晶片设有下表面及中央部位形成复数焊垫的上表面；黏著层敷设于下层半导体晶片下表面与基板第一表面之间，并溢延形成设于下层半导体周边及上表面溢胶；复数条导线两端分别电连接于位于下层半导体晶片中央部位的焊垫及基板第一表面的讯号输入端；上层半导体晶片堆叠于下层半导体晶片上方，且与基板第一表面讯号输入端电连接。
其中：
基板第二表面的讯号输出端为电连接于电路板上的球栅阵列金属球(BGA)。
基板上于下层半导体晶片周边形成阻隔溢胶往基板四周扩散而往上堆积覆盖于下层半导体晶片上表面四周边的阻隔层。
阻隔层系为覆设于基板第一表面的绿漆。
上层半导体晶片与基板第一表面的讯号输入端之间电连接有复数导线。
基板、下层半导体晶片及上层半导体晶片上方覆设有保护复数条导线的封胶层。
由于本实用新型包括形成讯号输入、出端的基板、设有上、下表面的下层半导体晶片、黏著层、复数条导线及上层半导体晶片；黏著层敷设于下层半导体晶片下表面与基板之间，并溢延形成设于下层半导体周边及上表面溢胶；复数条导线两端分别电连接于位于下层半导体晶片及基板的讯号输入端；上层半导体晶片堆叠于下层半导体晶片上方，且与基板第一表面讯号输入端电连接。当上层半导体晶片叠合于下层半导体晶片上时，藉由溢胶使电连于下层半导体晶片的复数条导线与下层半导体晶片隔离，使上层半导体晶片虽压著复数条导线，亦不致使复数条导线与下层半导体晶片形成电接触而产生短路或压损的现象；及不致因上层半导体晶片的压著而与下层半导体晶片形成电接触而影响到讯号的传递，不仅电传递性能好，而且制造方便、生产成本低、生产效率高，从而达到本实用新型的目的。
图1、为习知的堆叠半导体结构示意剖视图。
图2、为习知的堆叠半导体结构示意剖视图(焊垫位于下层半导体晶片中央部位)。
图3、为本实用新型结构示意剖视图(未堆叠上层半导体晶片时)。
图4、为本实用新型结构示意剖视图。
图5、为本实用新型结构示意俯视图。
下面结合附图对本实用新型进一步详细阐述。
如图3、图4、图5所示，本实用新型包括基板26、下层半导体晶片28、黏著层30、复数条导线32及上层半导体晶片34。
基板26具有第一表面36及第二表面38，第一表面36形成有讯号输入端40，第二表面38形成有讯号输出端42，讯号输出端42为球栅阵列金属球(ballgrid array)，用以电连接于电路板上。
下层半导体晶片28设有下表面44及上表面46，下表面44系设置于基板26的第一表面36上，其上表面46中央部位形成有若干个焊垫48，用以电连接于基板26的讯号输入端40。
黏著层30系设置于下层半导体晶片28的下表面44与基板26的第一表面36间，用以将下层半导体晶片28黏著固定于基板26。黏著层30加热液化使下层半导体晶片28黏著于基板26上时，位于下层半导体晶片28的下表面44的黏著层30将溢出下层半导体晶片28的下表面44，并令黏著层30的溢胶50延着下层半导体晶片28周边延伸至下层半导体晶片28的上表面46，以将下层半导体晶片28周边包覆住。基板26上于下层半导体晶片28周边形成有阻隔层52，用以阻隔溢胶50往基板26四周扩散，使溢胶50往上堆积覆盖于下层半导体晶片28的上表面46四周边。阻隔层52系以绿漆覆设于基板26上，在制造上更为便利。
如图4所示，将下层半导体晶片28固著于基板26后，将复数条导线32一端电连接于位于下层半导体晶片28中央部位的焊垫48，另一端电连接于基板26的讯号输入端40，使下层半导体晶片28的讯号传递至基板26上。此时，复数条导线32系位于下层半导体晶片28的上表面46的溢胶50上方，而后，将上层半导体晶片34藉由黏胶54黏著堆叠于下层半导体晶片28上方。此时，上层半导体晶片34虽压设于复数条导线32上，但复数条导线32与下层半导体晶片28间有溢胶50的隔绝，使复数条导线32与下层半导体晶片28不会导致电性的接触而产生短路的现象。而后，上层半导体晶片34藉由复数条导线56电连接于基板26的讯号输入端40，使上层半导体晶片34的讯号传递至基板26上，以完成上、下半导体晶片34、28的堆叠。
以封胶层58覆盖于基板26、下层半导体晶片28及上层半导体晶片34上方，用以保护复数条导线32、56，如是，即完成半导体晶片的堆叠封装。
本实用新型具有如下的优点：
1、当上层半导体晶片34叠合于下层半导体晶片28上时，藉由溢胶50使电连于下层半导体晶片28的复数条导线32与下层半导体晶片28隔离，使上层半导体晶片34虽压著复数条导线32，亦不致使复数条导线32与下层半导体晶片28形成电接触，而产生短路或压损的现象。
2、当下层半导体晶片28黏著于基板26时，藉由黏胶层30的溢胶50包覆住下层半体晶片28的上表面36，使复数条导线32不致因上层半导体晶片34的压著而与下层半导体晶片28形成电接触，以影响到讯号的传递，其在堆叠的制造上相当便利，可降低半导体晶片在堆叠时解决电性传递不良所产生制造成本。

Claims (6)

1、一种堆叠半导体，它包括基板、下层半导体晶片、复数条导线及上层半导体晶片；基板具有分别形成讯号输入、输出端的第一、二表面；下层半导体晶片设有下表面及中央部位形成复数焊垫的上表面；复数条导线两端分别电连接于位于下层半导体晶片中央部位的焊垫及基板第一表面的讯号输入端；上层半导体晶片堆叠于下层半导体晶片上方，且与基板第一表面讯号输入端电连接；其特征在于所述的下层半导体晶片下表面与基板第一表面之间设有将其黏著于基板第一表面的黏著层，其周边及上表面设有由黏著层溢延的溢胶。
2、根据权利要求1所述的堆叠半导体，其特征在于所述的基板第二表面的讯号输出端为电连接于电路板上的球栅阵列金属球(BGA)。
3、根据权利要求1所述的堆叠半导体，其特征在于所述的基板上于下层半导体晶片周边形成阻隔溢胶往基板四周扩散而往上堆积覆盖于下层半导体晶片上表面四周边的阻隔层。
4、根据权利要求3所述的堆叠半导体，其特征在于所述的阻隔层系为覆设于基板第一表面的绿漆。
5、根据权利要求1所述的堆叠半导体，其特征在于所述的上层半导体晶片与基板第一表面的讯号输入端之间电连接有复数导线。
6、根据权利要求1所述的堆叠半导体，其特征在于所述的基板、下层半导体晶片及上层半导体晶片上方覆设有保护复数条导线的封胶层。
CN01204313U 2001-02-26 2001-02-26 堆叠半导体 Expired - Lifetime CN2475142Y (zh)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100390990C (zh) * 2002-02-28 2008-05-28 自由度半导体公司 堆叠多芯片封装和制造堆叠多芯片封装的方法
CN102215401A (zh) * 2010-04-01 2011-10-12 美国博通公司 一种用于视频处理的方法和系统
CN103515257A (zh) * 2012-06-18 2014-01-15 智瑞达科技（苏州）有限公司 高密度半导体封装结构的封装方法
CN103515252A (zh) * 2012-06-21 2014-01-15 新科金朋有限公司 形成嵌入式sop扇出型封装的半导体器件和方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100390990C (zh) * 2002-02-28 2008-05-28 自由度半导体公司 堆叠多芯片封装和制造堆叠多芯片封装的方法
CN102215401A (zh) * 2010-04-01 2011-10-12 美国博通公司 一种用于视频处理的方法和系统
CN103515257A (zh) * 2012-06-18 2014-01-15 智瑞达科技（苏州）有限公司 高密度半导体封装结构的封装方法
CN103515252A (zh) * 2012-06-21 2014-01-15 新科金朋有限公司 形成嵌入式sop扇出型封装的半导体器件和方法
US10217702B2 (en) 2012-06-21 2019-02-26 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming an embedded SoP fan-out package

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