CN2528113Y - 多晶片封装组件 - Google Patents

多晶片封装组件 Download PDF

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CN2528113Y
CN2528113Y CN02201673U CN02201673U CN2528113Y CN 2528113 Y CN2528113 Y CN 2528113Y CN 02201673 U CN02201673 U CN 02201673U CN 02201673 U CN02201673 U CN 02201673U CN 2528113 Y CN2528113 Y CN 2528113Y
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substrate
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辛宗宪
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Kingpak Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06156—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

一种多晶片封装组件。为提供一种可将多数个晶片封装于一体、提高封装体的容量、降低堆叠厚度、达到轻薄短小、适用于焊垫设于中央位置半导体晶片的半导体元件，提出本实用新型，它包括基板、复数晶片及复数条导线；基板设有上、下表面；上表面形成有复数个第一连接点，下表面设有复数个第二连接点；复数晶片设置于基板上、下表面上；复数条导线分别连接于复数晶片与基板第一、二连接点；下表面设有凸缘层；凸缘层于下表面形成设置晶片的容置室，其上设有复数个分别与基板的第一、二连接点电连接的讯号输出点。

Description

多晶片封装组件
技术领域
本实用新型属于半导体元件，特别是一种多晶片封装组件。
背景技术
如图1所示，习知的半导体晶片堆叠组件包括有基板10、下层半导体晶片12、上层半导体晶片13及阻隔物14。
基板10设有上表面16及下表面18，上表面16形成有复数个第一连接点20，下表面18形成有复数个第二连接点22，复数个金属球24系电连接第二连接点22。
下层半导体晶片12系设置于基板10的上表面16，藉由复数条导线26电连接至基板10的第一连接点20。
阻隔物14系以粘胶层15设置于下层半导体晶片12上，上层半导体晶片13亦以粘胶层15设置于阻隔物14上。如此，复数条导线26不致被上层半导体晶片13压损。
此种半导体晶片堆叠组件，在制造上必须另行制作阻隔物14，再将阻隔物14先行涂上粘胶层15设于下层半导体晶片12，最后将上层半导体晶片13粘于阻隔物14上，因此，在制程上较为复杂，且整个封装体积较厚，无法达到轻薄短小的需求；另下层半导体晶片12及上层半导体晶片13电连接至基板10距离长，使得讯号传递效果较差。
如图2所示，习知的另一种半导体晶片堆叠组件包括基板30、下层半导体晶片32及上层半导体晶片34。
基板30设有上表面36及下表面38，上表面36形成有复数个第一连接点40，下表面38形成有复数个第二连接点42，复数个金属球44系电连接第二连接点42。
下层半导体晶片32系设置于基板30的上表面36，藉由复数条导线46电连接至基板30的第一连接点40；黏胶层48系涂布于下层半导体晶片32上，用以将复数条导线46包覆住，而上层半导体晶片34系藉由黏胶层48黏着固定于下层半导体晶片32上，以形成半导体晶片的堆叠，如此，复数条导线26不致被上层半导体晶片34压损。
惟，此种半导体晶片堆叠组件必须涂布较厚的黏胶层48，使得整个封装体积较厚，无法达到轻薄短小的需求；另，下层半导体晶片32及上层半导体晶片34电连接至基板30距离长，使得讯号传递效果较差。
再者，上述两种习知的半导体晶片堆叠组件，只能适用于半导体晶片的焊垫设于周边者，若是半导体晶片的焊垫设于中央位置者则无法适用。
发明内容
本实用新型的目的是提供一种可将多数个晶片封装于一体、提高封装体的容量、降低堆叠厚度、达到轻薄短小、适用于焊垫设于中央位置半导体晶片的多晶片封装组件。
本实用新型包括基板、复数晶片及复数条导线；基板设有上、下表面；上表面形成有复数个第一连接点，下表面设有复数个第二连接点；复数晶片设置于基板上、下表面上；复数条导线分别连接于复数晶片与基板第一、二连接点；下表面设有凸缘层；凸缘层于下表面形成设置晶片的容置室，其上设有复数个分别与基板的第一、二连接点电连接的讯号输出点。
其中：
凸缘层上设有使基板的第一、二连接点电连接至讯号输出点的穿孔。
复数个晶片设有将其包覆藉以保护晶片及复数条导线的的封胶体。
基板上表面设有一晶片；下表面容置室内设有一晶片。
基板上表面设并排的第一、二晶片；下表面容置室内设有一晶片。
凸缘层上的复数讯号输出点连接复数个金属球。
复数个金属球为球栅阵列金属球。
由于本实用新型包括基板、复数晶片及复数条导线；基板设有上、下表面；上表面形成有复数个第一连接点，下表面设有复数个第二连接点；复数晶片设置于基板上、下表面上；复数条导线分别连接于复数晶片与基板第一、二连接点；下表面设有凸缘层；凸缘层于下表面形成设置晶片的容置室，其上设有复数个分别与基板的第一、二连接点电连接的讯号输出点。将复数晶片分别设置于基板的上、下表面，便可将焊垫设于中央位置的复数晶片封装于同一封装体内，如此可提升封装体的容量，且在制程上较堆叠方式更为简易，可降低生产成本者，同时解决焊垫设于中央位置的两晶片无法堆叠封装的问题；不仅可将多数个晶片封装于一体、提高封装体的容量、降低堆叠厚度、达到轻薄短小，而且适用于焊垫设于中央位置半导体晶片，从而达到本实用新型的目的。
附图说明
图1、为习知的半导体晶片堆叠组件结构示意剖视图。
图2、为另一种习知的半导体晶片堆叠组件结构示意剖视图。
图3、为本实用新型实施例一结构示意剖视图。
图4、为本实用新型实施例二结构示意剖视图。
具体实施方式
实施例一
如图3所示，本实用新型包括基板50、第一晶片52、第二晶片54、复数条导线56、凸缘层58、封胶体59及复数个金属球78。
基板50设有上表面60及下表面62，上表面60形成有复数个第一连接点64，下表面62设有复数个第二连接点66。
第一晶片52中央位置形成有复数个焊垫68，其系设置于基板50的上表面60上，藉由复数条导线56电连接焊垫68至基板50的第一连接点64，使第一晶片52的讯号传递至基板50上。
凸缘层58系形成于基板50的下表面62上，使下表面62形成容置室70；凸缘层58上设有复数个讯号输出点72及穿孔74，于穿孔74内设有导线76，使基板50的第一、二连接点64、66电连接至讯号输出点72。
第二晶片54系设于基板50的下表面62的容置室70内，藉由复数条导线56电连接至基板50的第二连接点66。
封胶体59系用以将第一、二晶片52、54包覆，藉以保护住第一、二晶片52、54及复数条导线56。复数个金属球78为球栅阵列金属球(ball grid array)设置于该基板的下表面的凸缘层58上，并与讯号输出点72形成电连接。
如此，将第一、二晶片52、54分别设置于基板10的上表面60及下表面62，便可将焊垫设于中央位置的第一、二晶片封装于同一封装体内，如此可提升封装体的容量，且在制程上较堆叠方式更为简易，可降低生产成本者，同时解决焊垫设于中央位置的两晶片无法堆叠封装的问题。
实施例二
如图4所示，本实用新型包括有基板50、第一晶片52、第二晶片54、第三晶片61、复数条导线56、凸缘层58、封胶体59及复数个金属球78。
基板50设有上表面60及下表面62，上表面60形成有复数个第一连接点64，下表面62设有复数个第二连接点66。
第一晶片52的周边位置形成有复数个焊垫68，其系设置于基板50的上表面60上，藉由复数条导线56电连接焊垫68至基板50的第一连接点64，使第一晶片52的讯号传递至基板50上。
第三晶片61亦设置于基板50的上表面60上与第一晶片52并排设置，并藉由复数条导线56电连接至基板50的第一连接点64。
凸缘层58系形成于基板50的下表面62上，使下表面62形成有容置室70，凸缘层58上设有复数个讯号输出点72及穿孔74，于穿孔74内形成有导线76，使基板50的第一、二连接点64、66电连接至讯号输出点72。
第二晶片54系设于基板50的下表面62的容置室70内，藉由复数条导线56电连接至基板50的第二连接点66。
封胶体59系用以将第一、二、三晶片52、54、61包覆住，藉以保护住第一、二、三晶片52、54、61及复数条导线56。
复数个金属球78为球栅阵列金属球(ball grid array)设置于基板的下表面的凸缘层58上，并与讯号输出点72形成电连接。
如此，将第一、二、三晶片52、54、61分别设置于基板10的上表面60及下表面62，便可将三个晶片封装于同一封装体内，如此可提升封装体的容量，且在制程上较堆叠方式更为简易，可降低生产成本。
如上所述，本实用新型具有如下的优点：
1、可将多数个晶片封装于一封装体内，提升封装体的容量及制造较为便利。
2、降低堆叠厚度，以达到轻薄短小的封装体积。
3、可适用于焊垫设于中央位置的半导体晶片多晶片封装。

Claims (7)

1、一种多晶片封装组件，它包括基板、复数晶片及复数条导线；基板设有上、下表面；上表面形成有复数个第一连接点，下表面设有复数个第二连接点；复数晶片设置于基板上、下表面上；复数条导线分别连接于复数晶片与基板第一、二连接点；其特征在于所述的下表面设有凸缘层；凸缘层于下表面形成设置晶片的容置室，其上设有复数个分别与基板的第一、二连接点电连接的讯号输出点。
2、根据权利要求1所述的多晶片封装组件，其特征在于所述的凸缘层上设有使基板的第一、二连接点电连接至讯号输出点的穿孔。
3、根据权利要求1所述的多晶片封装组件，其特征在于所述的复数个晶片设有将其包覆藉以保护晶片及复数条导线的的封胶体。
4、根据权利要求1所述的多晶片封装组件，其特征在于所述的基板上表面设有一晶片；下表面容置室内设有一晶片。
5、根据权利要求1所述的多晶片封装组件，其特征在于所述的基板上表面设并排的第一、二晶片；下表面容置室内设有一晶片。
6、根据权利要求1所述的多晶片封装组件，其特征在于所述的凸缘层上的复数讯号输出点连接复数个金属球。
7、根据权利要求6所述的多晶片封装组件，其特征在于所述的复数个金属球为球栅阵列金属球。
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Cited By (4)

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CN102456677A (zh) * 2010-10-27 2012-05-16 三星半导体(中国)研究开发有限公司 球栅阵列封装结构及其制造方法
CN103579206A (zh) * 2013-11-07 2014-02-12 华进半导体封装先导技术研发中心有限公司 堆叠封装器件及其制造方法
CN106328620A (zh) * 2016-08-26 2017-01-11 苏州日月新半导体有限公司 集成电路封装体及其制造方法
CN109935577A (zh) * 2017-12-18 2019-06-25 无锡华润安盛科技有限公司 一种封装体

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102456677A (zh) * 2010-10-27 2012-05-16 三星半导体(中国)研究开发有限公司 球栅阵列封装结构及其制造方法
CN102456677B (zh) * 2010-10-27 2013-08-21 三星半导体(中国)研究开发有限公司 球栅阵列封装结构及其制造方法
CN103579206A (zh) * 2013-11-07 2014-02-12 华进半导体封装先导技术研发中心有限公司 堆叠封装器件及其制造方法
CN103579206B (zh) * 2013-11-07 2016-09-21 华进半导体封装先导技术研发中心有限公司 堆叠封装器件及其制造方法
CN106328620A (zh) * 2016-08-26 2017-01-11 苏州日月新半导体有限公司 集成电路封装体及其制造方法
CN109935577A (zh) * 2017-12-18 2019-06-25 无锡华润安盛科技有限公司 一种封装体

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