CN2543206Y - 内存芯片堆栈构造 - Google Patents

内存芯片堆栈构造 Download PDF

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CN2543206Y
CN2543206Y CN02207983U CN02207983U CN2543206Y CN 2543206 Y CN2543206 Y CN 2543206Y CN 02207983 U CN02207983 U CN 02207983U CN 02207983 U CN02207983 U CN 02207983U CN 2543206 Y CN2543206 Y CN 2543206Y
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memory chip
substrate
internal storage
storage chip
dielectric
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叶乃华
彭镇滨
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Kingpak Technology Inc
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    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract

本实用新型内存芯片堆栈构造，包括有一基板，其上设有一镂空槽；一下层内存芯片，其中央位置设有复数个焊垫，是设置于该基板上，而该复数个焊垫由该基板的镂空槽露出，并藉由复数条导线电连接该焊垫至基板的下表面；一上层内存芯片，其中央位置设有复数个焊垫，其系背对背地设置于该下层内存芯片上，使该复数个焊垫朝上；及一绝缘介质，其形成一透空区，其设置于该上层内存芯片上时，该内存芯片的复数个焊垫由该绝缘介质的透空区露出，且该绝缘介质上形成有复数条线路，并藉由复数条导线电连接至该上层内存芯片的焊垫及该基板的上表面。如是，可降低该复数条导线的长度及弧度，使其得到较佳的讯号传递效果及降低其封装体积。

Description

内存芯片堆栈构造
技术领域
本实用新型属于电子器件领域，特别涉及一种内存芯片。具体是指一种具有高记忆容量及讯号传递速度快的内存芯片堆栈构造。
技术背景
为了提升单一体积封装体的内存容量，通常将二个或以上的内存芯片予以堆栈封装，使单一面积可容纳较大记忆容量的内存。
如图1所示，为习知的一种内存芯片堆栈构造，它包括有一基板10、一下层内存芯片12及一上层内存芯片14：基板10中央部位形成有一镂空槽16；下层内存芯片12系设置于基板10上，其上复数个焊垫18由镂空槽16露出，藉由复数条导线20电连接至基板10上，使下层内存芯片12的讯号传递至基板10；上层内存芯片14系背对背地设置于下层内存芯片12上，其中央部位的焊垫22藉由复数条导线24电连接至基板10，使讯号传递至基板10。
如上所述的内存芯片堆栈构造，由于内存芯片的焊垫形成于中央位置，因此，上层内存芯片14藉由复数条导线24电连接至基板10上时，将造成导线24的弧度较大，如是，导线24的长度较长，将使讯号传递不易，且将使封装完成的体积较大，无法达到轻薄短小的需求，再者，由于导线24的长度较长，将使导线24易于下垂而接触到上层内存芯片14的表面，而容易产生电讯号传递不良或短路的情形。
有鉴于此，本发明人本着精益求精，创新突破的精神，研发出本实用新型内存芯片堆栈构造，它可改进上述习知内存芯片堆栈的缺失，使其更为实用。
发明内容
本实用新型的主要目的，在于提供一种内存芯片堆栈构造，它具有缩短讯号传递距离的功效，以达到提高讯号传递效果的目的。
本实用新型的另一目的，在于提供一种内存芯片堆栈构造，它具有提高堆栈品质的的功效，以达到提高生产良率的目的。
本实用新型的再一目的，在于提供一种内存芯片堆栈构造，它具有便于制造的功效，以达到更为实用的目的。
本实用新型的又一目的，在于提供一种内存芯片堆栈构造，它具有缩小封装体积的功效，以达到轻薄短小的目的。
上述的目的是这样实现的：
一种内存芯片堆栈构造，其特征在于包括有：
一基板，其设有一上表面、一下表面及由上表面贯通至下表面的镂空槽；
一下层内存芯片，其中央位置设有复数个焊垫，其系设置于该基板的上表面，而该复数个焊垫由该基板的镂空槽露出，并藉由复数条导线电连接该焊垫至基板的下表面；
一上层内存芯片，其中央位置设有复数个焊垫，其系背对背地设置于该下层内存芯片上，使该复数个焊垫朝上；及一绝缘介质，其中央位置形成一透空区，使其设置于该上层内存芯片上时，该内存芯片的复数个焊垫由该绝缘介质的透空区露出，且该绝缘介质上形成有复数条线路，该复数条线路藉由复数条导线电连接至该上层内存芯片的焊垫及该基板的上表面。
该基板的镂空槽填充有一第一封胶体，用以保护该复数条导线。
该基板的上表面覆盖有一第二封胶体，用以保护上、下层内存芯片及该绝缘介质。
该绝缘介质为软性电路板，其上布植有复数条线路。
该基板的下表面形成有球栅数组金属球。
本实用新型的积极效果是：
由于本实用新型包括有：一基板，其设有一上表面、一下表面及由上表面贯通至下表面的镂空槽；一下层内存芯片，其中央位置设有复数个焊垫，其系设置于该基板的上表面，而该复数个焊垫由该基板的镂空槽露出，并藉由复数条导线电连接该焊垫至基板的下表面；一上层内存芯片，其中央位置设有复数个焊垫，其系背对背地设置于该下层内存芯片上，使该复数个焊垫朝上；及一绝缘介质，其中央位置形成一透空区，其设置于该上层内存芯片上时，该内存芯片的复数个焊垫由该绝缘介质的透空区露出，且该绝缘介质上形成有复数条线路，并藉由复数条导线电连接至该上层内存芯片的焊垫及该基板的上表面。
藉由如上的构造组合，可降低该复数条导线的长度及弧度，使其更便于制造及得到较佳的讯号传递效果及降低其封装体积。具体的优点表现在：
1、绝缘介质的线路可布植较宽大的直径，而可提高讯号传递的效率及品质。
2、电连接上层内存芯片及基板的导线所形成的弧度较小，相对地可缩短讯号传递的距离，及减少整体封装的体积，以达到轻薄短小的需求。
附图说明
图1习知的一种内存芯片堆栈构造示意图；
图2本实用新型实施例的绝缘介质构造示意图；
图3本实用新型实施例封装前的基本结构示意图；
图4本实用新型实施例封装后整体结构示意图。
具体实施方式
本实用新型的上述及其它目的、优点和特色由以下较佳实施例的详细说明并参考附图得以更深入了解。
配合参阅图2、图3及图4，本实施例中该内存芯片堆栈构造包括有一基板30、一下层内存芯片32、一上层内存芯片34及一绝缘介质36：
基板30设有一上表面38、一下表面40及一由上表面38贯通至下表面40的镂空槽42，基板30的上表面30形成有复数个第一接点44，下表面40位于镂空槽42周边形成有第二接点46及复数个球栅(Ball Grid Array)数组金属球48。
下层内存芯片32中央部位形成有复数个焊垫50，其设于基板30的上表面38上，复数个焊垫50则由基板30的镂空槽42露出，藉由复数条导线52透过镂空槽42电连接焊垫50至基板30的第二连接点46。
上层内存芯片34中央部位形成有复数个焊垫54，其系背对背地设置于下层内存芯片32上，使复数个焊垫54分别朝上。
绝缘介质36于本实施例中为一软性电路板，其中央部位设有一透空区56，且其上布植有复数条线路58，该复数条线路58两端设有焊垫57、59，该绝缘介质36系设置于上层内存芯片34上，上层内存芯片34上的复数个焊垫54则由透空区56露出。
参阅图4，将绝缘介质36设置于上层内存芯片34后，藉由复数条导线60经由透空区56电连接上层内存芯片34的焊垫54及绝缘介质36的线路一端的焊垫59，及藉由复数条导线62电连接基板30的第一连接点44及绝缘介质36的线路另一端的焊垫57，如是，上层内存芯片34即可与基板30相互导通。而后，将第一封胶体64填充于基板30的镂空槽42，用以保护复数条导线52，及将第二封胶体66覆盖于基板30的上表面38，用以保护上、下层半导体芯片34、32及绝缘介质36。
在较佳实施例的详细说明中所提出的具体实施例仅为了易于说明本实用新型的技术内容，并非将本实用新型狭义地限制于实施例，凡依本实用新型的精神及其技术特征所作种种变化实施均属本实用新型的范围。

Claims (5)

1、一种内存芯片堆栈构造，其特征在于包括有：
一基板，其设有一上表面、一下表面及由上表面贯通至下表面的镂空槽；
一下层内存芯片，其中央位置设有复数个焊垫，其系设置于该基板的上表面，而该复数个焊垫由该基板的镂空槽露出，并藉由复数条导线电连接该焊垫至基板的下表面；
一上层内存芯片，其中央位置设有复数个焊垫，其系背对背地设置于该下层内存芯片上，使该复数个焊垫朝上；及
一绝缘介质，其中央位置形成一透空区，使其设置于该上层内存芯片上时，该内存芯片的复数个焊垫由该绝缘介质的透空区露出，且该绝缘介质上形成有复数条线路，该复数条线路藉由复数条导线电连接至该上层内存芯片的焊垫及该基板的上表面。
2、如权利要求1所述内存芯片堆栈构造，其特征在于，该基板的镂空槽填充有一第一封胶体，用以保护该复数条导线。
3、如权利要求1所述内存芯片堆栈构造，其特征在于，该基板的上表面覆盖有一第二封胶体，用以保护上、下层内存芯片及该绝缘介质。
4、如权利要求1所述内存芯片堆栈构造，其特征在于，该绝缘介质为软性电路板，其上布植有复数条线路。
5、如权利要求1所述内存芯片堆栈构造，其特征在于，该基板的下表面形成有球栅数组金属球。
CN02207983U 2002-03-26 2002-03-26 内存芯片堆栈构造 Expired - Lifetime CN2543206Y (zh)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101577267B (zh) * 2008-05-07 2011-05-04 南茂科技股份有限公司 芯片封装结构
CN101853845B (zh) * 2009-04-03 2012-02-22 南茂科技股份有限公司 多芯片堆叠封装
CN110058657A (zh) * 2019-04-09 2019-07-26 南昌嘉研科技有限公司 一种台式计算机内存条及插槽的防护结构及加工方法
WO2024031848A1 (zh) * 2022-08-08 2024-02-15 长鑫存储技术有限公司 三维堆叠封装结构及其形成方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101577267B (zh) * 2008-05-07 2011-05-04 南茂科技股份有限公司 芯片封装结构
CN101853845B (zh) * 2009-04-03 2012-02-22 南茂科技股份有限公司 多芯片堆叠封装
CN110058657A (zh) * 2019-04-09 2019-07-26 南昌嘉研科技有限公司 一种台式计算机内存条及插槽的防护结构及加工方法
CN110058657B (zh) * 2019-04-09 2024-03-08 南昌嘉研科技有限公司 一种台式计算机内存条及插槽的防护结构及加工方法
WO2024031848A1 (zh) * 2022-08-08 2024-02-15 长鑫存储技术有限公司 三维堆叠封装结构及其形成方法

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