CN101506975B - 堆叠管芯封装 - Google Patents
堆叠管芯封装 Download PDFInfo
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- CN101506975B CN101506975B CN2007800304876A CN200780030487A CN101506975B CN 101506975 B CN101506975 B CN 101506975B CN 2007800304876 A CN2007800304876 A CN 2007800304876A CN 200780030487 A CN200780030487 A CN 200780030487A CN 101506975 B CN101506975 B CN 101506975B
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- lead
- integrated circuit
- wire bonding
- electric contacts
- bonding integrated
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
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- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims (6)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US81377806P | 2006-06-15 | 2006-06-15 | |
US60/813,778 | 2006-06-15 | ||
US11/801,317 | 2007-05-09 | ||
US11/801,317 US7535110B2 (en) | 2006-06-15 | 2007-05-09 | Stack die packages |
PCT/US2007/013821 WO2007146307A2 (en) | 2006-06-15 | 2007-06-13 | Stack die packages |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101506975A CN101506975A (zh) | 2009-08-12 |
CN101506975B true CN101506975B (zh) | 2011-04-06 |
Family
ID=38666964
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2007800304876A Active CN101506975B (zh) | 2006-06-15 | 2007-06-13 | 堆叠管芯封装 |
Country Status (6)
Country | Link |
---|---|
US (2) | US7535110B2 (zh) |
EP (1) | EP2033220B1 (zh) |
JP (1) | JP5320611B2 (zh) |
CN (1) | CN101506975B (zh) |
TW (1) | TWI429050B (zh) |
WO (1) | WO2007146307A2 (zh) |
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JP5388422B2 (ja) * | 2007-05-11 | 2014-01-15 | スパンション エルエルシー | 半導体装置及びその製造方法 |
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US8093722B2 (en) * | 2008-05-27 | 2012-01-10 | Mediatek Inc. | System-in-package with fan-out WLCSP |
US8310051B2 (en) | 2008-05-27 | 2012-11-13 | Mediatek Inc. | Package-on-package with fan-out WLCSP |
US8896126B2 (en) | 2011-08-23 | 2014-11-25 | Marvell World Trade Ltd. | Packaging DRAM and SOC in an IC package |
US8253231B2 (en) * | 2008-09-23 | 2012-08-28 | Marvell International Ltd. | Stacked integrated circuit package using a window substrate |
US9009393B1 (en) | 2008-09-23 | 2015-04-14 | Marvell International Ltd. | Hybrid solid-state disk (SSD)/hard disk drive (HDD) architectures |
US20100213588A1 (en) * | 2009-02-20 | 2010-08-26 | Tung-Hsien Hsieh | Wire bond chip package |
US8236607B2 (en) * | 2009-06-19 | 2012-08-07 | Stats Chippac Ltd. | Integrated circuit packaging system with stacked integrated circuit and method of manufacture thereof |
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TWI501380B (zh) * | 2010-01-29 | 2015-09-21 | Nat Chip Implementation Ct Nat Applied Res Lab | 多基板晶片模組堆疊之三維系統晶片結構 |
KR101683814B1 (ko) | 2010-07-26 | 2016-12-08 | 삼성전자주식회사 | 관통 전극을 구비하는 반도체 장치 |
US9490003B2 (en) * | 2011-03-31 | 2016-11-08 | Intel Corporation | Induced thermal gradients |
US9658678B2 (en) | 2011-03-31 | 2017-05-23 | Intel Corporation | Induced thermal gradients |
US8674483B2 (en) | 2011-06-27 | 2014-03-18 | Marvell World Trade Ltd. | Methods and arrangements relating to semiconductor packages including multi-memory dies |
US8823165B2 (en) | 2011-07-12 | 2014-09-02 | Invensas Corporation | Memory module in a package |
US8502390B2 (en) | 2011-07-12 | 2013-08-06 | Tessera, Inc. | De-skewed multi-die packages |
US8513817B2 (en) | 2011-07-12 | 2013-08-20 | Invensas Corporation | Memory module in a package |
US8436457B2 (en) | 2011-10-03 | 2013-05-07 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
US8659141B2 (en) | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization using duplicate sets of terminals for wirebond assemblies without windows |
EP2769409A1 (en) | 2011-10-03 | 2014-08-27 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with orthogonal windows |
US8436477B2 (en) | 2011-10-03 | 2013-05-07 | Invensas Corporation | Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate |
KR20140069343A (ko) | 2011-10-03 | 2014-06-09 | 인벤사스 코포레이션 | 패키지의 중심으로부터 옵셋된 단자 그리드를 구비하는 스터드 최소화 |
US8525327B2 (en) | 2011-10-03 | 2013-09-03 | Invensas Corporation | Stub minimization for assemblies without wirebonds to package substrate |
US8441111B2 (en) | 2011-10-03 | 2013-05-14 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
US8659143B2 (en) | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization for wirebond assemblies without windows |
JP5887415B2 (ja) | 2011-10-03 | 2016-03-16 | インヴェンサス・コーポレイション | 平行な窓を有するマルチダイのワイヤボンドアセンブリのスタブ最小化 |
CN102446882B (zh) | 2011-12-30 | 2013-12-04 | 北京工业大学 | 一种半导体封装中封装系统结构及制造方法 |
US8848392B2 (en) | 2012-08-27 | 2014-09-30 | Invensas Corporation | Co-support module and microelectronic assembly |
US8848391B2 (en) | 2012-08-27 | 2014-09-30 | Invensas Corporation | Co-support component and microelectronic assembly |
US8787034B2 (en) | 2012-08-27 | 2014-07-22 | Invensas Corporation | Co-support system and microelectronic assembly |
US9368477B2 (en) | 2012-08-27 | 2016-06-14 | Invensas Corporation | Co-support circuit panel and microelectronic packages |
US9070423B2 (en) | 2013-06-11 | 2015-06-30 | Invensas Corporation | Single package dual channel memory with co-support |
CN103426871B (zh) * | 2013-07-25 | 2017-05-31 | 上海航天测控通信研究所 | 一种高密度混合叠层封装结构及其制作方法 |
US9123555B2 (en) | 2013-10-25 | 2015-09-01 | Invensas Corporation | Co-support for XFD packaging |
CN103558903A (zh) * | 2013-11-12 | 2014-02-05 | 上海航天测控通信研究所 | 一种具有抗辐性能的PowerPC计算机模块 |
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US9281296B2 (en) | 2014-07-31 | 2016-03-08 | Invensas Corporation | Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design |
US9691437B2 (en) | 2014-09-25 | 2017-06-27 | Invensas Corporation | Compact microelectronic assembly having reduced spacing between controller and memory packages |
JP2016192447A (ja) * | 2015-03-30 | 2016-11-10 | 株式会社東芝 | 半導体装置 |
EP3255668A4 (en) * | 2015-04-14 | 2018-07-11 | Huawei Technologies Co., Ltd. | Chip |
US9871019B2 (en) | 2015-07-17 | 2018-01-16 | Invensas Corporation | Flipped die stack assemblies with leadframe interconnects |
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US10566310B2 (en) * | 2016-04-11 | 2020-02-18 | Invensas Corporation | Microelectronic packages having stacked die and wire bond interconnects |
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CN108336030A (zh) * | 2018-01-16 | 2018-07-27 | 奥肯思(北京)科技有限公司 | 一种多层堆叠系统级封装 |
KR102699633B1 (ko) | 2019-06-25 | 2024-08-29 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US11075147B2 (en) * | 2019-07-08 | 2021-07-27 | Texas Instruments Incorporated | Stacked die semiconductor package |
CN110943077A (zh) * | 2019-11-08 | 2020-03-31 | 关键禾芯科技股份有限公司 | 毫米波应用的多颗晶片封装结构 |
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- 2007-06-13 WO PCT/US2007/013821 patent/WO2007146307A2/en active Application Filing
- 2007-06-13 CN CN2007800304876A patent/CN101506975B/zh active Active
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US7535110B2 (en) | 2009-05-19 |
US20090212410A1 (en) | 2009-08-27 |
WO2007146307A2 (en) | 2007-12-21 |
EP2033220A2 (en) | 2009-03-11 |
TWI429050B (zh) | 2014-03-01 |
WO2007146307A3 (en) | 2008-03-06 |
JP2009540606A (ja) | 2009-11-19 |
CN101506975A (zh) | 2009-08-12 |
EP2033220B1 (en) | 2019-10-16 |
TW200807670A (en) | 2008-02-01 |
US7825521B2 (en) | 2010-11-02 |
WO2007146307B1 (en) | 2008-05-22 |
US20080006948A1 (en) | 2008-01-10 |
JP5320611B2 (ja) | 2013-10-23 |
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