CN1474453A - 集成电路和分层引线框封装 - Google Patents

集成电路和分层引线框封装 Download PDF

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CN1474453A
CN1474453A CNA031451217A CN03145121A CN1474453A CN 1474453 A CN1474453 A CN 1474453A CN A031451217 A CNA031451217 A CN A031451217A CN 03145121 A CN03145121 A CN 03145121A CN 1474453 A CN1474453 A CN 1474453A
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��ղķ˹����Ƕ�
詹姆斯·纳普
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圣斯蒂芬·杰玫音
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Abstract

一种集成电路(100)，包括半导体管芯(102，103)和半导体封装块(101)，该半导体封装块具有安放半导体管芯的引线框(20，40，60，80)。引线框包括第一叠层(20)，其下表面形成以集成电路引线(106，107，131，132)的图案。第二叠层(40)的下表面(3)和第一叠层的上表面(5)相接触以实现引线和半导体管芯之间的电学耦连。

Description

集成电路和分层引线框封装
发明背景
本发明一般涉及半导体器件，特别涉及小面积封装集成电路。
电子系统制造商继续要求元器件在具有高性能和高可靠性的同时具有小的物理尺寸和低的制造成本。为适应该要求，半导体制造商正致力于发展减小器件尺寸和成本的技术，该技术通过在单一引线框内安放多个元器件实现，该引线框封装形成单个的集成电路封装块。
集成电路块的尺寸部分由封装引线框的最小特征尺寸决定，特征尺寸决定了引线的宽度和空隙。最小特征尺寸典型值大约等于引线框金属的厚度，该厚度是封装块的机械要求和被封装电路的电学和热学规格的函数。例如，高功率电路通常需要较厚的引线框金属来支持大电流水平和充分耗散电路产生的热量。
小的互连特征尺寸预先通过在一个插入件(interposer)上安装电路来实现。插入件是这样一类印刷电路板，它具有夹在两层电介质之间的金属箔片片层，被刻蚀以用来制备互连线，该互连线电学连接安装在插入件上的元件。该金属箔片很薄，这样可以获得小的特征尺寸。然而，对于大电流器件，插入件的薄的金属线必须做的很宽，这会抵消使用金属箔片的优势而增大封装面积。对于高功率应用，插入件的薄金属箔片的高热阻会引起不适宜的热转移。而且，插入件的制作成本很高，这更限制了它们的应用。
其他的器件使用一个压轧的金属引线框，通过半刻蚀技术减薄金属来实现小的特征尺寸，半刻蚀技术选择性刻蚀掉引线框的部分厚度。然而，半刻蚀不易控制，而且由于密封物和半刻蚀引线框的曲面附着不充分，并且导致密封物悬空，集成块的可靠性差。
因此，就需求一种集成电路和封装技术，要求能够在小的占用面积上容纳多个元件，且具有大的电流和热耗散能力，以及高的可靠性，同时保持低的成本。
附图简述
图1是一组集成电路在所选制造步骤的部分等距展示图；
图2是封装的集成电路的剖视图；
图3是另一种实施方案的封装集成电路的剖视图；
图4又是一种实施方案的集成电路的部分等距展示图；和
图5是另外一种实施方案的集成电路的部分等距展示图。
附图详述
图中，标号相同的元件具有相似的功能。
图1为集成电路阵列10在所选制作步骤时的部分等距展示图，包括一个引线框矩阵，该矩阵包括一个叠层矩阵2，叠层矩阵4和一个上方模制的或覆盖的密封块8。大量元件组6安装在叠层矩阵2的预定位置。阵列10中单个的器件称为一个集成电路100，该集成电路100在图中示出分割前的情形。如图所示阵列10由两层叠层矩阵形成，但在一些应用中，使用三层或更多的叠层矩阵来形成引线框更具优点，这样可以获得所需功能。注意，为了简化描述，如图所示的元件组6是以独立的元件形式画出的，但它通常包括多重电学元件，这些电学元件是用标准拾取放置(pick-and-place)工具或类似装备安装的。
叠层矩阵2由一层压轧的铜或其他导电材料形成，该铜或导电材料形成图案来形成具有相同构形的各引线框叠层20的一个阵列来安装元件组6。叠层矩阵2的图案由刻蚀，压印，碾磨或几乎任何其他标准引线框构图方法来实现。叠层矩阵2包括对准孔11，通过该孔在制备过程中插入对准柱(图中未标出)来对准。叠层矩阵2通常厚度超过约50微米。
叠层矩阵4的形成和叠层矩阵2类似，由一层压轧的铜或其他导电材料形成，该铜或导电材料制成图案来形成具有相似构形的引线框叠层40。引线框叠层40的形状通常和引线框叠层20的形状不同。多个对准孔13安置在上面提到的对准叠层矩阵2和4的对准柱上，以使引线框叠层40覆盖在它们对应的引线框叠层20上。叠层矩阵4通常厚度超过大约50微米且其厚度和材料可以和叠层矩阵2不同。例如，在一个实施方案中，叠层矩阵2的厚度大约是50微米以便于以小尺寸刻蚀特征(例如，高的引线密度)，而叠层矩阵4的厚度为1000微米以选择性的提供高的热导或电导。
阵列10的制备如下。叠层矩阵2的上表面5被一层低温焊料，导电环氧或具有导电特性和粘合特性的其他导电材料覆盖，并且可以在低于300摄氏度的条件下处理。叠层矩阵4的下表面3通常由相同的材料覆盖。
接着元件组6安装在它们特定的位置，当下表面3拿来和上表面5接触时对准孔11和13用来对准叠层矩阵2和4。然后叠层矩阵2和4被安放在一个热压或其他标准焊料回流工具上来机械键合下表面3和上表面5，这样也形成了叠层矩阵2和4之间的电学连接。根据应用，如果不在制备周期中较早的完成，其他的制作工艺例如电线键合通常在叠层2和4堆叠和粘附后完成。
在叠层矩阵2和4粘附之后，该组件被放在一个铸型工具里并用标准的热固树脂或热塑模化合物来形成覆盖密封块8。覆盖密封块8覆盖元件组6和暴露的叠层矩阵2和4的表面，该表面在叠层矩阵4的表面22上的密封区域9里面。密封过程留下叠层矩阵2的下表面7未被覆盖或裸露在外，这样可以在分割后提供制作和集成电路100相连的外部电学连接的引线。
当覆盖密封块8凝固以后，叠层矩阵2和4以及覆盖密封块8沿预定的切割线锯成单个的独立的封装集成电路。例如，切割线14，24，16和26定义了从阵列10分割出集成电路100的锯片的路径，以制造独立的封装器件。
所述叠层方案实际上允许任意数目的叠层矩阵形成一个半导体封装块，其最大数目是所需功能，制作成本和最后封装高度的函数。
图2显示了集成电路100的剖视图，其中元件组6包括容纳在封装块101中的半导体管芯102和半导体管芯103，封装块101包括叠层20和叠层40和覆盖密封块8的一个分割出的密封块108。注意集成电路100的左表面和右表面由切割线16和26分别确定。
叠层20被刻蚀形成管芯标志104-105来分别安置半导体管芯102-103，和引线106-107。使用现有的工艺技术，叠层20的最小特性尺寸，例如管芯标记105和引线107之间的间距109，和其厚度大约相等。因此，在一种实施方案中，叠层20厚度为250微米，间隙109的宽度大约也为250微米。
如图所示叠层40的下表面3和叠层20的上表面5相接触，206和207区域和引线106和107电学和机械的相连。叠层40上覆盖在管芯标志104-105区域上的材料被去除，这样半导体管芯102-103可以被安置在叠层矩阵2上并可以无损害的进行后续处理。叠层40厚度的选择比半导体管芯102-102稍厚这样半导体管芯102-103的上表面114-115比表面22所在的平面凹进去一些。例如，在一半导体管芯102-103的厚度大约为250微米的实施方案中，叠层40的厚度选择为大约300微米。
引线键合111在半导体管芯102和206区域之间形成，通过引线键合111、区域206和引线106形成半导体管芯102和外部的电学连接。同样的，引线键合112在半导体管芯103和区域207之间形成，通过引线键合112、区域207和引线107形成半导体管芯103和外部的电学连接。和外部器件或印刷电路板的电学连接通过确定在下表面7上的特征实现，下表面7在封装过程后仍然暴露。引线键合113在半导体管芯102和103之间形成以提供直接的内部连接。
半导体管芯102-103的表面所处的平面114-115低于或略低于表面22。结果，在不引入机械应力前提下，引线键合111和112的回路高度(loop height)比其他半导体封装技术要低很多。短的回路高度减少了引线键合111-112的总长度，这样提供低的寄生电感和寄生电阻，提高了集成电路100的频率响应和整体性能。而且，因为表面22的高度由叠层40的厚度决定，对回路高度的控制得到改善而性能更加一致。
注意区域206-207由切割线16和26分别确定，而引线106-107分别从切割线16和16凹进去一段距离。这样，区域206-207的下表面向外延伸形成一个遮架。这种安排允许固封材料流入下面和覆盖区域206-207裸露的部分形成模封锁120。很多半导体封装用到模封锁以提高机械粘合和防止密封材料悬空以提高可靠性。因为叠层用来形成模封锁120，它们的边缘基本上是直角的，这样可以比使用半刻蚀方法形成的模封锁的曲面的机械和粘附强度都高。
图3显示的剖面图是集成电路100的另一种实施方案，例如，无线通讯设备中的一个收发机。集成电路100上的元件具有和图2所述的相似的结构和功能，除了封装块101由4层叠层形成，包括叠层20和40，在叠层40上形成的叠层60，和在叠层60上形成的叠层80，如图所示。半导体管芯102配置成一个高频、低噪声放大器而半导体管芯103配置成高频、大功率发射级。在某一实施方案中，半导体管芯102-103被指定工作在高于6GHz的操作频率。
叠层40的131-132区域作为集成电路100的引线。叠层40的133-134区域和叠层60的135-136区域如图所示那样堆叠，其功能是在一个可以避免和引线键合112电学接触的高度，作为支持叠层80的137区域的垫层。区域131-137电学耦合在一起作为半导体管芯103周围的法拉第笼或电磁屏障。这样的屏障基本上阻止了由半导体管芯103产生的电磁波传播到半导体管芯102，反之亦然。使用叠层方案形成封装块101的一个结果是，半导体管芯102-103是互相屏幕的。而且，在保持低制造成本的同时，对封装块101的内部和外部的电磁干扰减少。
图4显示了另一种实施方案的集成电路100的部分等轴展示图，包括半导体封装块101，它由叠层20，叠层40、叠层60和密封块108，和元件组6形成。元件组6包括半导体管芯102，封装了的半导体器件320以及包括电感322和旁路电容324的无源元件。
封装了的半导体器件320实现为一个密封的，完全测试的集成电路，容纳在封装块101内并用密封块108再密封。因为不需要导向夹和引线键合工具，和其他的裸露的管芯相比，封装了的半导体器件320可以和半导体管芯102放置得更近。因此，很多情况下这种“层层封装”，和必须在同一个封装块中安装两个独立的未封装的半导体管芯相比，可以实现更小的尺寸。而且，通过在安置入封装块101之前对封装半导体器件320进行测试，整个产出率提高而制造成本降低。
如图所示，电感322电耦合在叠层60的区域151和153之间并与引线161和164电耦合。注意电感322侧向放置并和引线162和163相交，因此提供了灵活的、低成本的互连方案。在某个实施方案中，电感322产生大约1微亨的电感值。
电容324垂直安置在不同叠层之间，即叠层20的管芯标志104和叠层60的区域155之间。这种叠层的应用允许电容324物理地定位于和半导体管芯102相邻的封装块101中，因为内部安装的元件例如电容324具有更低的寄生电感和寄生电阻，这种放置的过滤功能最有效。
图5是集成电路100的又一种实施方案的部分等轴展示图，包括半导体封装块101，它由叠层20，40和60，密封块108和半导体管芯102-103形成。
半导体管芯102由键合区域382和384形成，而半导体管芯103由用来制作电学接触的键合区域383形成。在某个实施方案中，键合区域382-384形成为键合垫，该键合垫由标准半导体互连材料例如铝或铜制成。在另一实施方案中，键合区域382-384可能包括例如焊接球，镀铜或焊料等这样的组合层。
为提供外部的电学连接，叠层60由内部连接区域形成，例如叠层区域380，它电学连接键合区域382和引线390，叠层区域381电学连接键合区域383-384到引线392。使用标准的热压或超声键合工艺或者焊接回流工艺可以实现电学连接。叠层60优选做得薄，这样足够的柔软有利于键合，并且和集成电路键合特征相比具有小的特征尺寸。在某个实施方案中，叠层60的厚度大约为50微米。
注意叠层区域不仅提供了半导体管芯和封装引线之间的电学连接，而且提供了同一封装中安置的半导体管芯之间的电学连接。此外，和叠层区域380-381之间的键合避免了对标准的引线接合的引线结圈的要求，因此寄生电感低而操作频率高。另外，易供给大电流，仅仅制造足够宽大电流叠层区域就可以可靠的处理大电流，因此避免了对多个接合线或更大的接合线的需求。实际上，通过形成合适特征尺寸的叠层60，在相同的结构中，小的特征尺寸可以和大电流能力以及低制造成本相结合。
综上所述，本发明提供了一种低成本的集成电路和封装，经济地把小特性尺寸和大电流能力结合起来。安装半导体管芯的引线框由第一层叠层形成，该叠层的下表面具有集成电路引线的图案。第二层叠层的下表面和第一层叠层的上表面接触以电学耦连引线和半导体管芯。本发明提供了一种高引线密度和大电流能力相结合的低成本结构，提供了较高质量的引线锁合，交叉内部互连和电磁屏障。通过以所需键合图案形成第二叠层，避免了对独立接合线的需求，和其他结构相比，就有较高性能和较低成本。

Claims (10)

1.一种集成电路，其特征在于
第一半导体管芯；和
一个用于安装第一半导体管芯的引线框，它包括：
第一叠层，该叠层的下表面形成有集成电路的引线，和
第二叠层，其下表面和第一层叠层的上表面接触，以将引线电学耦连到第一半导体管芯。
2.权利要求1所述的集成电路，其进一步特征在于包括用于密封第一半导体管芯的化合物。
3.权利要求2所述的集成电路，其中第二叠层形成模化合物的模封锁。
4.权利要求3所述的集成电路，其中第二叠层从引线向外延伸形成一个遮架，模化合物覆盖在遮架上。
5.权利要求1所述的集成电路，其中，第一半导体管芯的下表面安置在第一叠层的上表面上，第二叠层的厚度比第一半导体管芯要厚。
6.权利要求1所述的集成电路，其进一步特征在于安装在引线框上的第二半导体管芯。
7.权利要求6所述的集成电路，其中第一叠层的一条第一内部连线通过第二叠层和第一半导体管芯的键合垫电学耦连。
8.权利要求7所述的集成电路，其中第二叠层由第二内部连线形成，该连线和第二半导体管芯的键合垫电学耦连，并交叉于第一内部连线下方。
9.一种半导体器件，其特征在于：
一个半导体管芯；和
一个引线框，形成为堆叠的导电叠层用来安装半导体管芯，堆叠的导电叠层其中之一被形成图形以形成该半导体器件的外引线，堆叠的导电叠层的另一个被形成图形来将该半导体管芯的键合垫和外部引线电学耦连。
10.一种半导体封装块，其特征在于一个用于安装半导体管芯的引线框，该引线框包括：
第一导电叠层，其下表面被形成图形以制作外部电学连接；和
第二导电叠层，它和第一叠层的上表面相接触，并且提供从半导体管芯到第一导电叠层的信号通路。
CNB031451217A 2002-06-27 2003-06-19 集成电路和分层引线框封装 Expired - Fee Related CN100377351C (zh)

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