CN105376936B - 具有集成的功率电子电路系统和逻辑电路系统的模块 - Google Patents

具有集成的功率电子电路系统和逻辑电路系统的模块 Download PDF

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CN105376936B
CN105376936B CN201510492902.6A CN201510492902A CN105376936B CN 105376936 B CN105376936 B CN 105376936B CN 201510492902 A CN201510492902 A CN 201510492902A CN 105376936 B CN105376936 B CN 105376936B
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power semiconductor
logic
semiconductor modular
circuit plate
embedding
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CN105376936A (zh
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陈柳
M·丁克尔
T·萨米南
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Infineon Technologies AG
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Abstract

具有集成功率电子电路系统和逻辑电路系统的集成功率模块包括埋置功率半导体模块、多层逻辑印刷电路板和柔性连接，该埋置功率半导体模块包括被埋置在介电材料中的一个以上功率半导体裸片，该逻辑印刷电路板具有被装配至该逻辑印刷电路板的表面的一个以上逻辑裸片，该柔性连接被整体地形成在埋置功率半导体模块和逻辑印刷电路板之间。该柔性连接将埋置功率半导体模块机械地连接至逻辑印刷电路板，并且提供埋置功率半导体模块和逻辑印刷电路板之间的电气通路。一种制造该集成功率模块的方法也被提供。

Description

具有集成的功率电子电路系统和逻辑电路系统的模块
技术领域
本申请涉及功率电子电路系统，尤其是集成有逻辑电路系统的功率电子电路系统，该逻辑电路系统控制功率电路系统的运行。
背景技术
许多应用(比如，汽车应用和工业应用)使用功率电子电路系统，比如，绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor，IGBT)、功率金属氧化物半导体场效应晶体管(Metal Oxide Semiconductor Field Effect Transistor，MOSFET)、功率二极管等。例如，常见的功率电路包括单相半波整流器和多相半波整流器、单相全波整流器和多相全波整流器、电压调节器等。集成功率模块(Integrated Power Module IPM)包括功率电子电路系统和逻辑电路系统两者，该逻辑电路系统用于控制功率电子电路系统的运行。在一些常规IPM中，功率裸片(芯片)被附接至功率电子基板，比如，直接键合铜(Direct BondedCopper DBC)、绝缘金属基板(Insulated Metal Substrate，IMS)或活泼金属铜焊(ActiveMetal Brazed，AMB)基板。逻辑裸片被表面装配至单独的逻辑印刷电路板。然后，功率电子基板通过刚性连接器被连接至该逻辑印刷电路板。在其他常规IPM中，连接机制并不是这么庞大。然而，功率裸片通常被表面装配至第二印刷电路板。在这两种IPM实施中，有效面积需要容纳各个部分，这增加了IPM的总体大小和成本。其他的常规IPM把功率半导体模块嵌入至逻辑印刷电路板之内。虽然该方法减少了实施IPM所需的面积，但其具有显著变多的过程步骤并且成本昂贵。因此，需要更小的、更简单的并且更具性价比的IPM解决方案。
发明内容
根据一种使功率电子电路系统和逻辑电路系统互相连接的方法的实施例，该方法包括：提供多层的逻辑印刷电路板和埋置功率半导体模块，该埋置功率半导体模块包括被埋置在介电材料之中的一个以上功率半导体裸片；将该一个以上逻辑裸片装配至逻辑印刷电路板的表面；并且在埋置功率半导体模块和逻辑印刷电路板之间形成整体的柔性连接，该整体的柔性连接将埋置功率半导体模块机械地连接至逻辑印刷电路板，并提供埋置功率半导体模块和逻辑印刷电路板之间的电气通路。
根据一种集成功率模块的实施例，该模块包括埋置功率半导体模块、多层逻辑印刷电路板和柔性连接，该埋置功率半导体模块包括被埋置在介电材料中的一个以上功率半导体裸片，该多层逻辑印刷电路板具有被装配至该逻辑印刷电路板的表面的一个以上逻辑裸片，并且该柔性连接被整体地形成在埋置功率半导体模块和逻辑印刷电路板之间。该柔性连接将埋置功率半导体模块机械地连接至逻辑印刷电路板，并且提供埋置功率半导体模块和逻辑印刷电路板之间的电气通路。
通过阅读下面的具体实施方式以及参看附图，本领域的技术人员将能认识到其他的特征和优点。
附图说明
附图中的元件不一定是彼此相对成比例的。相似的附图标记指相应的类似部件。各种所示实施例的特征能够被结合，除非其彼此排斥。实施例在附图中被示出，并且在接下来的具体实施方式中进行了详细说明。
图1示出了集成功率模块的一个实施例的剖视图，该集成功率模块具有被整体地形成在埋置功率半导体模块和逻辑印刷电路板之间柔性连接；
图2示出了集成功率模块的另一个实施例的剖视图，该集成功率模块具有被整体地形成在埋置功率半导体模块和逻辑印刷电路板之间的柔性连接；
图3A至图3D、图4A和图4B以及图5至图10示出了使用集成功率模块来使功率电子电路系统与逻辑电路系统互相连接的方法的一个实施例的不同阶段；
图11示出了集成功率模块的另一个实施例的剖视图，该集成功率模块具有被整体地形成在埋置功率半导体模块和逻辑印刷电路板之间柔性连接；
图12示出了集成功率模块的另一个实施例的剖视图，该集成功率模块具有被整体地形成在埋置功率半导体模块和逻辑印刷电路板之间柔性连接；
图13示出了集成功率模块的又一个实施例的剖视图，该集成功率模块具有被整体地形成在埋置功率半导体模块和逻辑印刷电路板之间柔性连接；
图14至图17示出了使用集成功率模块来使功率电子电路系统与逻辑电路系统互相连接的方法的另一个实施例的不同阶段。
具体实施方式
本文中所描述的实施例提供了具有被整体地形成在埋置功率半导体模块和逻辑印刷电路板(PCB)之间柔性连接的IPM(集成功率模块。PCB使用由层压在非导电的基板材料之上的铜片(箔)蚀刻形成的导电的轨(痕)、焊盘和其他特征，机械地支撑和电连接电子部件。PCB可以是单面的(例如，一个铜层)、双面的(例如，两个铜层)或多层的。在不同层上的导体与电镀孔通孔(via)、激光钻孔的微通孔、导电胶通孔(例如，ALIVH、B2it)等被连接。先进的PCB可包括被埋置在PCB树脂材料中和/或被装配至PCB表面的部件(比如，电容器、电阻器或有源器件)。在每种情况下，IPM的逻辑PCB包括用于控制埋置功率半导体模块的功率电路系统的逻辑电路系统。IPM的柔性连接将埋置功率半导体模块机械地连接至逻辑印刷电路板，并且提供该埋置功率半导体模块和该逻辑印刷电路板之间的电气通路。本文中所描述的IPM解决方案通过使用例如柔性的互相连接技术(比如，柔性的FR-4、柔性的PCB技术、柔性的印刷电路(FCP)技术等)，允许高密度逻辑PCB与埋置功率技术的结合。
图1示出了一个IPM的实施例的剖视图。根据该实施例，IPM包括埋置功率半导体模块100、多层逻辑印刷电路板(PCB)102和柔性连接104，柔性连接104被整体地形成在埋置功率半导体模块100和逻辑PCB 102之间。由于模块100包括被埋置在介电材料108中的一个以上功率半导体裸片106，因此功率半导体模块100是“埋置模块”。被包括在功率半导体模块100中的功率半导体裸片106可包括任何类型的功率半导体器件，比如垂直电流功率晶体管、横向功率晶体管、分立智能功率晶体管、功率二极管等。在一个实施例中，埋置功率半导体模块100包括金属块110，功率半导体裸片106被附接至金属块110。金属块110和功率半导体裸片106被埋置在介电材料108中。在一个实施例中，功率半导体模块100的介电材料108作为层压过程的部分被形成，该层压过程被用来制造IPM。在另一个实施例中，埋置功率半导体模块100在PCB处理期间被嵌入至逻辑PCB 102之中。另一种其他类型的埋置功率半导体模块可以被使用。
另外的有源部件和/或无源部件112可被装配至埋置功率半导体模块100的表面101。另外的部件112可通过图案化的金属箔114和导电通孔116被电连接至功率半导体裸片106，金属箔114位于埋置功率半导体模块100的装配表面101，导电通孔116在图案化的金属箔114和功率半导体裸片106之间延伸。在一个实施例中，IPM模块通过层压过程被形成，并且图案化的金属箔114是被层压在埋置功率半导体模块100和多层逻辑PCB 102之上的最上面的层压基板的部分。用于控制功率半导体裸片106的运行的一个以上逻辑裸片118以及对应的无源部件120被装配至逻辑PCB 102的外部表面103。例如，逻辑裸片118和无源部件120可以是表面装配技术(Surface Mount Technology SMT)器件。逻辑裸片118可包括用于控制功率半导体裸片106的运行的任何类型的电子器件(比如，控制器、驱动器等)。
在任何情况下，被整体地形成在埋置功率半导体模块100和逻辑PCB 102之间的柔性连接104机械地将埋置功率半导体模块100连接至逻辑PCB 102，并且还提供埋置功率半导体模块100和逻辑PCB 102之间的电气通路。柔性连接104“被整体地形成”在埋置功率半导体模块100和逻辑PCB 102之间，因此柔性连接104不易与埋置功率半导体模块100或逻辑PCB 102分离。相反地，在IPM制造过程期间，柔性连接104变成埋置功率半导体模块100和逻辑PCB 102的整体部分或组成部分。在一个实施例中，IPM通过本文中稍后将更详细描述的层压过程被形成，并且柔性连接104包括被层压至埋置功率半导体模块100和逻辑PCB 102的层压基板。根据此实施例，由该整体的柔性连接所提供的电气通路由被布置在该层压基板的介电材料124上的金属箔122所形成。热沉或板126可在埋置功率半导体模块100下方被附接至金属箔122，例如用来提升在IPM的此区域中的散热，或提供与另外的组件的连接。
通常地，整体的柔性连接104可具有例如通过层压层压板和铜层被形成的一个以上电连接层。整体的柔性连接104桥接了埋置功率半导体模块100和逻辑PCB 102之间的间隙或空间，并且提供功率模块100和逻辑PCB 102之间的柔性机械连接和电连接。整体的柔性连接104可根据IPM所被使用的应用，以各种配置被弯曲。例如在图1中，整体的柔性连接104被弯曲，从而逻辑PCB 102处于一个平面(A)，并且埋置功率半导体模块100处于不同的平面(B)。在一个实施例中，柔性连接104被弯曲，从而如图1中所示的，平面A和平面B垂直。
图2示出了另一个IPM的实施例的剖视图。图2中所示的实施例类似于图1中所示的实施例。然而不同的是，整体的柔性连接104是弯曲的，从而逻辑PCB 102被放置在埋置功率半导体模块100之上。也即，平面A和平面B平行，但彼此以一定距离间隔开。根据此实施例，柔性连接104是弯曲的，从而被装配至逻辑PCB 102的表面103的逻辑裸片118朝向埋置功率半导体模块100。在又一个实施例中，整体的柔性连接104以与图2中所示的相反方式被弯曲，从而逻辑PCB 102被放置在埋置功率半导体模块100的下方，并且被装配至逻辑PCB 102的逻辑裸片118远离埋置功率半导体模块100。
图3至图11示出了一个制造图1和图2中所示的IPM的实施例。根据此实施例，位于埋置功率半导体模块100和逻辑PCB 102之间的整体柔性连接104通过提供层压板被形成，该层压板包括被布置在第一层压基板和第二层压基板之间的逻辑PCB 102和埋置功率半导体模块100，从而介电填充的间隙存在于逻辑PCB 102和功率半导体模块100之间。然后，该层压板在该介电填充间隙的区域处被薄化，从而该层压板的薄化区域形成该整体的柔性连接。
图3包括图3A至图3D，示出了不同的示例性的逻辑PCB和功率模块，该逻辑PCB和功率模块是用于IPM的开始的芯材料。图3A示出了示例性的2层的逻辑PCB芯200，逻辑PCB芯200包括顶层金属箔和底层金属箔202、204(比如，铜箔)以及中间的树脂型介电材料206(比如，聚四氟乙烯、FR-4、FR-1、CEM-1、CEM-3、聚酰亚胺、液晶高聚物等)。图3B示出了示例性的4层的逻辑PCB芯210，逻辑PCB芯210包括顶层金属箔和底层金属箔212、214(比如，铜箔)以及被树脂型介电材料220(比如，聚四氟乙烯、FR-4、FR-1、CEM-1、CEM-3、聚酰亚胺、液晶高聚物等)分开的两层中间的金属箔216、218。仅为简化例证和说明，IPM制造过程参考图3A中所示的示例性的2层逻辑PCB芯200进行说明。通常地，任何高密度的逻辑PCB芯可被使用。图3C示出了用于实施功率半导体模块100的示例性的功率模块芯230的侧视图，并且图3D示出了对应的顶部平面图。功率模块芯230包括金属块232(比如，铜块)，功率半导体裸片106被附接至金属块232。如图3D中所示，功率模块芯230可包括用于不止一个最终IPM的功率半导体裸片106。逻辑PCB芯200/210的厚度(Tlogic)等于功率模块芯230的金属块232和功率半导体裸片106的总厚度(Tpower)。
图4包括图4A和图4B，示出了逻辑PCB芯200，逻辑PCB芯200被放置为邻近各自的功率模块芯230，以形成适合于后面的处理步骤的制造面板240。图4A示出了该布置的顶部平面图，并且图4B示出了沿着图4A中标示为I-II的直线的对应剖视图。
图5示出了被布置在第一层压基板242上的面板240，面板240具有逻辑PCB芯200和功率模块芯230，从而介电填充间隙244保留在各自的逻辑PCB芯200和功率模块芯230之间。根据此实施例，位于逻辑PCB芯200和功率模块芯230之间的间隙244被填充以逻辑PCB芯200的介电材料206。第二层压基板246被类似地布置在逻辑PCB芯200和功率模块芯230上，以形成堆叠，该堆叠包括被嵌入在第一层压基板和第二层压基板242、246之间的逻辑PCB芯和功率模块芯200、230。层压基板242和246可包括被层压有各金属箔248、250的任何标准的介电质247、249(比如，聚四氟乙烯、FR-4、FR-1、CEM-1、CEM-3、聚酰亚胺、液晶高聚物等)。
图6示出了层压之后的该堆叠。层压包括将该堆叠置于压力中，并持续一段时间施加压力和热。该层压过程产生不可分割的整片的层压板252，层压板252可被钻孔、电镀、蚀刻等，以如图6中所示的在层压板252的底层金属箔和顶层金属箔248、250上形成痕(trace)。功率部分和逻辑部分被集成在一起，并且由被层压在一起的不同的逻辑PCB芯和功率模块芯200、230形成。在一个实施例中，第二层压基板246的金属箔250被蚀刻，以形成接触焊盘，用于将逻辑裸片118装配至各逻辑PCB 102的表面103。第二层压基板246的金属箔250还可在不同的区域处被蚀刻，以在各埋置功率半导体模块100上形成外部连接，用于电连接至被埋置在各模块100中的功率半导体裸片106。第一层压基板242的金属箔248也可被蚀刻以为位于每个IPM的埋置功率半导体模块100和对应的PCB 102之间的整体的柔性连接104形成导电痕。
图7示出了在各埋置功率半导体模块100和对应的PCB 102之间形成整体的柔性连接104期间的层压板。标准的精密铣削(比如，机械铣削)可被用于如图7中朝下的箭头所指示的薄化层压板252和形成柔性连接104。例如，通过铣穿逻辑PCB芯200的位于介电填充间隙244的区域处的第二层压基板246和介电(树脂)材料206，层压板252可在位于各自的功率半导体模块100和逻辑PCB 102之间的介电填充间隙244的区域处被变薄。
图8示出了在整体的柔性连接104被形成之后的层压板252。根据此实施例，第一层压基板242的介电材料247的至少一些保留在各自的功率半导体模块100和逻辑PCB 102之间。第一层压基板242的剩余介电材料247和第一层压基板242的被蚀刻金属箔248在每个IPM的埋置功率半导体模块100和逻辑PCB 102之间形成整体的柔性连接104。由每个整体的柔性连接104所提供的电气通路由第一层压基板242的被蚀刻的金属箔(例如，铜箔)248形成。
图9示出了在单独的IPM的分离(单个化)期间的层压板252。任何标准的层压板单个化过程可被用来如图9中向下的箭头所示的使IPM分离(比如，铣削、切割、锯切等)。
图10示出了在分离(单个化)过程之后的IPM中的一个。被整体地形成在埋置功率半导体模块100和逻辑PCB 102之间的柔性连接104将埋置模块100机械连接至逻辑PCB102，并且如本文中先前所描述地提供埋置模块100和逻辑PCB 102之间的电气通路。例如如图1和图2中所示的，逻辑裸片118和任何另外的部件120可在逻辑PCB102的顶表面103上被装配至图案化金属箔250，并且另外的部件112可在埋置功率半导体模块100之上被装配至相同的图案化金属箔250。
图11示出了另一个IPM的实施例的剖视图。根据此实施例，埋置功率半导体模块100作为层压过程的部分被形成，该层压过程被用来制造逻辑PCB 102。位于埋置功率半导体模块100和逻辑PCB 102之间的整体柔性连接104通过标准的精密铣削被形成，该精密铣削包括使在埋置功率半导体裸片106的逻辑PCB 102之间的区域244处的层压板变薄。
图12和图13示出了IPM另一个实施例的剖视图。除了不同的连接至被包在埋置功率半导体模块100之内的功率半导体裸片106的电连接被形成，在图11-13中所示的实施例是类似的。通常地，通过在半导体封装领域中的标准实施，图案化层压基板的对应金属箔并且形成对应的通孔连接，任何期望的电连接可被形成在埋置功率半导体模块100和逻辑PCB102之内以及在功率半导体裸片106和逻辑PCB102之间。
图14至图17示出了另一个制造IPM的实施例。根据此实施例，埋置功率半导体模块100是预层压的镶嵌模块。位于埋置功率半导体模块100和逻辑PCB 102之间的整体柔性连接104通过提供层压板被形成，该层压板包括位于第一层压基板和第二层压基板中间的逻辑PCB 102和被嵌入的埋置功率半导体模块100，从而介电填充间隙存在于逻辑PCB 102和功率模块嵌体100之间。然后，该层压板在该介电填充间隙的区域处被薄化，从而该层压板的薄化区域形成该整体的柔性连接104。
图14示出了面板300，面板300具有被布置在第一层压基板304上的预层压的功率半导体基板嵌体302和相应的逻辑PCB芯200，从而介电填充间隙244保留在各逻辑PCB芯200和功率半导体模块嵌体302之间。根据此实施例，位于逻辑PCB芯200和功率半导体模块嵌体302之间的间隙244被填充以逻辑PCB芯200的介电材料206。第一层压基板304包括被层压有金属箔308的介电材料306(比如，聚四氟乙烯、FR-4、FR-1、CEM-1、CEM-3、聚酰亚胺、液晶高聚物等)。金属箔308可以被图案化，并且导电通孔310可从金属箔308延伸至介电材料306的相对侧面，以与功率半导体模块嵌体302和对应的逻辑PCB芯200形成期望的电连接。第二层压基板312被类似地布置在逻辑PCB芯200和功率半导体模块嵌体302上，以形成堆叠，该堆叠包括位于第一层压基板和第二层压基板304、312之间的逻辑PCB芯和功率半导体模块嵌体200、302。第二层压基板312包括被层压有金属箔316的介电材料314(比如，聚四氟乙烯、FR-4、FR-1、CEM-1、CEM-3、聚酰亚胺、液晶高聚物等)。金属箔316可以被图案化，并且导电通孔318可从金属箔316延伸至介电材料314的相对侧面，以与功率半导体模块嵌体302和各逻辑PCB芯200形成期望的电连接。层压基板304、312可包括被层压有一个以上各金属箔308、316的任何标准的介电质306、314(比如，聚四氟乙烯、FR-4、FR-1、CEM-1、CEM-3、聚酰亚胺、液晶高聚物等)。
图15示出了该堆叠被层压之后的结构。下金属箔和上金属箔308、316中的一个或两个可被图案化，并且相应的导电通孔310、318可延伸至金属320、322(嵌入的功率半导体模块302的对应末端320、322)。通过被嵌入的功率半导体模块302之内的各内部通孔连接326，连接至功率半导体裸片106上的端子324的电连接可被完成，功率半导体裸片106被埋置在被嵌入的功率半导体模块302之中。
图16示出了在铣穿了位于邻接的逻辑PCB 102和被嵌入的功率半导体模块100之间的第二层压基板312和介电填充间隙244之后，并且在单独的IPM的分离(单个化)之后的层压结构。如本文先前所描述的，任何标准的铣削过程和分离(单个化)过程可被使用。
图17示出了在分离(单个化)过程之后的IPM中的一个。被整体地形成在功率半导体模块100和逻辑PCB 102之间的柔性连接104将被嵌入的功率模块100机械连接至逻辑PCB102，并且如本文先前所描述的，提供被嵌入的功率模块100和逻辑PCB 102之间的电气连接。逻辑裸片118和任何另外的部件120可在逻辑PCB 102的顶表面上被装配至图案化金属箔316，并且如果需要，另外的部件112(图17中未示出)可在被嵌入的功率半导体模块100之上被装配至相同的图案化金属箔316。
本文所描述的IPM使用整体的柔性连接方法将高密度逻辑PCB与埋置功率半导体模块结合，这允许3D系统设计(例如，折叠、堆叠)，通过使用单个PCB板的构思简化了装配过程，降低了总成本，同时为高密度PCB和埋置功率半导体模块提供了单独的优化技术，并且允许IPM模块的微型化(缩小)。
空间相关术语比如“下(under、below、lower)”、“上(over、upper)”等被用于简化描述，以解释一个元件相对于第二元件的定位。这些术语旨在涵盖除那些在附图中所示出的不同方位之外的封装的不同方位。此外，术语比如“第一(first)”、“第二(second)”等也被用于描述各种元件、区域、部分等，并且也并非意在限制。贯穿整个描述同样的术语指同样的元件。
如本文所用，术语“具有(having)”、“包括(containing、including、comprising)”等是开放式术语，表示所陈述的元件或特征的存在，但并不排除其它的元件或特征。冠词“一(a或an)”和“该(the)”旨在包括复数形式以及单数形式，除非上下文另有明确说明。
考虑以上所述的变化和应用，应当理解的是，本发明既不受前述具体实施方式的限制，也不受附图限制。相反，本发明仅由下述权利要求及其等同物限制。

Claims (19)

1.一种使功率电子电路系统与逻辑电路系统互相连接的方法，所述方法包括：
提供多层逻辑印刷电路板和埋置功率半导体模块，所述埋置功率半导体模块包括被埋置在介电材料中的一个以上功率半导体裸片；
将一个以上逻辑裸片装配至所述逻辑印刷电路板的表面；以及
在所述埋置功率半导体模块和所述逻辑印刷电路板之间形成整体的柔性连接，所述整体的柔性连接将所述埋置功率半导体模块机械地连接至所述逻辑印刷电路板，并且提供所述埋置功率半导体模块和所述逻辑印刷电路板之间的电气通路，
其中在所述埋置功率半导体模块和所述逻辑印刷电路板之间形成所述整体的柔性连接包括：
形成层压板，所述层压板包括位于第一层压基板和第二层压基板之间的所述逻辑印刷电路板和所述埋置功率半导体模块，位于所述逻辑印刷电路板和所述埋置功率半导体模块之间存在介电填充的间隙；
薄化位于所述介电填充间隙的区域中的所述层压板，从而所述层压板的所薄化的区域形成所述整体的柔性连接。
2.如权利要求1所述的方法，进一步包括：
使所述整体的柔性连接弯曲，从而所述逻辑印刷电路板与所述埋置功率半导体模块处于不同的平面中。
3.如权利要求2所述的方法，
其中所述整体的柔性连接被弯曲，从而所述逻辑印刷电路板处于垂直于所述埋置功率半导体模块所处于的平面的平面。
4.如权利要求1所述的方法，进一步包括：
使所述整体的柔性连接弯曲，从而所述逻辑印刷电路板被放置在所述埋置功率半导体模块之上或在所述埋置功率半导体模块之下。
5.如权利要求4所述的方法，
其中所述整体的柔性连接被弯曲，从而被装配至所述逻辑印刷电路板的所述表面的所述一个以上逻辑裸片朝向所述埋置功率半导体模块。
6.如权利要求1所述的方法，
其中由所述整体的柔性连接所提供的所述电气通路由所述第一层压基板的铜箔形成。
7.如权利要求1所述的方法，进一步包括：
蚀刻所述第二层压基板的、背离所述逻辑印刷电路板和所述埋置功率半导体模块的金属箔，以形成接触焊盘，所述接触焊盘用于将所述一个以上逻辑裸片装配至所述逻辑印刷电路板的所述表面。
8.如权利要求1所述的方法，进一步包括：
蚀刻所述第二层压基板的、背离所述逻辑印刷电路板和所述埋置功率半导体模块的金属箔，以在所述埋置功率半导体模块上形成用于被埋置在所述埋置功率半导体模块中的所述一个以上功率半导体裸片的外部电气连接。
9.如权利要求1所述的方法，其中形成所述层压板包括：
在所述第一层压基板上布置所述逻辑印刷电路板和金属块，所述一个以上功率半导体裸片被附接至所述金属块，从而在所述逻辑印刷电路板和所述埋置功率半导体模块之间的所述介电填充间隙被填充以所述逻辑印刷电路板的介电材料；
将第二层压基板布置在所述逻辑印刷电路板和所述金属块上，以形成堆叠；并且
层压所述堆叠。
10.如权利要求9所述的方法，其中薄化所述层压板包括：
铣穿位于所述介电填充间隙的区域处的所述第二层压基板和所述逻辑印刷电路板的所述介电材料。
11.如权利要求1所述的方法，其中所述埋置功率半导体模块是预层压的埋置功率半导体模块，并且其中形成所述层压板包括：
在所述第一层压基板上布置所述预层压的埋置功率半导体模块，并且在所述预层压的埋置功率半导体模块上布置所述第二层压基板，以形成堆叠；以及
层压所述堆叠。
12.如权利要求11所述的方法，其中薄化所述层压板包括：
铣穿位于所述介电填充间隙的区域处的所述第二层压基板。
13.一种具有集成功率电子电路系统和逻辑电路系统的集成功率模块，包括：
埋置功率半导体模块，其包括被埋置在介电材料中的一个以上功率半导体裸片；
多层逻辑印刷电路板，其具有被装配至所述逻辑印刷电路板的表面的一个以上逻辑裸片；
柔性连接，其被整体地形成在所述埋置功率半导体模块和所述逻辑印刷电路板之间，所述柔性连接将所述埋置功率半导体模块机械地连接至所述逻辑印刷电路板，并且提供所述埋置功率半导体模块和所述逻辑印刷电路板之间的电气通路，
其中所述柔性连接包括层压板，所述层压板包括位于第一层压基板和第二层压基板之间的所述逻辑印刷电路板和所述埋置功率半导体模块，其中介电填充的间隙存在于所述逻辑印刷电路板和所述埋置功率半导体模块之间，以及
其中位于所述介电填充间隙的区域中的所述层压板被薄化，从而所述层压板的所薄化的区域形成所述整体的柔性连接。
14.如权利要求13所述的集成功率模块，
其中所述柔性连接被弯曲，从而所述逻辑印刷电路板与所述埋置功率半导体模块处于不同的平面中。
15.如权利要求14所述的集成功率模块，
其中所述柔性连接被弯曲，从而所述逻辑印刷电路板处于垂直于所述埋置功率半导体模块所处的平面的平面。
16.如权利要求13所述的集成功率模块，
其中所述柔性连接被弯曲，从而所述逻辑印刷电路板被放置在所述埋置功率半导体模块之上或在所述埋置功率半导体模块之下。
17.如权利要求16所述的集成功率模块，
其中所述柔性连接被弯曲，从而被装配至所述所述逻辑印刷电路板的所述表面的所述一个以上逻辑裸片朝向所述埋置功率半导体模块。
18.如权利要求13所述的集成功率模块，
其中由所述整体的柔性连接所提供的所述电气通路由所述第一层压基板和所述第二层压基板的铜箔形成。
19.如权利要求13所述的集成功率模块，
其中所述埋置功率半导体模块被嵌入至所述逻辑印刷电路板之中，并且其中所述逻辑印刷电路板的介电材料在邻近被嵌入的所述功率半导体模块的区域中被薄化，从而薄的介电层和所述逻辑印刷电路板的金属层在所示逻辑印刷电路板和被嵌入的所述功率半导体模块之间形成所述整体的柔性连接。
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