CN100576522C - 半导体封装结构及其制造方法 - Google Patents

半导体封装结构及其制造方法 Download PDF

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Publication number
CN100576522C
CN100576522C CN200610064770A CN200610064770A CN100576522C CN 100576522 C CN100576522 C CN 100576522C CN 200610064770 A CN200610064770 A CN 200610064770A CN 200610064770 A CN200610064770 A CN 200610064770A CN 100576522 C CN100576522 C CN 100576522C
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Prior art keywords
encapsulation
exposes
sign
conductive
columnar leads
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CN200610064770A
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CN101136384A (zh
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舒特师·克里南
贾金得尔·库玛尔
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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Abstract

在一种实施方式中，半导体封装包括一个导电金属块和与其成隔开关系的柱形引线。所述柱形引线被耦合到与金属块相连的电子器件，并且至少在与管芯固定金属块相反的封装一侧露出。进一步露出该管芯固定金属块以便提供金属块向上取向配置的封装。

Description

半导体封装结构及其制造方法
技术领域
本发明涉及电子器件，尤其是半导体封装及其组装方法。
背景技术
在便携电子产品微型化的趋势下，手持消费产品市场迅猛增长。在手机和数字助理市场的驱动下，这些设备的制造商面临着缩小尺寸和更多的类似PC功能需求的挑战。这种挑战对表面安装元件制造商中施加了压力以设计他们的产品支配尽可能最小的面积。由此，将允许便携电子产品设计者在一个设备中整合附加功能而又不用增加整个产品的尺寸。
在芯片规模封装(CSP)工艺中，制造商们努力使封装尺寸尽可能的接近半导体芯片的尺寸。电子工业已经接受电子元件工业联合会(JEDEC)定义的方形扁平无引线封装(QFN)的概要来作为低成本芯片规模封装的良好替代。在典型的QFN封装中，半导体芯片的下侧与金属引线管芯固定盘相连接。导线键合然后被用来连接置于芯片前侧的电路和引线。芯片和引线框架被环氧树脂覆盖来形成一组装元件。然后，管芯固定盘和引线与下一级组件连接，比如说印刷电路板。
图1表示包括引线框架11的传统QFN封装10的剖视图。引线框架11包括一个金属块、标志或者管芯固定部分13来支撑半导体芯片14和引线16。导线键合17将半导体芯片14和引线16相连接。在标志13较低的部分和引线16露出的同时，环氧树脂层19覆盖半导体芯片14和部分引线框架11。在QFN封装中，引线16在封装的边缘终止来提供一个较小的封装印迹(footprint)。典型的QFN封装是正方形的，在封装下表面的四个侧面具有引线16。图1示出了封装10附加在印刷电路板21上，该印刷电路板包括连接或键合焊盘22。图2和图3分别是封装10的等距顶视图和底视图。如图3所示，金属块13和引线16都暴露在封装10的底部或下表面用于与印刷电路板21连接。
QFN封装具备很多优点，包括小封装印迹、使组装更容易的矩阵引线框架陈列、以及已建立的自动组装工具。然而，这种封装随之带来很多问题，包括高功率器件应用时产生的不良导热能力。特别地，在设备10中，金属块13放置在印刷电路板21旁边或者与其邻近，这就必须提供散热。这将导致无效散热和热传导问题，以至影响设备性能、可靠性和产品寿命。
因此，在封装结构和组装方法中存在提供增强的散热能力的需要。需要上述结构和组装方法通过使用例如现有的组装工艺技术而成本高效。
发明内容
根据本发明的一方面，提供一种半导体封装，其特征在于：导电金属块，该导电金属块具有附加到一个表面上的电子芯片；多个柱形引线，该多个柱形引线与导电金属块成隔开的关系，其中该多个柱形引线包括键合凸出部分；导电连接结构，该导电连接结构将电子芯片电耦合到键合凸起部分；和密封层，该密封层覆盖部分导电金属块、多个柱形引线和电子芯片，其中柱形引线的其他部分在半导体封装的第一个表面上露出，并且其中导电金属块在与第一表面相反的半导体封装的第二个表面上露出。
根据本发明的另一方面，提供一种模制半导体封装结构，其特征在于：标志，该标志具有附加到一个表面的半导体器件；多个导电柱，该多个导电柱与该标志成隔开的关系，其中每一个导电柱包括键合延伸部分；导电连接结构，将半导体器件电耦合到键合延伸部分；和密封层，该密封层覆盖部分模制半导体封装结构，其中所述多个导电柱在模制半导体封装结构的第一主要表面露出，并且其中该标志在与第一主要表面相反的第二主要表面露出，使得该模制半导体封装结构被配置成在将其附加到下一级组件时该模制半导体封装结构按金属块向上取向的方式安装。
根据本发明的又一方面，提供一种形成模制半导体封装结构的方法，其特征在于包括以下步骤：提供具有标志和与该标志成隔开关系的多个导电柱的引线框架，其中每一个导电柱包括键合延伸部分将半导体器件附加到该标志的一个表面；将导电连接结构附加到半导体器件和键合延伸部分；以及形成覆盖部分模制半导体封装结构的密封层，其中所述多个导电柱在模制半导体封装结构的第一主要表面露出，并且其中该标志在与第一主要表面相反的第二主要表面露出，使得该模制半导体封装结构被配置成在将其附加到下一级组件时该模制半导体封装结构按金属块向上取向的方式安装。
附图说明
图1是现有技术中方形扁平无引线封装(QFN)的剖视图；
图2是图1中现有技术的QFN封装等距顶视图；
图3是图1中现有技术的QFN封装等距底视图；
图4是根据本发明的半导体封装剖视图；
图5是图4中的半导体封装等距顶视图；
图6是图4中的半导体封装等距底视图；
图7是本发明中引线框架部分的等距图；
图8是根据本发明的替代的实施方式的半导体封装等距顶视图；
图9是图8中的半导体封装等距底视图；
图10是根据本发明的更进一步的实施方式的半导体封装等距底视图；并且
图11是图10中半导体封装的等距顶视图。
具体实施方式
为了容易理解，附图中的元件不必按比例绘制，并且相似的元件数字在不同的附图中在适当时用来指示相同或相似的元件。
图4表示根据本发明的一种实施方式的模制封装结构、半导体封装、或者封装组件40的剖视图。半导体封装40包括一个金属块、标志或者管芯固定盘或者部分43，以及多个导电柱、柱体或者柱形引线46。在本实施方式中，柱形引线46完全穿透封装40而延伸，使得柱形引线46在封装40的两个表面410和420都露出。柱形引线46进一步包括键合部分、凸缘部分、延伸部分、凸出部分或者结构460。在优选实施方式中，键合部分460与柱形引线46形成一体并从柱形引线46的一侧朝着金属块43的方向凸出。
在可选实施方式中并且如图4所示，柱形引线46进一步包括模制锁槽或者结构461来结合模制化合物或钝化材料。举例来说，金属块43和柱形引线46包括诸如铜合金(例如，TOMAC4，TAMAC 5，2ZFROFC，或CDA194)、镀铜的铁/镍合金(例如，镀铜合金42)，经镀敷的铝、经镀敷的塑料等的材料。镀敷材料包括铜、银或多层镀层，如镍-钯和金。
封装40进一步包括一个电子芯片或器件44，使用传统连接工艺由连接或焊料层47与金属块43相连。电子芯片44上的导电层48与键合部分460使用导电连接结构49进行电连接或耦合。在所示的实施方式中，导电连接结构49包括导线键合，如使用传统键合技术形成的金和/或铝导线键合。在替代的实施方式中，导电连接结构49包括导电夹子、带等。依然在进一步的实施方式中，导电连接结构49包括一个导线键合和夹子或带的组合。举例来说，电子芯片44包括一个功率MOSFET、双极功率晶体管、绝缘栅极双极晶体管、半导体闸流管、二极管、传感器、光学器件或其他，以及可能包括更进一步的功能性如逻辑和/或存储单元或电路。
模制的密封或钝化层51覆盖并保护部分封装40。举例来说，密封层51包括一塑料环氧树脂材料，并且使用传统模制技术形成。封装40进一步被显示为与下一级组件或印刷电路板210连接，该电路板包括导电键合部分211。
依照本发明，封装40按向上的方式设置有金属块43，当与印刷电路板210附加时金属块43相反。连同其它方面，这提供了增强的散热，改善了设备的性能和可靠性。特别地，封装40是这样设置的：柱形引线46至少在封装40的表面410或其上露出，与此同时金属块43在封装40的相反表面420上露出。本发明进一步利用标准管芯固定、导线键合，模制和将组件分成单个(singulatingassembly)的步骤，节约成本和制造时间。
在一个替代的实施方式中，使用表面420处的柱形引线46的那些部分，封装40可以附加在下一级组件上。换句话说，封装40设置成按照金属块43向上或向下布置的方式附加到下一级组件，因为柱形引线46完全穿透封装40而延伸。也就是说，封装40可以在散热重要时按照向上配置的方式使用，或者当芯片44包括一个较低功率应用散热不重要时按照向下配置的方式使用。这就增加了设计的灵活性。
可以理解，封装40内部的芯片44的位置和方向以及导线键合/柱形引线46的分配根据向上或向下的配置而可以改变，以便来维持一个想得到的I/O布置。替代地，改变印刷电路板布局以适应任一配置。在一进一步的实施方式中，当封装40是金属块43向上的配置时，在金属块43露出的表面附加一个热沉或结构(未示出)。在如图4所示的仍进一步的实施方式中，封装40可选地包括导热但电绝缘层57，这允许散热但保护封装不在表面420发生短路。举例来说，这种薄膜包括氮化铝或者氮化硼薄膜或膏。
图5表示封装40的等距顶视图，示出表面420。如图5所示，模制锁定结构461填充有密封层51，但是部分柱形引线46连同金属块43露出。图6是封装40的等距底视图，示出露出的表面410及部分柱形引线46。
现在看图7，示出引线框架400部分的等距图以进一步说明本发明。引线框架400和金属块43一起示出，包括与其相连的流道430，进一步按矩阵引线框架配置连接到额外的金属块43(未示出)。举例来说，引线框架400是蚀刻或压制的引线框架。柱形引线46按照与金属块43成接近或隔开的关系示出。流道或框架431为组装工艺而将柱形引线46和流道430连接在一起。之后，在封装被密封后的分成单个工艺(singulation process)中，例如使用切割线432，切掉或分离流道431。
图8给出了根据本发明的替代的实施方式的半导体封装401的等距顶视图。本实施方式中的封装401与封装40相似，除了柱形引线46不完全穿透封装而延伸之外，从而部分柱形引线46不在封装401的表面420露出。即，在该配置中，仅金属块43在表面420露出。与封装40相似，封装41中的金属块43暴露于表面420，并且按金属块向上的配置来增强散热。图9示出封装401的等距底视图。如图9所示，柱形引线46暴露于表面410，用于与下一级组件相连，如印刷电路板210。
图10表示根据本发明的更进一步的实施方式的半导体封装100的等距视图。封装100包括一个金属块、标志或管芯固定盘103和导电柱、柱体或者柱形引线106，与金属块103成隔开的关系。在这一实施方式中，柱形引线106仅在封装100的一侧上。柱形引线106进一步包括键合部分、凸缘部分、延伸部分、凸出部分或者结构160。举例来说，金属块103和柱形引线106包括诸如铜合金(例如，TOMAC4，TAMAC 5，2ZFROFC，或CDA194)、镀铜的铁/镍合金(例如，镀铜合金42)、经镀敷的铝、经镀敷的塑料等材料。镀敷材料包括铜、银或多层镀层，如镍-钯和金。
封装100进一步包括采用管芯固定层107连接到金属块103的电子芯片104。使用连接结构，芯片104上的导电焊盘108被连接或电耦合到柱形引线106，该连接结构包括导线键合109、导电夹子或带111、其组合等。在本实施方式中，采用连接结构109，金属块103也与柱形引线106之一连接。在替代的实施方式中，一个外部导电夹或其他导电方式被连接到金属块103的外部暴露表面，用于将金属块103电耦合到下一级组件。模制的密封或钝化层151覆盖并保护部分封装100。举例来说，密封层151包括塑性环氧树脂材料，并且使用传统模制工艺形成。
依照本发明，封装100被配置按金属块103向上的方向来安装，这在封装100被连接到下一级组件时提供增强的散热。并且，由于柱形引线106完全穿透封装封装100，使得柱形引线106在封装100的两个表面110和120都露出，封装100可以在散热重要时按向上的配置使用，或者当芯片104包括一个较低功率应用散热不重要时按向下的配置使用。这提供了增加的设计灵活性。
在替代的实施方式中，柱形引线106没有完全穿透封装100，而是仅在封装100的一侧110露出，然后仅按金属块103向上的配置安装封装100。举例来说，本实施方式中柱形引线106的部分161被去除。这个实施方式进一步示于图11中，该图是观看表面120和金属块103的封装100的等距图。当安装到下一级组件(例如，图4中的印刷电路板210)时，金属块103是向上的配置，表面110邻接与下一级组件而放置。可以理解，当按向上的配置安装时，向金属块103附加额外的热沉以进一步增强散热。另外，可以可选地向表面120附加导热但电绝缘层，如上面结合图4描述的那样。
因此，显然已经提供根据本发明的封装结构和组装方法，其中该结构被配置成金属块向上取向。在功率器件应用中，这将增强封装的散热能力，改善其性能和可靠性。在一种实施方式中，柱形引线穿透封装而延伸并在该封装的两侧露出。这提供进一步的组装和设计灵活性。另外，封装结构使用传统的封装工艺，节约制造和实施成本。
尽管已参照实施方式描述和举例说明本发明，但是并不意味着本发明限于这些举例说明的实施方式。

Claims (10)

1.一种具有相对的第一和第二主表面的半导体封装，其特征在于：
导电金属块，所述导电金属块具有附加到一个表面上的电子芯片；
多个柱形引线，所述多个柱形引线与导电金属块成隔开的关系，其中所述多个柱形引线中的每一个包括键合凸出部分，并且其中所述多个柱形引线中的每一个具有一对重叠的相对端面；
导电连接结构，所述导电连接结构将电子芯片电耦合到键合凸出部分；和
密封层，所述密封层覆盖部分导电金属块、多个柱形引线和电子芯片，其中至少一个柱形引线的相对端面中的一个端面在所述第一主表面上露出，并且其中导电金属块在所述第二主表面上露出。
2.根据权利要求1所述的封装，其中至少一个柱形引线的相对端面中的另一个端面在所述第二主表面露出。
3.根据权利要求1所述的封装，其中所述键合凸出部分与所述多个柱形引线形成一体，并且其中每一个键合凸出部分从每一个柱形引线的一侧朝着导电金属块的方向凸出，并且其中至少一个键合凸出部分位于至少一个柱形引线的基本上中间位置。
4.根据权利要求1所述的封装，其中至少一个导电连接结构具有一个导电夹。
5.一种具有相对的第一和第二主表面的模制半导体封装结构，其特征在于：
标志，所述标志具有附加到一个表面的半导体器件；
多个导电柱，所述多个导电柱与所述标志成隔开的关系，其中每一个导电柱包括键合延伸部分，并且其中每一个导电柱包括一对重叠的相对面；
导电连接结构，将半导体器件电耦合到键合延伸部分；和
密封层，所述密封层覆盖部分模制半导体封装结构，其中所述多个导电柱中的至少一部分导电柱中的每一个导电柱的所述相对面中的一个面在所述第一主表面露出，并且其中所述标志在所述第二主表面露出，使得所述模制半导体封装结构被配置成在将其附加到下一级组件时所述模制半导体封装结构按标志向上取向的方式安装。
6.根据权利要求5所述的封装，其中所述多个导电柱仅在所述封装的一侧上。
7.根据权利要求5所述的封装，进一步特征在于在所述第二主表面上形成的导热且电绝缘的材料的层。
8.一种形成具有相对的第一和第二主表面的模制半导体封装结构的方法，其特征在于包括以下步骤：
提供具有标志和与所述标志成隔开关系的多个导电柱的引线框架，其中每一个导电柱包括键合延伸部分，并且其中每一个导电柱包括一对重叠的相对面；
将半导体器件附加到所述标志的一个表面；
将导电连接结构附加到半导体器件和键合延伸部分；以及
形成覆盖部分模制半导体封装结构的密封层，其中所述多个导电柱中的至少一部分的相对面中的一个面在所述第一主表面露出，并且其中所述标志在所述第二主表面露出，使得所述模制半导体封装结构被配置成在将其附加到下一级组件时所述模制半导体封装结构按标志向上取向的方式安装。
9.根据权利要求8所述的方法，其中所述形成密封层的步骤包括形成密封层，其中所述多个导电柱中的至少一部分导电柱中的每一个导电柱的所述相对面中的另一个面还在第二主表面露出。
10.根据权利要求8所述的方法，其中所述提供引线框架的步骤包括提供仅在一侧具有多个导电柱的引线框架。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6605866B1 (en) * 1999-12-16 2003-08-12 Amkor Technology, Inc. Stackable semiconductor package and method for manufacturing same
CN1474453A (zh) * 2002-06-27 2004-02-11 �뵼��Ԫ����ҵ�������ι�˾ 集成电路和分层引线框封装

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6605866B1 (en) * 1999-12-16 2003-08-12 Amkor Technology, Inc. Stackable semiconductor package and method for manufacturing same
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