CN102446882B - 一种半导体封装中封装系统结构及制造方法 - Google Patents

一种半导体封装中封装系统结构及制造方法 Download PDF

Info

Publication number
CN102446882B
CN102446882B CN201110456464XA CN201110456464A CN102446882B CN 102446882 B CN102446882 B CN 102446882B CN 201110456464X A CN201110456464X A CN 201110456464XA CN 201110456464 A CN201110456464 A CN 201110456464A CN 102446882 B CN102446882 B CN 102446882B
Authority
CN
China
Prior art keywords
chip
material layer
metal material
lead frame
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201110456464XA
Other languages
English (en)
Other versions
CN102446882A (zh
Inventor
秦飞
夏国峰
安彤
刘程艳
武伟
朱文辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing University of Technology
Original Assignee
Beijing University of Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing University of Technology filed Critical Beijing University of Technology
Priority to CN201110456464XA priority Critical patent/CN102446882B/zh
Publication of CN102446882A publication Critical patent/CN102446882A/zh
Priority to US14/354,583 priority patent/US9397068B2/en
Priority to PCT/CN2012/085785 priority patent/WO2013097581A1/zh
Application granted granted Critical
Publication of CN102446882B publication Critical patent/CN102446882B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142—Metallic substrates having insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/45664—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49544—Deformation absorbing parts in the lead frame plane, e.g. meanderline shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/171—Frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Abstract

本发明公开了一种半导体封装中封装系统结构及制造方法。本半导体封装中封装系统结构包括引线框架、第一金属材料层、第二金属材料层、具有凸点的IC芯片、引线键合的IC芯片、绝缘填充材料、粘贴材料和塑封材料。引线框架包括芯片载体和多个围绕芯片载体呈多圈排列的引脚。第一金属材料层和第二金属材料层分别配置于引线框架上表面和下表面。绝缘填充材料配置于引线框架的台阶式结构下。引线键合的IC芯片配置于芯片载体上。具有凸点的IC芯片的凸点倒装焊接配置于多圈引脚的内引脚上，通过塑封材料包覆具有凸点的IC芯片、引线键合的IC芯片形成半导体封装中封装系统结构。本发明是基于QFN封装的高可靠性、低成本、高I/O密度的三维封装结构及其制造方法。

Description

一种半导体封装中封装系统结构及制造方法
技术领域
本发明涉及半导体元器件制造技术领域，尤其涉及到基于QFN封装的半导体封装中封装(Package in Package，PiP)系统结构，本发明还包括该封装件的制造方法。
背景技术
随着电子产品如手机、笔记本电脑等朝着小型化，便携式，超薄化，多媒体化以及满足大众化所需要的低成本方向发展，高密度、高性能、高可靠性和低成本的封装形式及其组装技术得到了快速的发展。与价格昂贵的BGA等封装形式相比，近年来快速发展的新型封装技术，即四边扁平无引脚QFN(Quad Flat Non-lead Package)封装，由于具有良好的热性能和电性能、尺寸小、成本低以及高生产率等众多优点，引发了微电子封装技术领域的一场新的革命。
图1A和图1B分别为传统QFN封装结构的背面示意图和沿
Figure BDA0000127617420000011
剖面的剖面示意图，该QFN封装结构包括引线框架11，塑封材料12，粘片材料13，IC芯片14，金属导线15，其中引线框架11包括芯片载体111和围绕芯片载体111四周排列的引脚112，IC芯片14通过粘片材料13固定在芯片载体111上，IC芯片13与四周排列的引脚112通过金属导线15实现电气连接，塑封材料12对IC芯片14、金属导线15和引线框架11进行包封以达到保护和支撑的作用，引脚112裸露在塑封材料12的底面，通过焊料焊接在PCB等电路板上以实现与外界的电气连接。底面裸露的芯片载体111通过焊料焊接在PCB等电路板上，具有直接散热通道，可以有效释放IC芯片14产生的热量。与传统的TSOP和SOIC封装相比，QFN封装不具有鸥翼状引线，导电路径短，自感系数及阻抗低，从而可提供良好的电性能，可满足高速或者微波的应用。裸露的芯片载体提供了卓越的散热性能。
随着IC集成度的提高和功能的不断增强，IC的I/O数随之增加，相应的电子封装的I/O引脚数也相应增加，且逐渐由传统的二维平面封装形式向更高集成度的三维立体封装形式发展，传统的四边扁平无引脚封装件为典型的二维平面封装形式，单圈的引脚围绕芯片载体呈周边排列，限制了I/O数量的提高，满足不了高密度、具有更多I/O数的IC的需要。传统的引线框架无台阶式结构设计，无法有效的锁住塑料材料，导致引线框架与塑封材料结合强度低，易于引起引线框架与塑封材料的分层甚至引脚或芯片载体的脱落，而且无法有效的阻止湿气沿着引线框架与塑封材料结合界面扩散到电子封装内部，从而严重影响了封装体的可靠性。传统QFN产品在塑封工艺时需要预先在引线框架背面粘贴胶带以防止溢料现象，待塑封后还需进行去除胶带、塑封料飞边等清洗工艺，增加了封装成本增高。使用切割刀切割分离传统的四边扁平无引脚封装件，切割刀在切割塑封材料的同时也会切割到引线框架金属，不仅会造成切割效率的降低和切割刀片寿命的缩短，而且会产生金属毛刺，影响了封装体的可靠性。因此，为了突破传统QFN的低I/O数量的瓶颈，提高封装体的可靠性和降低封装成本，急需研发一种基于QFN封装的高可靠性、低成本、高I/O密度的三维封装结构及其制造方法。
发明内容
本发明提供了一种基于QFN封装的半导体封装中封装(Package inPackage，PiP)系统结构及其制造方法，以达到突破传统QFN的低I/O数量的瓶颈和提高封装体的可靠性的目的。
为了实现上述目的，本发明采用下述技术方案：
本发明提出一种半导体封装中封装(PiP)系统结构，包括引线框架、第一金属材料层、第二金属材料层、具有凸点的IC芯片、引线键合的IC芯片、金属导线、绝缘填充材料、粘贴材料和塑封材料。引线框架沿厚度方向具有台阶式结构，具有上表面、下表面和台阶表面。引线框架包括芯片载体和多个围绕芯片载体呈多圈排列的引脚。芯片载体配置于引线框架中央部位，芯片载体四边边缘部位沿厚度方向具有台阶式结构。围绕芯片载体呈多圈排列的引脚的横截面形状呈圆形或者矩形状，其中每个引脚包括配置于该上表面的内引脚和配置于该下表面的外引脚。第一金属材料层和第二金属材料层分别配置于引线框架的上表面位置和下表面位置。缘填充材料配置于引线框架的台阶式结构下，支撑、保护引线框架，暴露出配置于引线框架下表面的第二金属材料层。引线键合的IC芯片通过粘片材料配置于引线框架上表面位置的第一金属材料层上，且配置于芯片载体的中央部位，引线键合的IC芯片上的多个键合焊盘通过金属导线分别连接至多个配置有第一金属材料层的多个引脚的内引脚，塑封材料包覆引线键合的IC芯片、粘贴材料、金属导线、芯片载体和具有第一金属材料层的多个引脚，形成封装件。具有凸点的IC芯片通过倒装上芯设备配置于具有金属材料层的多个引脚的内引脚上，IC芯片上的凸点通过回流焊或者热压焊与多圈引脚的内引脚连接，具有凸点的IC芯片通过粘贴材料配置于第一次塑封后的封装件上，塑封材料包覆具有凸点的IC芯片、凸点、第一次塑封后的封装件、粘贴材料和具有第一金属材料层的多个引脚，形成产品阵列。
根据本发明的实施例，半导体封装中封装(PiP)系统结构包括两个封装件。
根据本发明的实施例，引脚框架具有多个围绕芯片载体呈三圈排列的引脚。
根据本发明的实施例，包括芯片载体和围绕芯片载体呈三圈排列的引脚具有台阶式结构。
根据本发明的实施例，围绕芯片载体呈三圈排列的引脚的横截面形状呈圆形形状。
根据本发明的实施例，围绕芯片载体呈三圈排列的引脚的横截面形状呈矩形形状。
根据本发明的实施例，芯片载体每边的引脚排列方式为平行排列。
根据本发明的实施例，芯片载体每边的引脚排列方式为交错排列。
根据本发明的实施例，引线框架上表面和下表面分别配置有第一金属材料层和第二金属材料层。
根据本发明的实施例，引线框架上表面和下表面分别配置的第一金属材料层和第二金属材料层包括镍(Ni)、钯(Pd)、金(Au)金属材料。
根据本发明的实施例，通过倒装上芯设备将具有凸点的IC芯片倒装焊接配置于具有第一金属材料层的多个引脚的内引脚上，IC芯片上的凸点通过回流焊或者热压焊与多个引脚的内引脚连接。
根据本发明的实施例，通过导热的粘贴材料将引线键合的IC芯片配置于芯片载体上，将具有凸点的IC芯片配置于第一次塑封后的封装件上。
根据本发明的实施例，引线键合的IC芯片封装件具有两圈排列的引脚。根据本发明的实施例，具有凸点的IC芯片上的凸点呈单圈排列，且分别焊接配置于呈三圈排列的引脚的最外圈。
根据本发明的实施例，IC芯片上凸点为无铅焊料凸点、含铅焊料凸点或者金属凸点。
根据本发明的实施例，引线键合的IC芯片配置于具有凸点的IC芯片与引线框架之间。
根据本发明的实施例，引线框架台阶式结构下配置绝缘填充材料。
根据本发明的实施例，引线框架台阶式结构下配置绝缘填充材料种类是热固性塑封材料，或者塞孔树脂、油墨以及阻焊绿油等材料。
本发明提出一种半导体封装中封装(PiP)系统结构的制造方法，包括以下步骤：
步骤1：配置掩膜材料层
对薄板基材进行清洗和预处理，在薄板基材的上表面和下表面配置具有窗口的掩膜材料层图形。
步骤2：配置金属材料层
在配置于薄板基材上表面和下表面的掩膜材料层的窗口中分别配置第一金属材料层和第二金属材料层。
步骤3：下表面选择性部分蚀刻
移除薄板基材下表面的掩膜材料层，以第二金属材料层为抗蚀层，对薄板基材下表面进行选择性部分蚀刻，形成凹槽。
步骤4：配置绝缘填充材料
在薄板基材下部分经选择性半蚀刻形成的凹槽中填充绝缘材料。
步骤5：上表面选择性部分蚀刻
移除薄板基材上表面的掩膜材料层，以第一金属材料层为阻蚀层，对薄板基材上表面进行选择性部分蚀刻，形成具有台阶式结构的引线框架，包括分离的芯片载体和多圈引脚。
步骤6：配置引线键合的IC芯片
通过含银颗粒的环氧树脂树脂或者胶带等导热粘贴材料将引线键合的IC芯片配置于芯片载体中央部位。
步骤7：引线键合连接
引线键合的IC芯片上的多个键合焊盘通过金属导线分别连接至配置有第一金属材料层的多个引脚的内引脚，以实现电气互联。
步骤8：第一次塑封
通过塑封材料包覆引线键合的IC芯片、粘贴材料、金属导线、芯片载体和具有第一金属材料层的多个引脚，形成封装件。
步骤9：配置具有凸点的IC芯片
通过倒装上芯设备将具有凸点的IC芯片倒装焊接配置于具有第一金属材料层的多个引脚的内引脚上，通过回流焊或者热压焊实现凸点与多个引脚的内引脚相连，具有凸点的IC芯片通过导热粘贴材料配置于第一次塑封后的封装件上。
步骤10：第二次塑封
通过塑封材料包覆具有凸点的IC芯片、第一次塑封后的封装件、粘贴材料和具有第一金属材料层的多个引脚，形成产品阵列。
步骤11：打印
对半导体封装中封装(PiP)系统结构的产品阵列进行激光打印。
步骤12：切割分离产品
切割分离产品，形成独立的单个封装系统。
根据本发明的实施例，通过电镀或者化学镀方法配置第一金属材料层和第二金属材料层。
根据本发明的实施例，以第一金属材料层和第二金属材料层为抗蚀层，分别对薄板基材上表面和下表面选择性部分蚀刻。
根据本发明的实施例，绝缘填充材料通过丝网印刷或者涂布等方法配置在半蚀刻凹槽中。
根据本发明的实施例，IC芯片上的凸点通过回流焊或者热压焊与多个引脚的内引脚连接。
根据本发明的实施例，半导体封装中封装(PiP)系统结构通过两次塑封工艺形成。
根据本发明的实施例，选用刀片切割、激光切割或者水刀切割等方法切割分离产品，且仅切割塑封材料和绝缘填充材料，不切割引线框架。
基于上述，根据本发明，基于传统QFN封装的半导体封装中封装(PiP)系统结构为三维立体封装，高度可控制在0.7毫米内，具有较高的I/O密度和集成度，引线框架的台阶式结构增加了与塑封材料和绝缘填充材料的结合面积，具有与塑封材料和绝缘填充材料相互锁定的效果，能够有效防止引线框架与塑封材料和绝缘填充材料的分层以及引脚或芯片载体的脱落，有效阻止湿气从封装件结构外部向内部扩散，小面积尺寸的外引脚能够有效防止表面贴装时桥连现象的发生，引线框架上表面和下表面分别配置的第一金属材料层和第二金属材料层能够有效提高引线键合质量、倒装焊接质量和表面贴装质量，由于单个封装系统之间仅由塑封材料和绝缘填充材料相连，因此当使用切割刀切割分离产品，不会切割到引线框架金属材料，从而提高了切割效率，延长了切割刀的寿命，防止了金属毛刺的产生，同时省去了传统QFN封装流程中的塑封前引线框架背面粘贴胶膜、塑封后去除胶膜和塑封料飞边等工艺，降低了封装成本。
下文特举实施例，并配合附图对本发明的上述特征和优点做详细说明。
附图说明
图1A为传统QFN封装结构的背面示意图；
图1B为沿图1A中的
Figure BDA0000127617420000061
剖面的剖面示意图；
图2A为根据本发明的实施例绘制的引脚横截面为圆形，且芯片载体每边的引脚排列方式为平行排列的半导体封装中封装(PiP)系统结构的背面示意图；
图2B为根据本发明的实施例绘制的引脚横截面为矩形，且芯片载体每边的引脚排列方式为平行排列的半导体封装中封装(PiP)系统结构的背面示意图；
图3A为根据本发明的实施例绘制的引脚横截面为圆形，且芯片载体每边的引脚排列方式为交错排列的半导体封装中封装(PiP)系统结构的背面示意图；
图3B为根据本发明的实施例绘制的引脚横截面为矩形，且芯片载体每边的引脚排列方式为交错排列的半导体封装中封装(PiP)系统结构的背面示意图；
图4为根据本发明的实施例绘制的，沿图2A-B和图3A-B中的I-I剖面的剖面示意图；
图5A至图5N为根据本发明的实施例绘制的半导体封装中封装(PiP)系统结构的制造流程剖面示意图，所有剖面示意图都为沿图4剖面所示的剖面示意图。
图中标号：100.传统四边扁平无引脚封装结构，11.引脚框架，111.芯片载体112.引脚，12.塑封材料，13.粘片材料，14.IC芯片，15.金属导线，200、200a、200b、200c、200d.半导体封装中封装(PiP)系统结构，201.引线框架，202.芯片载体，203.引脚，20.薄板基材，20a.薄板基材上表面、引线框架上表面，20b.薄板基材下表面、引线框架下表面，21a、21b.掩膜材料层，22.第一金属材料层，23.第二金属材料层，22a.第一金属材料层表面，23a.第二金属材料层表面，24.凹槽，24a.台阶式结构表面，24b.台阶式结构，25.绝缘填充材料，25a.绝缘填充材料表面，26.粘贴材料，27.引线键合的IC芯片，28.金属导线，29.塑封材料，30.具有凸点的IC芯片，31.凸点。
具体实施方式
下面结合附图对本发明进行详细说明：
图2A为根据本发明的实施例绘制的引脚横截面为圆形，且芯片载体每边的引脚排列方式为平行排列的半导体封装中封装(PiP)系统结构的背面示意图。图2B为根据本发明的实施例绘制的引脚横截面为矩形，且芯片载体每边的引脚排列方式为平行排列的半导体封装中封装(PiP)系统结构的背面示意图。
参照上述图2A-B可以看出，在本实施例中，半导体封装中封装(PiP)系统结构200a和200b的引线框架201包括芯片载体202和围绕芯片载体202呈多圈排列的引脚203，且芯片载体202每边的引脚203的排列方式为平行排列，在引线框架201下表面配置有第二金属材料层23，在引线框架201中配置有绝缘填充材料25。不同之处在于图2A的半导体封装中封装(PiP)系统结构中的引脚横截面为圆形，图2B的半导体封装中封装(PiP)系统结构中的引脚横截面为矩形。
图3A为根据本发明的实施例绘制的引脚横截面为圆形，且芯片载体每边的引脚排列方式为交错排列的半导体封装中封装(PiP)系统结构的背面示意图。图3B为根据本发明的实施例绘制的引脚横截面为矩形，且芯片载体每边的引脚排列方式为交错排列的半导体封装中封装(PiP)系统结构的背面示意图。
参照上述图3A-B可以看出，在本实施例中，半导体封装中封装(PiP)系统结构200c和200d的引线框架201包括芯片载体202和围绕芯片载体202呈多圈排列的引脚203，且芯片载体202每边的引脚203的排列方式为交错排列，在引线框架201下表面配置有第二金属材料层23，在引线框架201中配置有绝缘填充材料25。不同之处在于图3A的半导体封装中封装(PiP)系统结构中的引脚横截面为圆形，图3B的半导体封装中封装(PiP)系统结构中的引脚横截面为矩形。
图4为根据本发明的实施例绘制的，沿图2A-B和图3A-B中的I-I剖面的剖面示意图。结合图2A-B、图3A-B，参照图4，在本实施例中，半导体封装中封装(PiP)系统结构200包括引线框架201、第一金属材料层22、第二金属材料层23、绝缘填充材料25、粘贴材料26、引线键合的IC芯片27、金属导线28、塑封材料29、具有凸点的IC芯片30和凸点31。
在图4的实施例中，引线框架201作为导电、散热、连接外部电路的通道，沿厚度方向具有台阶式结构24b，具有上表面20a和相对于上表面20a的下表面20b，以及台阶式结构24b的台阶表面24a。引线框架201包括芯片载体202和围绕芯片载体202呈多圈排列的引脚203，芯片载体202和围绕芯片载体202呈多圈排列的引脚203都具有台阶式结构24b。芯片载体202配置于引线框架201中央部位，芯片载体202四边边缘部位沿厚度方向具有台阶式结构24b。多个引脚203配置于芯片载体202四周，围绕芯片载体202呈多圈排列，且沿厚度方向具有台阶结构24b，其横截面形状呈圆形或者矩形状，其中每个引脚203包括配置于该上表面20a的内引脚和配置于该下表面20b的外引脚。
第一金属材料层22和第二金属材料层23分别配置于引线框架201的上表面20a位置和引线框架201的下表面20b位置，第一金属材料层22与引脚203的内引脚具有相同尺寸大小，第二金属材料层23与引脚203的外引脚具有相同尺寸大小。第一金属材料层22具有金属材料层表面22a，第二金属材料层23具有金属材料层表面23a。
绝缘填充材料25配置于引线框架201的台阶式结构24下，对引线框架201起到支撑和保护的作用，绝缘填充材料25具有绝缘填充材料表面25a，绝缘填充材料表面25a与金属材料层表面23a处于同一水平面上。
通过含银颗粒的环氧树脂树脂或者胶带等导热粘贴材料26将引线键合的IC芯片27配置于芯片载体202的中央部位。塑封材料29包覆引线键合的IC芯片27、粘贴材料26、金属导线28、芯片载体202和具有第一金属材料层22的多个引脚203，形成封装件。在本实施例中，引线键合的IC芯片封装件具有两圈排列的引脚。具有凸点的IC芯片30通过倒装上芯设备配置于引脚203的内引脚上，且通过粘片材料26配置于第一次塑封后的封装件上，IC芯片30上的凸点31通过回流焊或者热压焊与多圈引脚203的内引脚连接，塑封材料29包覆具有凸点的IC芯片27、凸点31、第一次塑封后的封装件、粘贴材料26和具有第一金属材料层22的多个引脚203，形成半导体封装中封装(PiP)系统结构200产品阵列。在本实施例中，具有凸点的IC芯片30上的凸点31呈单圈排列，且分别焊接配置于呈三圈排列引脚203的最外圈。
下面将以图5A至图5N来详细说明一种半导体封装中封装(PiP)系统结构的制造流程。
图5A至图5N为根据本发明的实施例绘制的半导体封装中封装(PiP)系统结构的制造流程剖面示意图，所有剖面示意图都为沿图4剖面所示的剖面示意图。
请参照图5A，提供具有上表面20a和相对于上表面20a的下表面20b的薄板基材20，薄板基材20的材料可以是铜、铜合金、铁、铁合金、镍、镍合金以及其他适用于制作引线框架的金属材料。薄板基材20的厚度范围为0.1mm-0.25mm，例如为0.127mm，0.152mm，0.203mm。对薄板基材20的上表面20a和下表面20b进行清洗和预处理，例如用等离子水去油污、灰尘等，以实现薄板基材20的上表面20a和下表面20b清洁的目的。
请参照图5B，在薄板基材20的上表面20a和下表面20b上分别配置具有窗口的掩膜材料层21a和掩膜材料层21b，这里所述的窗口是指没有被掩膜材料层21a和掩膜材料层21b覆盖的薄板基材20，掩膜材料层21a和掩膜材料层21b保护被其覆盖的薄板基材20，在后面的工艺步骤中将对被掩膜材料层21a和掩膜材料层21b覆盖的薄板基材20进行蚀刻。
请参照图5C，在配置于薄板基材20的上表面20a上的掩膜材料层21a的窗口中配置第一金属材料层22，第一金属材料层22具有第一金属材料层表面22a，在配置于薄板基材20的下表面20b上的掩膜材料层21b的窗口中配置第二金属材料层23，第二金属材料层23具有第二金属材料层表面23a。第一金属材料层22和第二金属材料层23的配置方法为电镀、化学镀、蒸发、溅射等方法，并且允许由不同的金属材料组成，在本实施例中，优先选择电镀或者化学镀作为第一金属材料层22和第二金属材料层23的配置方法。第一金属材料层22和第二金属材料层23的材料是镍(Ni)、钯(Pd)、金(Au)、银(Ag)、锡(Sn)等金属材料及其合金，在本实施例中，第一金属材料层22和第二金属材料层23例如是镍-钯-金镀层，对于第一金属材料层22，外面的金镀层和中间的钯镀层是保证金属导线28在引线框架201上的引线键合质量和凸点31的倒装焊接质量，里面的镍镀层是作为扩散阻挡层以防止由元素扩散-化学反应引起的过厚共晶化合物的生成，过厚的共晶化合物影响键合区域的可靠性，对于第二金属材料层23，外面的金镀层和中间的钯镀层是保证焊料在引线框架201的可浸润性，提高封装体在PCB等电路板上表面贴装的质量，里面的镍镀层是作为扩散阻挡层以防止由元素扩散-化学反应引起的过厚共晶化合物的生成，过厚的共晶化合物影响表面贴装焊接区域的可靠性。
请参照图5D，将薄板基材20的下表面20b上的掩膜材料层21b移除，在本实施例中的移除方法可以是化学反应方法和机械方法，化学反应方法是选用可溶性的碱性溶液，例如氢氧化钾(KOH)、氢氧化钠(NaOH)，采用喷淋等方式与薄板基材20的下表面20b上的掩膜材料层21b进行化学反应，将其溶解从而达到移除的效果，也可选择有机去膜液将掩膜材料层21b移除，移除掩膜材料层21b后，薄板基材20的下表面20b上仅剩下第二金属材料层23。
请参照图5E，以薄板基材20的下表面20b上的第二金属材料层23作为蚀刻的抗蚀层，采用喷淋方式对薄板基材20下表面20b进行选择性部分蚀刻，形成凹槽24和台阶式结构表面24a，蚀刻深度范围可以是占薄板基材20的厚度的40％-90％。在本实施例中，喷淋方式优先采用上喷淋方式，蚀刻液优先选择碱性蚀刻液，如碱性氯化铜蚀刻液、氯化铵等碱性蚀刻液，以减少蚀刻液对第二金属材料层23的破坏作用。
请参照图5F，在薄板基材20的下表面20b经选择性部分蚀刻形成的凹槽24中填充绝缘填充材料25，绝缘填充材料25具有表面25a，该表面与第二金属材料层表面23a处于同一水平面上。在本实施例中，绝缘填充材料25是热固性塑封材料、塞孔树脂、油墨以及阻焊绿油等绝缘材料，绝缘填充材料25具有足够的耐酸、耐碱性，以保证后续的工艺不会对已形成绝缘填充材料25造成破坏，绝缘填充材料25的填充方法是通过注塑或者丝网印刷等方法填充到凹槽24中，配置后用机械研磨方法或者化学处理方法去除过多的绝缘填充材料25，以消除绝缘填充材料25的溢料，使绝缘填充材料25的表面25a与第二金属材料层23a处于同一水平面上，对于感光型阻焊绿油等绝缘填充材料25，通过显影方法去除溢料。
请参照图5G，将薄板基材20的上表面20a上的掩膜材料层21a移除，在本实施例中的移除方法可以是化学反应方法和机械方法，化学反应方法是选用可溶性的碱性溶液，例如氢氧化钾(KOH)、氢氧化钠(NaOH)，采用喷淋等方式与薄板基材20的上表面20a上的掩膜材料层21a化学反应，将其溶解从而达到移除的效果，也可选择有机去膜液将掩膜材料层21a移除，移除掩膜材料层21a后，薄板基材20的上表面20a上仅剩下第一金属材料层22。
请参照图5H，以薄板基材20的上表面20a上的第一金属材料层22作为蚀刻的抗蚀层，采用喷淋方式对薄板基材20上表面20a进行选择性部分蚀刻，蚀刻至台阶式结构表面24a，暴露出绝缘填充材料25。形成引线框架201，引线框架201包括芯片载体202和围绕芯片载体202呈多圈排列的引脚203，引线框架201中配置有绝缘填充材料25，即芯片载体202和围绕芯片载体202呈多圈排列的引脚203通过绝缘填充材料25固定在一起。经选择性部分蚀刻后形成的分离的引脚203具有内引脚与外引脚，内引脚在后续的工艺中连接引线键合的IC芯片27的键合焊盘、具有凸点的IC芯片30的凸点31，外引脚作为连接外部电路的通道。形成台阶式结构24b，台阶式结构24b具有台阶式结构表面24a。在本实施例中，蚀刻液的喷淋方式优先采用上喷淋方式，蚀刻液优先选择碱性蚀刻液，如碱性氯化铜蚀刻液、氯化铵等碱性蚀刻液，以减少蚀刻液对第一金属材料层22的破坏作用。
请参照图5I，通过粘贴材料26将引线键合的IC芯片27配置于引线框架上表面20a的第一金属材料层22位置，且固定于芯片载体202的中央部位，在本实施例中，粘贴材料26可以是粘片胶带、含银颗粒的环氧树脂等导热材料。
请参照图5J，引线键合的IC芯片27上的多个键合焊盘通过金属导线28连接至多个配置有第一金属材料层22的内引脚上，以实现电气互联，在本实施例中，金属导线28是金线、铝线、铜线以及镀钯铜线等。
请参照图5K，采用注塑方法，通过塑封材料29包覆引线键合的IC芯片27、粘贴材料26、金属导线28、引线框架201的部分区域和第一金属材料层22，形成QFN封装形式的内封装。在本实施例中，塑封材料29可以是热固性聚合物等材料，所填充的绝缘填充材料25具有与塑封材料29相似的物理性质，例如热膨胀系数，以减少由热失配引起的产品失效，提高产品的可靠性，绝缘填充材料25与塑封材料29可以是同一种材料。塑封后进行烘烤后固化，塑封材料29和绝缘填充材料25与具有台阶式结构24b的引线框架201具有相互锁定功能，可以有效防止引线框架201与塑封材料29和绝缘填充材料25的分层以及引脚203或芯片载体202的脱落，而且有效阻止湿气沿着引线框架201与塑封材料29和绝缘填充材料25的结合界面扩散到封装体内部，提高了封装体的可靠性。
请参照图5L，具有凸点的IC芯片30通过倒装上芯设备配置于引脚203的内引脚上，且通过粘片材料26配置于第一次塑封后的封装件上，IC芯片30上的凸点31通过回流焊或者热压焊与多圈引脚203的内引脚连接，以实现电气互联。在本实施例中，IC芯片上凸点为无铅焊料凸点、含铅焊料凸点或者金属凸点。
请参照图5M，采用注塑方法，通过环保型塑封材料29包覆具有凸点的IC芯片27、凸点31、第一次塑封后的封装件、粘贴材料26和具有第一金属材料层22的多个引脚203，形成半导体封装中封装(PiP)系统结构200产品阵列。。在本实施例中，具有凸点的IC芯片30上的凸点31呈单圈排列，且分别焊接配置于呈三圈排列引脚203的最外圈，塑封材料29可以是热固性聚合物等材料，所填充的绝缘填充材料25具有与塑封材料29相似的物理性质，例如热膨胀系数，以减少由热失配引起的产品失效，提高产品的可靠性。形成半导体封装中封装(PiP)系统结构200产品阵列后，对产品阵列进行激光打印。
请参照图5N，切割半导体封装中封装(PiP)系统结构200产品阵列，彻底切割分离塑封材料29和绝缘填充材料25，形成单个半导体封装中封装(PiP)系统结构200。在本实施例中，单个产品分离方法是刀片切割、激光切割或者水刀切割等方法，且仅切割塑封材料29和绝缘填充材料25，不切割引线框架金属材料，图5N中仅绘制出切割分离后的2个半导体封装中封装(PiP)系统结构200产品阵列。
对本发明的实施例的描述是出于有效说明和描述本发明的目的，并非用以限定本发明，任何所属本领域的技术人员应当理解：在不脱离本发明的发明构思和范围的条件下，可对上述实施例进行变化。故本发明并不限定于所披露的具体实施例，而是覆盖权利要求所定义的本发明的实质和范围内的修改。

Claims (3)

1.一种半导体封装中封装系统的制造方法，所述的半导体封装中封装系统包括：
引线框架，沿厚度方向具有台阶式结构，具有上表面、下表面和台阶表面，其中引线框架包括芯片载体、多个引脚：
芯片载体，配置于引线框架中央部位，芯片载体四边边缘部位沿厚度方向具有台阶式结构，以及
多个引脚，配置于芯片载体四周，围绕芯片载体呈多圈排列，沿厚度方向具有台阶式结构，其中每个引脚包括配置于该上表面的内引脚和配置于该下表面的外引脚；
第一金属材料层，配置于引线框架的上表面位置；
第二金属材料层，配置于引线框架的下表面位置；
引线键合的IC芯片，通过粘贴材料配置于引线框架上表面位置的第一金属材料层上，且配置于芯片载体的中央部位；
具有凸点的IC芯片，通过倒装焊接配置于具有第一金属材料层的多个引脚的内引脚上；
引线键合的IC芯片配置于具有凸点的IC芯片与引线框架之间；
绝缘填充材料，配置于引线框架的台阶式结构下；
金属导线，引线键合的IC芯片上的多个键合焊盘通过金属导线分别连接至配置有第一金属材料层的多个引脚的内引脚；
塑封材料，包覆引线键合的IC芯片、具有凸点的IC芯片、粘贴材料、引线框架和第一金属材料层，
其特征在于包括：
配置掩膜材料层，在薄板基材的上表面和下表面配置具有窗口的掩膜材料层图形；
配置第一金属材料层和第二金属材料层，在配置于薄板基材上表面和下表面的掩膜材料层的窗口中分别配置第一金属材料层和第二金属材料层；
下表面选择性部分蚀刻，移除薄板基材下表面的掩膜材料层，以第二金属材料层为抗蚀层，对薄板基材下表面进行选择性部分蚀刻，形成凹槽；
配置绝缘填充材料，在薄板基材下表面经选择性部分蚀刻形成的凹槽中填充绝缘材料；
上表面选择性部分蚀刻，移除薄板基材上表面的掩膜材料层，以第一金属材料层为阻蚀层，对薄板基材上表面进行选择性部分蚀刻，形成具有台阶式结构的引线框架，包括分离的芯片载体和多圈引脚；
配置引线键合的IC芯片，通过粘贴材料将引线键合的IC芯片配置于引线框架上表面位置的第一金属材料层上，且配置于芯片载体的中央部位；
金属导线键合连接，引线键合的IC芯片上的多个键合焊盘通过金属导线分别连接至配置有第一金属材料层的多个引脚的内引脚；
第一次塑封，用塑封材料包覆引线键合的IC芯片、粘贴材料、金属导线、芯片载体和具有第一金属材料层的多个引脚，形成封装件；
配置具有凸点的IC芯片，通过倒装上芯设备将具有凸点的IC芯片倒装焊接配置于具有第一金属材料层的多个引脚的内引脚上，通过回流焊或者热压焊实现凸点与多个引脚的内引脚相连，具有凸点的IC芯片通过粘贴材料配置于第一次塑封后的封装件上；
第二次塑封，用塑封材料包覆具有凸点的IC芯片、凸点、第一次塑封后的封装件、粘贴材料和具有第一金属材料层的多个引脚，形成产品阵列；
切割分离形成单个封装系统，切割分离形成独立的单个封装系统。
2.根据权利要求1所述的方法，其特征在于，半导体封装中封装系统通过两次塑封工艺形成。
3.根据权利要求1所述的方法，其特征在于，切割分离形成单个封装系统，是用刀片切割、激光切割或者水刀切割方法切割，且仅切割塑封材料和绝缘填充材料。
CN201110456464XA 2011-12-30 2011-12-30 一种半导体封装中封装系统结构及制造方法 Expired - Fee Related CN102446882B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201110456464XA CN102446882B (zh) 2011-12-30 2011-12-30 一种半导体封装中封装系统结构及制造方法
US14/354,583 US9397068B2 (en) 2011-12-30 2012-12-04 Package in package (PiP) electronic device and manufacturing method thereof
PCT/CN2012/085785 WO2013097581A1 (zh) 2011-12-30 2012-12-04 一种半导体封装中封装系统结构及制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201110456464XA CN102446882B (zh) 2011-12-30 2011-12-30 一种半导体封装中封装系统结构及制造方法

Publications (2)

Publication Number Publication Date
CN102446882A CN102446882A (zh) 2012-05-09
CN102446882B true CN102446882B (zh) 2013-12-04

Family

ID=46009248

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110456464XA Expired - Fee Related CN102446882B (zh) 2011-12-30 2011-12-30 一种半导体封装中封装系统结构及制造方法

Country Status (3)

Country Link
US (1) US9397068B2 (zh)
CN (1) CN102446882B (zh)
WO (1) WO2013097581A1 (zh)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102446882B (zh) 2011-12-30 2013-12-04 北京工业大学 一种半导体封装中封装系统结构及制造方法
CN102738015A (zh) * 2012-06-05 2012-10-17 华天科技（西安）有限公司 一种基于腐蚀、喷砂的aaqfn产品的二次塑封制作工艺
CN103021890B (zh) * 2012-12-17 2016-06-29 北京工业大学 一种qfn封装器件的制造方法
CN103050419A (zh) * 2012-12-17 2013-04-17 北京工业大学 具有多圈引脚排列的qfn的制造方法
CN103021876B (zh) * 2012-12-17 2016-06-01 北京工业大学 一种高密度qfn封装器件的制造方法
CN103489792B (zh) * 2013-08-06 2016-02-03 江苏长电科技股份有限公司 先封后蚀三维系统级芯片倒装封装结构及工艺方法
CN104681544A (zh) * 2013-12-03 2015-06-03 上海北京大学微电子研究院 多芯片qfn封装结构
US9704772B2 (en) 2014-04-02 2017-07-11 Xintec Inc. Chip package and method for forming the same
TWI588954B (zh) * 2015-02-16 2017-06-21 精材科技股份有限公司 晶片封裝體及其製造方法
US20160307799A1 (en) * 2015-04-15 2016-10-20 Advanced Semiconductor Engineering, Inc. Semiconductor substrates, semiconductor packages and processes of making the same
CN106935565A (zh) * 2015-12-31 2017-07-07 无锡华润安盛科技有限公司 高密度qfn封装体及其制备方法
JP6593842B2 (ja) * 2016-03-16 2019-10-23 大口マテリアル株式会社 Ｌｅｄパッケージ並びに多列型ｌｅｄ用リードフレーム及びその製造方法
JP6537144B2 (ja) * 2016-03-16 2019-07-03 大口マテリアル株式会社 多列型リードフレーム及びその製造方法
JP6593841B2 (ja) * 2016-03-16 2019-10-23 大口マテリアル株式会社 Ｌｅｄパッケージ並びに多列型ｌｅｄ用リードフレーム及びその製造方法
US10707157B2 (en) * 2016-06-15 2020-07-07 Advanced Semiconductor Engineering, Inc. Semiconductor device package
US20200161206A1 (en) * 2018-11-20 2020-05-21 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process
US11450596B2 (en) * 2019-11-22 2022-09-20 Advanced Semiconductor Engineering, Inc. Lead frame, package structure and method for manufacturing the same
TWI736409B (zh) * 2020-03-27 2021-08-11 美商矽成積體電路股份有限公司 封裝結構
US20240006278A1 (en) * 2022-07-01 2024-01-04 Mediatek Inc. Multi-die qfn hybrid package
CN116364686A (zh) * 2023-04-03 2023-06-30 深圳市鑫宇微科技有限公司 引线框架和单相模块

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102231376A (zh) * 2011-06-30 2011-11-02 天水华天科技股份有限公司 多圈排列无载体双ic芯片封装件及其生产方法
CN202384324U (zh) * 2011-12-30 2012-08-15 北京工业大学 一种半导体封装中封装系统结构

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6258626B1 (en) * 2000-07-06 2001-07-10 Advanced Semiconductor Engineering, Inc. Method of making stacked chip package
KR100747996B1 (ko) * 2001-03-26 2007-08-08 앰코 테크놀로지 코리아 주식회사 반도체 패키지
US6613606B1 (en) * 2001-09-17 2003-09-02 Magic Corporation Structure of high performance combo chip and processing method
US7535110B2 (en) 2006-06-15 2009-05-19 Marvell World Trade Ltd. Stack die packages
CN102222657B (zh) * 2011-06-30 2013-12-04 天水华天科技股份有限公司 多圈排列双ic芯片封装件及其生产方法
CN102446882B (zh) 2011-12-30 2013-12-04 北京工业大学 一种半导体封装中封装系统结构及制造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102231376A (zh) * 2011-06-30 2011-11-02 天水华天科技股份有限公司 多圈排列无载体双ic芯片封装件及其生产方法
CN202384324U (zh) * 2011-12-30 2012-08-15 北京工业大学 一种半导体封装中封装系统结构

Also Published As

Publication number Publication date
WO2013097581A1 (zh) 2013-07-04
CN102446882A (zh) 2012-05-09
US9397068B2 (en) 2016-07-19
US20150348934A1 (en) 2015-12-03

Similar Documents

Publication Publication Date Title
CN102446882B (zh) 一种半导体封装中封装系统结构及制造方法
CN102543937B (zh) 一种芯片上倒装芯片封装及制造方法
CN102543907B (zh) 一种热增强型四边扁平无引脚倒装芯片封装及制造方法
CN102354691B (zh) 一种高密度四边扁平无引脚封装及制造方法
CN102339809B (zh) 一种多圈引脚排列四边扁平无引脚封装及制造方法
CN102456677B (zh) 球栅阵列封装结构及其制造方法
CN103474406A (zh) 一种aaqfn框架产品无铜扁平封装件及其制作工艺
KR20120079325A (ko) 반도체 패키지 및 그 제조방법
CN102354689B (zh) 一种面阵引脚排列四边扁平无引脚封装及制造方法
CN103021890A (zh) 一种qfn封装器件的制造方法
CN102420205B (zh) 一种四边扁平无引脚封装的制造方法
CN103887256A (zh) 一种高散热芯片嵌入式电磁屏蔽封装结构及其制作方法
CN103165475B (zh) 一种半导体封装器件的制造方法
CN102522394A (zh) 一种芯片上芯片封装及制造方法
CN103021876B (zh) 一种高密度qfn封装器件的制造方法
CN202633291U (zh) 一种芯片上芯片封装结构
CN103065975B (zh) 一种再布线qfn封装器件的制造方法
CN202384324U (zh) 一种半导体封装中封装系统结构
CN103050452B (zh) 一种再布线高密度aaqfn封装器件及其制造方法
CN202495438U (zh) 一种热增强型四边扁平无引脚倒装芯片封装
JP6290987B2 (ja) 半導体パッケージ基板及びその製造方法
CN202275815U (zh) 一种高密度四边扁平无引脚封装
CN202495443U (zh) 一种芯片上倒装芯片封装
CN203787410U (zh) 一种高散热芯片嵌入式电磁屏蔽封装结构
CN202996820U (zh) 一种再布线qfn封装器件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20131204

Termination date: 20161230