WO2013097581A1 - 一种半导体封装中封装系统结构及制造方法 - Google Patents

一种半导体封装中封装系统结构及制造方法 Download PDF

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Publication number
WO2013097581A1
WO2013097581A1 PCT/CN2012/085785 CN2012085785W WO2013097581A1 WO 2013097581 A1 WO2013097581 A1 WO 2013097581A1 CN 2012085785 W CN2012085785 W CN 2012085785W WO 2013097581 A1 WO2013097581 A1 WO 2013097581A1
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Prior art keywords
chip
material layer
package
disposed
lead frame
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PCT/CN2012/085785
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English (en)
French (fr)
Inventor
秦飞
夏国峰
安彤
武伟
刘程艳
朱文辉
Original Assignee
北京工业大学
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Application filed by 北京工业大学 filed Critical 北京工业大学
Priority to US14/354,583 priority Critical patent/US9397068B2/en
Publication of WO2013097581A1 publication Critical patent/WO2013097581A1/zh

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
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Definitions

  • the present invention relates to the field of semiconductor component manufacturing technology, and more particularly to a package in package (PiP) system structure based on a QFN package, and a method of manufacturing the package.
  • SiP package in package
  • FIG. 1A and FIG. 1B are respectively a schematic rear view and a cross-sectional view of a conventional QFN package structure including a lead frame 11, a molding material 12, a bonding material 13, a C chip 14, a metal wire 15, wherein the lead frame 11 includes a chip carrier 111 and pins 112 arranged around the periphery of the chip carrier 111.
  • the IC chip i4 is fixed on the chip carrier 111 by the adhesive material 13, and the IC chip 13 is electrically connected to the surrounding pins 112 through the metal wires 15.
  • the molding material 12 encapsulates the IC chip 14, the metal wire 15 and the lead frame 11 for protection and support.
  • the pin U2 is exposed on the bottom surface of the molding material i2, and is soldered to a circuit board such as a PCB to realize the external environment. Electrical connection.
  • the bare chip carrier 111 on the bottom surface is soldered to a circuit board such as a PCB, and has a direct heat dissipation channel, which can effectively release the heat generated by the C chip.
  • the QFN package does not have gull-wing leads, short conductive paths, low self-inductance coefficient and low impedance, and provides good electrical performance to meet high-speed or chopping ffi.
  • the exposed chip carrier provides excellent thermal performance.
  • the traditional two-dimensional planar package As IC integration increases and functions continue to increase, the number of IC I/Os increases, and the number of I/O pins in the corresponding electronic package increases accordingly, and is gradually reduced by the traditional two-dimensional planar package.
  • the highly integrated dimensional three-dimensional package form is developed.
  • the traditional four-sided flat leadless package is a typical two-dimensional planar package.
  • the single-turn pins are arranged around the chip carrier, which limits the increase of the number of I/Os. There is no need for high-density ICs with more I/O counts.
  • the traditional lead frame has a stepless structure design, which cannot effectively lock the plastic material, resulting in low bonding strength between the lead frame and the molding material, and is easy to cause delamination of the lead frame and the molding material or even pins or cores;
  • the moisture cannot be effectively prevented from diffusing into the interior of the electronic package along the bonding interface of the lead frame and the molding material, thereby seriously affecting the reliability of the package.
  • the plastic sealing process needs to be pre-applied to the back of the lead frame to prevent the phenomenon of flashing. After the plastic sealing, the cleaning process such as removing the tape and the plastic material flashing edge is required, which increases the packaging cost.
  • the cutting blade will cut the lead frame metal while cutting the molding material, which will not only reduce the cutting efficiency and shorten the life of the cutting blade, but also produce metal burrs. , affecting the reliability of the package. Therefore, in order to break through the low threshold of traditional QFN: the bottleneck of I/O quantity, improve the reliability of package and reduce the cost of packaging, it is urgent to develop a high reliability, low cost, high I/O density dimension package based on QFN package. Structure and its manufacturing method.
  • the invention provides a package in package (PiP) system structure and a manufacturing method thereof in a base QFN package, so as to overcome the bottleneck of the low I/O quantity of the traditional QFN and improve the reliability of the package. .
  • the present invention adopts the following technical solution - the present invention provides a semiconductor package-in-package (PiP) system structure including a lead frame, a first metal material layer, a second metal material layer, and an iC chip having bumps , I-bonded IC chip, metal wire, insulating filler material, adhesive material and plastic sealing material.
  • the lead frame has a stepped structure in the thickness direction, and has an upper surface, a T surface, and a stepped surface.
  • the lead frame includes a chip carrier and a plurality of chests arranged in a plurality of circles around the chip carrier.
  • the chip carrier is disposed at a central portion of the lead frame, and the four edge portions of the chip carrier have a stepped structure along the thickness direction.
  • the pins arranged in a plurality of turns around the chip carrier have a circular or rectangular cross-sectional shape, wherein each of the pins includes an inner pin disposed on the upper surface and an outer pin disposed on the surface of the T.
  • the first metal material layer and the second metal material layer are respectively disposed at an upper surface position and a lower surface position of the lead frame.
  • the edge fill material is disposed under the stepped hook of the lead frame to support and protect the lead frame to expose the second metal compound layer disposed on the lower surface of the lead frame.
  • the wire-bonded IC chip is disposed on the first metal material layer at the upper surface position of the lead frame through the adhesive sheet, and is disposed at a central portion of the chip carrier, and the plurality of bonding pads on the wire-bonded IC chip pass through
  • the metal wires are respectively connected to the inner pins of the plurality of pins configured with the first metal material layer, and the molding material covers the wire bonding: C chip, adhesive material, metal wire, chip carrier and layer having the first metal material Multiple chests are formed to form a package.
  • Bump with bump The chip is placed on the inner lead of a plurality of pins with a metal material layer by flip-chip device, and the bump on the IC chip is reflowed or thermocompressed with the inside of the multi-turn pin Pin-connected, IC chip with bumps is disposed on the first molded package by adhesive material, and the molding material is covered with bumps: C chip, bump, package after the first molding, paste The material and the plurality of chests having the first layer of metallic material form an array of products.
  • a package ( PlP ) system structure in a semiconductor package includes two packages.
  • the leadframe has a plurality of pins arranged in a circle around the chip carrier.
  • the chip including the chip carrier and the pins arranged around the chip carrier have a stepped structure.
  • the cross-sectional shape of the arches arranged in three turns around the chip carrier has a circular shape.
  • the cross-sectional shape of the lead around the core; t-carrier is a rectangular shape.
  • the pin arrangement on each side of the chip carrier is arranged in parallel.
  • the pin arrangement on each side of the core i ⁇ carrier is a staggered array.
  • the upper surface and the lower surface of the lead frame are respectively provided with a first metal material layer and a second metal material layer.
  • the first metal material layer and the second metal material layer respectively disposed on the upper surface and the lower surface of the bow wire frame include a nickel (Pur), palladium (Pd), gold (Au) metal material.
  • the IC chip with bumps is flip-chip soldered to the inner leads of the plurality of pins having the first metal material layer by flip-chip device, and the bumps on the IC chip pass through the reflow Solder or thermocompression bonding to the internal pins of multiple pins.
  • the wire-bonded IC chip is disposed on the chip carrier by a thermally conductive adhesive material, and the bumped IC chip is disposed on the first molded package.
  • a wire bonded IC chip package has two turns of pins arranged.
  • the bumps on the IC core j with the bumps are arranged in a single turn, and the turns are respectively welded to the outermost rings of the pins arranged in three turns.
  • the bumps on the IC chip are lead-free solder bumps, lead-containing solder bumps, or metal bumps.
  • the wire bonded chip is disposed between the C chip having a bump and the lead frame.
  • an insulating filler material is disposed under the lead frame stepped structure.
  • the type of insulating filler material disposed under the stepped structure of the bow line frame is a thermosetting plastic seal material, or a material such as a plug resin, an ink, and a barrier green oil.
  • the present invention provides a method of fabricating a package (P) system structure in a semiconductor package, comprising the following steps - step h: arranging a mask material layer
  • the thin plate base is cleaned and pretreated, and a mask having a window is disposed on the upper surface and the lower surface of the thin plate substrate
  • the first metal material layer and the second metal material layer are disposed in the windows of the mask material layer disposed on the upper surface and the lower surface of the thin plate substrate, respectively.
  • Step 3 Selective partial etching of the lower surface
  • the mask material layer on the lower surface of the thin plate substrate is removed, and the second metal material layer is used as an anti-mite layer, and the lower surface of the thin plate substrate is selectively partially etched to form a groove.
  • Step 4 Configure the insulation filler
  • a portion of the recess formed by selective semi-etching under the sheet substrate is filled with an insulating material.
  • Step 5 Selective partial etching of the upper surface
  • Step 6 Configure the wire bonding K: chip
  • the wire-bonded IC core j ⁇ is placed in the center of the chip carrier by a thermally conductive adhesive material such as an epoxy resin containing silver particles or a tape.
  • a plurality of bonding pads on the wire-bonded IC chip are respectively connected to the inner pins of the plurality of pins provided with the first metal material layer through metal wires to achieve electrical interconnection.
  • Step 8 First plastic seal
  • a C-chip, a bonding material, a metal wire, a chip carrier, and a plurality of chests having a first metal material layer are covered by a molding material to form a package.
  • Step 9 Configure the IC chip with bumps
  • Flip-chip IC chip is flip-chip mounted on an inner pin of a plurality of pins having a first metal material layer by flip-chip device, and bumps and pins are realized by reflow soldering or thermocompression bonding The inner pins are connected, and the bumped 1C chip is disposed on the first molded package by a thermal adhesive material.
  • Step 10 The second plastic seal
  • An array of products is formed by coating a bumped IC chip, a first molded package, an adhesive material, and a plurality of leads having a first metal material layer with a molding material.
  • Step 12 Cutting the separated product
  • the separated products are cut to form a single, individual package system.
  • the first metal material layer and the second metal material are disposed by electroplating or electroless plating, according to an embodiment of the present invention, the first metal substrate layer and the second metal material layer are used as a resist layer, respectively Selective partial etching of the upper and lower surfaces of the sheet substrate.
  • the insulating filler material is disposed in the half-etching groove by screen printing or coating or the like.
  • the bumps on the ic chip are connected to the inner leads of the plurality of pins by reflow soldering or thermocompression bonding.
  • a package structure in a semiconductor package is formed by two molding processes.
  • the separation product is cut by a blade cutting, laser cutting or water jet cutting method, and only the molding material and the insulating filling material are cut, and the lead frame is not cut.
  • the package (Pff) system structure of the semiconductor package based on the conventional QFN package is a three-dimensional package, and the height can be controlled within 0.7 mm, and has high I/O density and integration, and the lead frame is
  • the stepped structure increases the bonding area with the molding material and the insulating filling material, and has the effect of locking the molding material and the insulating filling material, thereby effectively preventing the layering of the lead frame and the molding material and the insulating filling material, and the pin or chip carrier.
  • the falling off, effectively preventing the outer portion of the moisture package from diffusing to the inside, and the small-sized outer pin can effectively prevent the surface mount bridging phenomenon, and the first metal material layer and the lower surface of the lead frame are respectively disposed
  • the second metal material layer can effectively improve the wire bonding quality, the flip-chip bonding quality and the surface mount quality.
  • the single package system is only connected by the molding material and the insulating filler material, when the cutting product is cut by using a cutting blade, Cutting into the lead frame metal material, the plexus improves the cutting Rate, prolongs the life of the cutting knives, prevents the occurrence of metal burrs, and eliminates the process of attaching the adhesive film on the back of the lead frame before the plastic sealing in the traditional QFN packaging process, removing the film and the flash of the molding material after molding, and reducing the package. cost.
  • Figure IB is a schematic cross-sectional view along the cut surface in Figure 1A;
  • FIG. 2A is a schematic diagram showing the back side of a package ( ⁇ ) system hook in a semiconductor package in which the pin cross-section is circular and the pin arrangement on each side of the chip carrier is arranged in parallel according to an embodiment of the present invention - FIG.
  • a lead cross-section drawn according to an embodiment of the present invention is rectangular, and a chest arrangement on each side of the chip carrier is a rear view of a parallel packaged semiconductor package-in-package (PiP) system structure;
  • 3A is a rear schematic view of a package (PW) system structure in a semiconductor package in which the pin cross-section is circular and the pin arrangement on each side of the chip carrier is staggered according to an embodiment of the present invention
  • 3B is a schematic rear view of a semiconductor package-in-package (PiP) system structure in which the pin cross-section is rectangular and the pin arrangement on each side of the chip carrier is staggered according to an embodiment of the present invention
  • 4 is a cross-sectional view taken along line W of FIG. 2A-B and FIG. 2B according to an embodiment of the present invention
  • FIGS. 5A to 5N are diagrams showing a structure of a packaged PiP) system in a semiconductor package according to an embodiment of the present invention.
  • a schematic cross-sectional view of the manufacturing process, and all of the cross-sectional views are schematic cross-sectional views along the cross-section of FIG.
  • FIG. 2A is a semiconductor package package (P1P) in which the lead cross-section is medically shaped and the chest arrangement of each side of the chip carrier is parallel arranged in accordance with an embodiment of the present invention.
  • 2B is a rear schematic view of a semiconductor package-in-package (PiP) system structure in which the pin-outs are rectangular in cross-section and the pinouts on each side of the chip carrier are arranged in parallel, in accordance with the present invention.
  • PiP semiconductor package-in-package
  • the lead frame 201 of the package (PiP) system structures 200a and 200b in the semiconductor package includes a chip carrier 202 and pins 203 arranged in a plurality of circles around the chip carrier 202. Further, the arrangement of the leads 203 on each side of the chip carrier 202 is parallel, and a second metal material layer 23 is disposed on the lower surface of the lead frame 201, and an insulating filler 25 is disposed in the lead frame 201.
  • the pin cross-section in the semiconductor package (PiP) system structure of Fig. 2A is circular
  • the cross-section of the thoracic cross-section in the package (PiP) system structure of the semiconductor package of Fig. 2B is rectangular.
  • 3A is a rear schematic view of a package-in-package (PiP) system structure in which the pin cross-section is circular and the pin arrangement on each side of the chip carrier is staggered in accordance with an embodiment of the present invention.
  • 3B is a rear schematic view of a semiconductor package-in-package (PiP) system structure in which the pin cross-section is rectangular and the pin arrangement on each side of the chip carrier is staggered in accordance with an embodiment of the present invention.
  • the lead frame 201 of the package (PiP) system structures 200c and 200d in a semiconductor package includes a chip carrier 202 and a pin 203 that is arranged in a plurality of turns around the chip carrier 202.
  • the pins 203 on each side of the chip carrier 202 are arranged in a staggered manner.
  • a second metal material layer 23 is disposed on the lower surface of the lead frame 201, and an insulating filler 25 is disposed in the lead frame 201.
  • the lead cross-section in the semiconductor package (PiP) system structure of Fig. 3A is circular
  • the cross-section of the thoracic cross-section in the package (PiP) system structure of the semiconductor package of Fig. 3B is rectangular.
  • the package (PiP) system structure 200 includes a lead frame 201, a first metal material layer 22, and a second metal material layer 23, The insulating filler 25, the bonding material 26, the wire-bonded IC chip 27, the metal wires 28, the molding material 29, the IC core j 30 having bumps, and the bumps 31.
  • the package (PiP) system structure 200 includes a lead frame 201, a first metal material layer 22, and a second metal material layer 23, The insulating filler 25, the bonding material 26, the wire-bonded IC chip 27, the metal wires 28, the molding material 29, the IC core j 30 having bumps, and the bumps 31.
  • the lead frame 201 serves as a passage for conducting, dissipating, and connecting external circuits, having a stepped structure 24b in the thickness direction, having an upper surface 20a and a lower surface 20b with respect to the upper surface 20a, and a stepped structure. Step surface 24a of 24b.
  • the lead frame 201 includes a chip carrier 202 and pins 203 arranged in a plurality of turns around the chip carrier 202.
  • the chip carrier 202 and the leads 203 arranged in a plurality of turns around the chip carrier 202 have a stepped structure 24b.
  • the chip carrier 202 is disposed at a central portion of the lead frame 201, and the four edge portions of the chip carrier 202 have a stepped structure 24b in the thickness direction.
  • the plurality of pins 203 are disposed around the chip carrier 202, and are arranged in a plurality of circles around the core j ⁇ carrier 202, and have a step structure 24b in the thickness direction, and the cross-sectional shape thereof is circular or rectangular, wherein each of the pins 203 includes a configuration.
  • the first metal material layer 22 and the second metal material layer 23 are respectively disposed at positions of the upper surface 20a of the dry lead frame 201 and the lower surface 20b of the lead frame 201, and the first metal material layer 22 has the same size as the inner pins of the old 203.
  • the size, the second metal material layer 23 and the outer bow of the pin 203 have the same size.
  • the first metal village layer 22 has a metal material layer surface 22a
  • the second metal material layer 23 has a metal material layer surface 23a.
  • the insulating filling material 25 is disposed under the stepped structure 24 of the dry lead frame 20, and supports and protects the lead frame 201.
  • the insulating filling material 25 has an insulating filling material surface 25a, an insulating filling material surface 25a and a metal material layer.
  • the surface 23a is on the same level.
  • the wire bonding is carried out by a thermally conductive adhesive material 26 such as an epoxy resin containing silver particles or a thermal conductive adhesive material such as a tape.
  • the C chip 27 is disposed at a central portion of the dry chip carrier 202.
  • the molding material 29 is covered with a wire bond: a C chip 27, a bonding material 26, a metal wire 28, a chip carrier 202, and a plurality of pins 203 having a first metal material layer 22, forming a package.
  • the LED-bonded IC chip package has two rows of pins.
  • the IC chip 30 having bumps is disposed on the inner leads of the dry pins 203 through the flip chip device, and is disposed on the package after the second plastic package by the adhesive material 26, and the bumps 31 on the IC chip 30
  • the reflow soldering or thermo-compression bonding is connected to the inner lead of the multi-turn pin 203, and the molding material 29 encloses the IC chip 27 with bumps, the bump 31, the package after the first molding, the paste material 26 and
  • a plurality of leads 203 having a first layer of metal material 22 form an array of products in a semiconductor package (CPIP) system structure 200.
  • CPIP semiconductor package
  • the bumps 31 on the K: chip 30 having the bumps are arranged in a single turn, and are respectively soldered to the outer circumference of the pins 203 arranged in three turns.
  • a manufacturing process of a package (PiP) system structure in a semiconductor package will be described in detail below with reference to Figs. 5A to 5N.
  • 5A-5N are schematic cross-sectional views showing a manufacturing process of a packaged PiP) system structure in a semiconductor package according to an embodiment of the present invention, and all cross-sectional views are schematic cross-sectional views taken along the line of FIG.
  • a thin plate substrate 20 having an upper surface 20a and a lower surface 20b opposite to the upper surface 20a is provided.
  • the material of the thin plate substrate 20 may be copper, copper alloy, iron, iron alloy, nickel, nickel alloy, and the like. Metal material for the fraudulent lead frame.
  • the thickness of the thin plate substrate 20 is in the range of 0.1 mm 0.25 mmb, for example, 0. 27 mm, 0.152 mmb, 0.203 nmio, and the upper surface 20a and the lower surface 20b of the thin plate base 20 are cleaned and pretreated, for example, by plasma water to remove oil, dust. Etc., for the purpose of cleaning the upper surface 20a and the lower surface 20b of the thin plate substrate 20.
  • a mask material layer 21a and a mask material layer 2ib having windows are respectively disposed on the upper surface 2 (3 ⁇ 4 and the lower surface 20b of the thin plate base 20), and the window described herein means that there is no mask material.
  • the thin plate substrate 20 covered by the layer 2ia and the mask material layer 21b, the mask material layer 21a and the mask material layer 21b protect the thin plate substrate 20 covered by it, and the layer of the mask material will be layered in a later process step: Ha and the thin-plate base material 20 covered by the mask material layer 21b are etched.
  • a first metal material layer 22 having a first metal material layer surface 22a is disposed in a window of the mask material layer 21a disposed on the upper surface 20a of the thin plate substrate 20.
  • the second metal material layer 23 is disposed in the window of the masking layer 21b disposed on the T surface 20b of the thin plate substrate 20, and the second metal substrate layer 23 has the second metal material layer surface 23a.
  • the first metal material layer 22 and the second metal material layer 23 are disposed by electroplating, electroless plating, evaporation, sputtering, etc., and are allowed to be composed of different metal materials. In the present embodiment, electroplating or electroless plating is preferred.
  • the method of arranging the first metal material layer 22 and the second metal material layer 23 is smeared.
  • the material of the first metal material layer 22 and the second metal material layer 23 is a metal material such as nickel (Ni), palladium (Pd), gold ( ⁇ ), silver (Ag), tin, or the like, and in the present embodiment,
  • the first metal material layer 22 and the second metal material layer 23 are, for example, a nickel-palladium-gold plating layer, and for the dry metal material layer 22, the outer gold plating layer and the intermediate palladium plating layer ensure that the metal wires 28 are on the lead frame 201.
  • the quality of the wire bonding and the quality of the flip-chip soldering of the bump 3, the nickel plating inside is a diffusion barrier to prevent the formation of excessively thick eutectic compounds caused by elemental diffusion-chemical reactions, and the influence of excessively thick eutectic compounds.
  • the reliability of the bonding region, for the second metal material layer 23, the outer gold plating layer and the intermediate palladium plating layer ensure the wettability of the solder in the lead frame 201, and improve the surface mount quality of the package on a PCB or the like.
  • the nickel plating inside serves as a diffusion barrier to prevent the formation of excessively thick eutectic compounds caused by elemental diffusion-chemical reactions, and the excessively thick eutectic compounds affect the reliability of the surface mount soldering region.
  • the mask material layer 21b on the lower surface 20b of the thin plate substrate 20 is removed.
  • the removal method in this embodiment may be a chemical reaction method or a mechanical method, and the chemical reaction method is to select a soluble alkali.
  • a solution such as potassium hydroxide (KOH) or sodium hydroxide (NaOH) is chemically reacted with the mask material layer 2ib on the lower surface 20b of the thin plate substrate 20 by spraying or the like to dissolve it to achieve the shift.
  • the masking material layer 21b may be removed by removing the masking material. After the masking material layer 21b is removed, only the second metallic material layer 23 remains on the lower surface 20b of the thin-plate base 20.
  • the second metal material layer 23 on the lower surface 20b of the thin plate base 20 is used as an etching resist layer, and the lower surface 20b of the thin plate substrate 20 is selectively partially etched by a shower method to form a groove. 24 and the stepped structure surface 24a, the etching depth may range from 40% to 90% of the thickness of the thin plate substrate 20.
  • the spray method preferably uses the upper spray method, and the etching liquid preferentially selects an alkaline etching solution, such as an alkaline copper chloride engraving liquid, an alkaline etching solution such as ammonium chloride, to reduce the etching liquid pair. The destruction of the second metal material layer 23.
  • the recess 24 formed by selective partial etching on the lower surface 20b of the thin plate substrate 20 is filled with an insulating filler material 25 having a surface 25a which is at the surface 23a of the second metal material layer.
  • the insulating filling material 25 is an insulating material such as a thermosetting plastic sealing material, a plug resin, an ink, and a solder resist green oil.
  • the insulating filling material 25 has sufficient acid resistance and alkali resistance to ensure that the subsequent process is not correct.
  • the insulating filler material 25 has been formed to cause damage.
  • the filling method of the insulating filler material 25 is filled into the recess 24 by means of injection molding or screen printing, and after the configuration, excessive insulating filler material is removed by mechanical grinding or chemical treatment.
  • the surface 25a of the insulating filler 25 and the second metal material layer 23a are on the same level, and for the insulating filler 25 such as the photosensitive solder resist green oil, the flash is removed by the developing method. .
  • the mask material layer 21a on the upper surface 20a of the thin plate substrate 20 is removed.
  • the removal method in the present embodiment may be a chemical reaction method and a mechanical method, and the chemical reaction method is selected to be soluble.
  • An alkaline solution such as potassium hydroxide (KDH), sodium hydroxide (NaOH), spray, or the like, chemically reacts with the mask material layer 21a on the upper surface 20a of the thin plate substrate 20 to dissolve it
  • KDH potassium hydroxide
  • NaOH sodium hydroxide
  • spray or the like
  • the first metal substrate layer 22 on the upper surface 20a of the thin plate substrate 20 is used as an etching resist layer, and the upper surface 20a of the thin plate substrate 20 is selectively partially etched by a shower method, and etched to a step.
  • the structural surface 24a exposes the insulating filler material 25.
  • the lead frame 201 is formed.
  • the lead frame 201 includes a chip carrier 202 and a lead 203 wound in a plurality of turns around the chip carrier 202.
  • the lead frame 20 is provided with an insulating filling material 25, that is, the chip carrier 202 and the surrounding chip carrier 202.
  • the pins 203 arranged in a plurality of turns are fixed together by the insulating filling village material 25.
  • the separated lead 203 formed by selective partial etching has an inner lead and an outer lead, and the inner lead is connected to the bonding pad of the 1C chip 27 of the wire bonding in a subsequent process, and the iC chip having the bump The bump 3 of 30], the outer pin acts as a channel for connecting an external circuit.
  • the stepped structure 24b is formed, and the stepped structure 24b has a stepped structural surface 24a.
  • the spraying method of the etching liquid is preferentially sprayed on the fl, and the etching liquid preferentially selects an alkaline etching liquid, such as an alkaline copper chloride etching solution, an alkaline etching solution such as ammonium chloride, to reduce etching.
  • an alkaline etching liquid such as an alkaline copper chloride etching solution, an alkaline etching solution such as ammonium chloride
  • the wire-bonded 1C chip 27 is placed on the first metal material layer 22 of the lead frame upper surface 20a by the paste material 26, and is fixed to the central portion of the chip carrier 202.
  • the paste is pasted.
  • Material 26 - may be a thermally conductive material such as a tape adhesive tape or an epoxy resin containing silver particles.
  • a plurality of bonding pads on the wire-bonded IC chip 27 are connected to a plurality of inner pins configured with the first metal material layer 22 through metal wires 28 to achieve electrical interconnection, in this embodiment.
  • the metal wires 28 are gold wires, aluminum wires, copper wires, palladium-plated copper wires, and the like.
  • the wire-bonded IC chip 27, the bonding material 26, the metal wires 28, the partial regions of the lead frame 20, and the first metal material layer 22 are covered by the molding material 29 by an injection molding method to form a QFN package.
  • the molding material 29 may be a material such as a thermosetting polymer
  • the filled insulating filler material 25 has physical properties similar to those of the molding material 29, such as a coefficient of thermal expansion, to reduce product failure caused by thermal mismatch, and to improve The reliability of the product, the insulating filler material 25 and the molding material 29 may be the same material.
  • the post-baking curing is performed, and the plastic sealing material 29 and the insulating filling material 25 have a mutual locking function with the lead frame 201 having the stepped structure 24b, and the layering of the lead frame 201 and the molding material 29 and the insulating filling material 25 can be effectively prevented.
  • the pin 203 or the chip carrier 202 is detached, and effectively prevents moisture from diffusing along the bonding interface of the lead frame 201 and the molding compound 29 and the insulating filler 25 into the inside of the package, thereby improving the reliability of the package.
  • the IC chip 30 having bumps is disposed on the inner lead of the lead 203 through the flip-chip device, and is disposed on the package after the first molding by the adhesive material 26, and the IC chip 30 is disposed.
  • the upper bump 31 is connected to the inner pin of the multi-turn pin 203 by reflow soldering or thermocompression bonding to achieve electrical interconnection.
  • the bumps on the IC chip are lead-free solder bumps, lead-containing solder bumps or metal bumps.
  • an IC chip 27 having bumps, bumps 31, a package after the first molding, a bonding material 26, and a layer having the first metal material layer 22 are coated by an environmentally-friendly molding material 29 by an injection molding method.
  • a plurality of pins 203 form an array of products in a package (PiP) system structure in a semiconductor package.
  • the bumps 31 on the IC chip 30 having bumps are arranged in a single turn, and are respectively soldered and disposed on the outermost ring of the three-circle arrangement pin 203, and the molding material 29 may be a thermosetting polymer or the like.
  • the material, the filled insulating filler material 25 has physical properties similar to those of the molding material 29, such as thermal expansion factor, to reduce product failure caused by thermal mismatch and improve product reliability.
  • the product array is laser printed. Referring to FIG. 5N, an array of package (HP) system structures 200 in a semiconductor package is diced, and the encapsulation material 29 and the insulating fill material 25 are thoroughly diced to form a package (PiP) system structure 200 in a single semiconductor package.
  • the single product separation method is a blade cutting, laser cutting or water jet cutting method, and only the molding material 29 and the insulating filling material 25 are cut, and the lead frame metal material is not cut, and only the cutting separation is drawn in FIG.

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Abstract

本发明公开了一种半导体封装中封装系统结构及制造方法。本半导体封装中封装系统结构包括引线框架、第一金属材料层、第二金属材料层、具有凸点的IC芯片、引线键合的IC芯片、绝缘填充材料、粘贴材料和塑封材料。引线框架包括芯片载体和多个围绕芯片载体呈多圈排列的引脚。第一金属材料层和第二金属材料层分别配置于引线框架上表面和下表面。绝缘填充材料配置于引线框架的台阶式结构下。引线键合的IC芯片配置于芯片载体上。具有凸点的IC芯片的凸点倒装焊接配置于多圈引脚的内引脚上，通过塑封材料包覆具有凸点的IC芯片、引线键合的IC芯片形成半导体封装中封装系统结构。本发明是基于QFN封装的高可靠性、低成本、高I/O密度的三维封装结构及其制造方法。

Description

说明书 一种半导体封装中封装系统结构及制造方法 技术领域
本发明涉及半导体元器件制造技术领域，尤其涉及到基于 QFN封装的半导体封装中封 装 （Package in Package, PiP) 系统结构， 本发明还包括该封装件的制造方法。
背景技术
随着电子产品如手机、 笔记本电脑等朝着小型化， 便携式， 超薄化， 多媒体化以及满 足大众化所需要的低成本方向发展， 高密度、 高性能、 高可靠性和低成本的封装形式及其 组装技术得到了快速的发展。 与价格昂贵的 BGA等封装形式相比， 近年来快速发展的新 型封装技术， 即四边扁平无引胸 QFN (Quad Flat Non · lead Package)封装， 由于具有良好 的热性能和电性能、 尺寸小、 成本低以及高生产率等众多优点， 引发了微电子封装技术领 域的一场新的革命。
图 1A和图 IB分别为传统 QFN封装结构的背面示意图和沿 面的剖面示意图，该 QFN封装结构包括引线框架 11 , 塑封材料 12, 粘片材料 13, :C芯片 14， 金属导线 15, 其中引线框架 11包括芯片载体 111和围绕芯片载体 111四周排列的引脚 112， IC芯片 i4 通过粘片材料 13固定在芯片载体 111上， IC芯片 13与四周排列的引脚 112通过金属导线 15实现电气连接， 塑封材料 12对 IC芯片 14、 金属导线 15和引线框架 11进行包封以达 到保护和支撑的作用， 引脚 U2裸露在塑封材料 i2的底面， 通过焊料焊接在 PCB等电路 板上以实现与外界的电气连接。底面裸露的芯片载体 111通过焊料焊接在 PCB等电路板上， 具有直接散热通道， 可以有效释放】C芯片】 4产生的热量。 与传统的 TSOP和 SOIC封装 相比， QFN封装不具有鸥翼状引线， 导电路径短， 自感系数及阻抗低， 丛而可提供良好的 电性能， 可满足高速或者徼波的应 ffi。 裸露的芯片载体提供了卓越的散热性能。
随着 IC集成度的提高和功能的不断增强， IC的 I/O数随之增加， 相应的电子封装的 I/O引脚数也相应增加， 且逐渐由传统的二维平面封装形式 ^更高集成度的 维立体封装 形式发展， 传统的四边扁平无引脚封装件为典型的二维平面封装形式， 单圈的引脚围绕芯 片载体呈周边排列， 限制了 I/O数量的提高， 满足不了高密度、 具有更多 I/O数的 IC的需 要。 传统的引线框架无台阶式结构设计， 无法有效的锁住塑料材料， 导致引线框架与塑封 材料结合强度低， 易于引起引线框架与塑封材料的分层甚至引脚或芯； t载体的脱落， 而且 无法有效的阻止湿气沿着引线框架与塑封材料结合界面扩散到电子封装内部， 从而严重影 响了封装体的可靠性。 传统 QFN产品在塑封工艺^需要预先在引线框架背面粘贴胶带以 防止溢料现象， 待塑封后还需迸行去除胶带、 塑封料飞边等清洗工艺， 增加了封装成本增 高。 使用切割刀切割分离传统的四边扁平无引脚封装件， 切割刀在切割塑封材料的同时也 会切割到引线框架金属， 不仅会造成切割效率的降低和切割刀片寿命的缩短， 而且会产生 金属毛刺， 影响了封装体的可靠性。 因此， 为了突破传统 QFN的低: I/O数量的瓶颈， 提高 封装体的可靠性和降低封装成本， 急需研发一种基于 QFN封装的高可靠性、 低成本、 高 I/O密度的 维封装结构及其制造方法。
发明内容 本发明提供了一种基干 QFN封装的半导体封装中封装 （Package in Package, PiP) 系 统结构及其制造方法，以达到突破传统 QFN的低 I/O数量的瓶颈和提高封装体的可靠性的 目的。
为了实现上述目的， 本发明采用下述技术方案- 本发明提出一种半导体封装中封装（PiP)系统结构， 包括引线框架、第一金属材料层、 第二金属材料层、 具有凸点的 iC芯片、 弓 I线键合的 IC芯片、 金属导线、 绝缘填充材料、 粘贴材料和塑封材料。 引线框架沿厚度方向具有台阶式结构， 具有上表面、 T表面和台阶 表面。 引线框架包括芯片载体和多个围绕芯片载体呈多圈排列的引胸。 芯片载体配置于引 线框架中央部位， 芯片载体四边边缘部位沿厚度方向具有台阶式结构。 绕芯片载体呈多 圈排列的引脚的橫截面形状呈圆形或者矩形状， 其中每个引脚包括配置于该上表面的内引 脚和配置于该 T表面的外引脚。 第一金属材料层和第二金属材料层分别配置于引线框架的 上表面位置和下表面位置。 缘填充材料配置于引线框架的台阶式结钩下， 支撑、 保护引线 框架， 暴露出配置于引线框架下表面的第二金属村料层。 引线键合的 IC芯片通过粘片村 料配置于引线框架上表面位置的第一金属材料层上， ϋ配置于芯片载体的中央部位， 引线 键合的 IC芯片上的多个键合焊盘通过金属导线分别连接至多个配置有第一金属材料层的 多个引脚的内引脚， 塑封材料包覆引线键合的: C芯片、 粘贴材料、 金属导线、 芯片载体 和具有第一金属材料层的多个引胸， 形成封装件。 具有凸点的 Κ:芯片通过倒装上芯设备 配置于具有金属材料层的多个引脚的内引脚上， IC芯片上的凸点通过回流焊或者热压焊 与多圈引脚的内引脚连接， 具有凸点的 IC芯片通过粘贴材料配置于第一次塑封后的封装 件上， 塑封材料包覆具有凸点的 :C芯片、 凸点、 第一次塑封后的封装件、 粘贴材料和具 有第一金属材料层的多个引胸， 形成产品阵列。
根据本发明的实施例， 半导体封装中封装 （PlP) 系统结构包括两个封装件。
根据本发明的实施倒， 引脚框架具有多个围绕芯片载体呈 圈排列的引脚。
根据本发明的实施例， 包括芯片载体和围绕芯片载体呈≡圈排列的引脚具有台阶式结 构。
根据本发明的实施倒， 围绕芯片载体呈三圈排列的弓 i脚的横截面形状呈圆形形状。 根据本发明的实施例， 围绕芯； t载体呈 Ξ:圈排列的引脚的橫截面形状呈矩形形状。 根据本发明的实施倒， 芯片载体每边的引脚排列方式为平行排列。
根据本发明的实施倒， 芯 i†载体每边的引脚排列方式为交错棑列。
根据本发明的实施例， 引线框架上表面和下表面分别配置有第一金属材料层和第二金 属材料层。
根据本发明的实施例， 弓 I线框架上表面和下表面分別配置的第一金属材料层和第二金 属材料层包括镍 (Νί)、 钯 (Pd)、 金 (Au)金属材料。
根据本发明的实施倒，通过倒装上芯设备将具有凸点的 IC芯片倒装焊接配置于具有第 一金属材料层的多个引脚的内引脚上， IC芯片上的凸点通过回流焊或者热压焊与多个引脚 的内引脚连接。
根据本发明的实施倒， 通过导热的粘贴材料将引线键合的 IC芯片配置于芯片载体上， 将具有凸点的 IC芯片配置于第一次塑封后的封装件上。 根据本发明的实施倒， 引线键合的 IC芯片封装件具有两圈排列的引脚。根据本发明的 实施例， 具有凸点的 IC芯 j†上的凸点呈单圈排列， ϋ分别焊接配置于呈三圈排列的引脚 的最外圈。
根据本发明的实施倒， IC芯片上凸点为无铅焊料凸点、 含铅焊料凸点或者金属凸点。 根据本发明的实施例，引线键合的 芯片配置于具有凸点的：C芯片与引线框架之间。 根据本发明的实施例， 引线框架台阶式结构下配置绝缘填充材料。
根据本发明的实施例， 弓 I线框架台阶式结构下配置绝缘填充材料种类是热固性塑封村 料， 或者塞孔树脂、 油墨以及阻悍绿油等材料。
本发明提出一种半导体封装中封装 （ P) 系统结构的制造方法， 包括以下歩骤- 步骤 h 配置掩膜材料层
对薄板基 进行清洗和预处理， 在薄板基材的上表面和下表面配置具有窗口的掩膜
" 步 s: 配置金属材料层
在配置于薄板基材上表面和下表面的掩膜材料层的窗口中分别配置第一金属材料层和 第二金属材料层。
步骤 3: 下表面选择性部分蚀刻
移除薄板基材下表面的掩膜材料层， 以第二金属材料层为抗饨层， 对薄板基材下表面 进行选择性部分饨刻， 形成凹槽。
步骤 4: 配置绝缘填充材料
在薄板基材下部分经选择性半饨刻形成的凹槽中填充绝缘材料。
步骤 5: 上表面选择性部分蚀刻
移除薄板基材上表面的掩膜材料层， 以第一金属材料层为阻蚀层， 对薄板基材上表面 进行选择性部分蚀刻，形成具有台阶式结构的引线框架，包括分离的芯片载体和多圈引脚。
步骤 6: 配置引线键合的 K:芯片
通过含银颗粒的环氧树脂树脂或者胶带等导热粘贴材料将引线键合的 IC 芯 j†配置于 芯片载体中央部位。
步骤 7: 引线键合连接
引线键合的 IC 芯片上的多个键合焊盘通过金属导线分别连接至配置有第一金属材料 层的多个引脚的内引脚， 以实现电气互联。
步骤 8: 第一次塑封
通过塑封材料包覆引线键合的】 C芯片、粘贴材料、 金属导线、 芯片载体和具有第一金 属材料层的多个引胸， 形成封装件。
歩骤 9: 配置具有凸点的 IC芯片
通过倒装上芯设备将具有凸点的 IC 芯片倒装焊接配置于具有第一金属材料层的多个 引脚的内引脚上， 通过回流焊或者热压焊实现凸点与多个引脚的内引脚相连， 具有凸点的 1C芯片通过导热粘贴材料配置于第一次塑封后的封装件上。
步骤 10: 第二次塑封
通过塑封材料包覆具有凸点的 IC芯片、第一次塑封后的封装件、粘贴材料和具有第一 金属材料层的多个引脚， 形成产品阵列。 歩骤 11 : 打印
对半导体封装中封装 （ΡιΡ) 系统结构的产品阵列进行激光打印。
步骤 12: 切割分离产品
切割分离产品， 形成独立的单个封装系统。
根据本发明的实施例， 通过电镀或者化学镀方法配置第一金属材料层和第二金属材料 根据本发明的实施例， 以第一金属村料层和第二金属材料层为抗蚀层， 分别对薄板基 材上表面和下表面选择性部分蚀刻。
根据本发明的实施例， 绝缘填充材料通过丝网印刷或者涂布等方法配置在半饨刻凹槽 中。
根据本发明的实施例， ic芯片上的凸点通过回流焊或者热压焊与多个引脚的内引脚连 接。
根据本发明的实施例， 半导体封装中封装 （ΡιΡ) 系统结构通过两次塑封工艺形成。 根据本发明的实施例， 选用刀片切割、 激光切割或者水刀切割等方法切割分离产品， 仅切割塑封材料和绝缘填充材料， 不切割引线框架。
基于上述， 根据本发明， 基于传统 QFN封装的半导体封装中封装 （Pff ) 系统结构为 ≡维立体封装， 高度可控制在 0.7毫米内， 具有较高的 I/O密度和集成度， 引线框架的台 阶式结构增加了与塑封材料和绝缘填充材料的结合面积， 具有与塑封材料和绝缘填充材料 相互锁定的效果， 能够有效防止引线框架与塑封材料和绝缘填充材料的分层以及引脚或芯 片载体的脱落， 有效阻止湿气 封装件结构外部向内部扩散， 小面积尺寸的外引脚能够有 效防止表面贴装 桥连现象的发生， 引线框架上表面和下表面分别配置的第一金属材料层 和第二金属材料层能够有效提高引线键合质量、 倒装焊接质量和表面贴装质量， 由于单个 封装系统之间仅由塑封材料和绝缘填充材料相连， 因此当使用切割刀切割分离产品， 不会 切割到引线框架金属材料， 丛而提高了切割效率， 延长了切割刀的寿命， 防止了金属毛刺 的产生， 同 省去了传统 QFN封装流程中的塑封前引线框架背面粘贴胶膜、 塑封后去除 胶膜和塑封料飞边等工艺， 降低了封装成本。
下文特举实施例， 并配合附图对本发明的上述特征和优点做详细说明。
Figure imgf000006_0001
图 IB为沿图 1A中的 割面的剖面示意图；
图 2A为根据本发明的实施^绘制的引脚横截面为圆形，且芯片载体每边的引脚排列方 式为平行排列的半导体封装中封装 （ΡΪΡ) 系统结钩的背面示意图- 图 2Β为根据本发明的实施例绘制的引脚横截面为矩形，且芯片载体每边的引胸排列方 式为平行排列的半导体封装中封装 （PiP) 系统结构的背面示意图；
图 3A为根据本发明的实施例绘制的引脚横截面为圆形，且芯片载体每边的引脚排列方 式为交错排列的半导体封装中封装 （Pff ) 系统结构的背面示意图；
图 3B为根据本发明的实施例绘制的引脚横截面为矩形，且芯片载体每边的引脚排列方 式为交错排列的半导体封装中封装 （PiP) 系统结构的背面示意图； 图 4为根据本发明的实施例绘制的，沿图 2A- B和图 中的 W 剖面的剖面示意图； 图 5A至图 5N为根据本发明的实施例绘制的半导体封装中封装 PiP) 系统结构的制 造流程剖面示意图， 所有剖面示意图都为沿图 4剖面所示的剖面示意图。
图中标号： 100,传统四边扁平无引脚封装结构， 11 ,引脚框架， 111.芯； t载体 U2.引脚, 12.塑封材料, 13.粘片材料， 14.IC芯片， 15.金属导线, 200、 200a> 200b, 200c > 200d.半 导体封装中封装 Q>iP) 系统结构， 201 ,引线框架， 202.芯片载体， 203.引胸， 20.薄板基材， 20a.薄板基材上表面、 引线框架上表面， 20b.薄板基材下表面、 引线框架下表面， 21a、 21b, 掩膜材料层， 22.第一金属材料层， 23.第二金属材料层， 22a,第一金属材料层表面， 23a.第 二金属材料层表面， 24.凹槽， 24a.台阶式结构表面， 241 台阶式结构， 25.绝缘填充村料， 25a.绝缘填充材料表面， 26.粘贴材料， 27.引线键合的 iC芯片， 28.金属导线， 29.塑封材料， 30,具有凸点的 IC芯片， 31.凸点。
具体实施方式
下面结合 i 图对本发明进行详细说明 - 图 2A为根据本发明的实施例绘制的引脚横截面为醫形，且芯片载体每边的引胸排列方 式为平行排列的半导体封装中封装 （P1P) 系统结构的背面示意图。 图 2B为根据本发明的 实施倒绘制的引脚横截面为矩形， 且芯片载体每边的引脚排列方式为平行排列的半导体封 装中封装 （PiP) 系统结构的背面示意图。
参照上述图 2A- B可以看出， 在本实施例中， 半导体封装中封装 （PiP) 系统结构 200a 和 200b的引线框架 201包括芯片载体 202和围绕芯片载体 202呈多圈排列的引脚 203，且 芯片载体 202每边的引脚 203的排列方式为平行排列， 在引线框架 201下表面配置有第二 金属材料层 23， 在引线框架 201中配置有绝缘填充材料 25。 不同之处在于图 2A的半导体 封装中封装（PiP )系统结构中的引脚横截面为圆形， 图 2B的半导体封装中封装（PiP )系 统结构中的引胸横截面为矩形。
图 3A为根据本发明的实施例绘制的引脚横截面为圆形，且芯片载体每边的引脚排列方 式为交错排列的半导体封装中封装 （PiP) 系统结构的背面示意图。 图 3B为根据本发明的 实施例绘制的引脚横截面为矩形， 且芯片载体每边的引脚排列方式为交错排列的半导体封 装中封装 （PiP) 系统结构的背面示意图。
参照上述图 3A- B可以看出， 在本实施飼中， 半导体封装中封装 （PiP) 系统结构 200c 和 200d的引线框架 201包括芯片载体 202和围绕芯片载体 202呈多圈棑列的引脚 203，且 芯片载体 202每边的引脚 203的排列方式为交错排列， 在引线框架 201下表面配置有第二 金属材料层 23 , 在引线框架 201中配置有绝缘填充材料 25。 不同之处在于图 3A的半导体 封装中封装（PiP)系统结构中的引脚横截面为圆形， 图 3B的半导体封装中封装（PiP )系 统结构中的引胸横截面为矩形。
图 4为根据本发明的实施例绘制的，沿图 2A-B和图 3A-B中的 I-I 剖面的剖面示意图。 结合图 2A- B、 图 3A- B, 参照图 4， 在本实施例中， 半导体封装中封装（PiP)系统结构 200 包括引线框架 201、 第一金属材料层 22、 第二金属材料层 23、 绝缘填充材料 25、 粘贴材 料 26、 引线键合的 IC芯片 27、 金属导线 28、 塑封材料 29、 具有凸点的 IC芯 j† 30和凸 点 31。 在图 4的实施飼中， 引线框架 201作为导电、 散热、 连接外部电路的通道， 沿厚度方 向具有台阶式结构 24b, 具有上表面 20a和相对于上表面 20a的下表面 20b， 以及台阶式结 构 24b的台阶表面 24a。 引线框架 201包括芯片载体 202和围绕芯片载体 202呈多圈排列 的引脚 203， 芯片载体 202和围绕芯片载体 202呈多圈排列的引脚 203都具有台阶式结构 24b。 芯片载体 202配置于引线框架 201中央部位， 芯片载体 202四边边缘部位沿厚度方 向具有台阶式结构 24b。 多个引脚 203配置于芯片载体 202四周， 围绕芯 j†载体 202呈多 圈排列， 沿厚度方向具有台阶结构 24b， 其横截面形状呈圆形或者矩形状， 其中每个引 脚 203包括配置于该上表面 20a的内引脚和配置于该下表面 20b的外引脚。
第一金属材料层 22和第二金属材料层 23分别配置干引线框架 201的上表面 20a位置 和引线框架 201的下表面 20b位置， 第一金属材料层 22与舊 203的內引脚具有相同尺 寸大小， 第二金属材料层 23与引脚 203的外弓 i脚具有相同尺寸大小。 第一金属村料层 22 具有金属材料层表面 22a, 第二金属材料层 23具有金属材料层表面 23a„
绝缘填充材料 25配置干引线框架 20〗 的台阶式结构 24下， 对引线框架 201起到支撑 和保护的诈 ^， 绝缘填充材料 25具有绝缘填充材料表面 25a， 绝缘填充材料表面 25a与金 属材料层表面 23a处于同一水平面上。
通过含银颗粒的环氧树脂树脂或者胶带等导热粘贴材料 26将引线键合的 : C芯片 27配 置干芯片载体 202的中央部位。 塑封材料 29包覆引线键合的 :C芯片 27、 粘贴材料 26、 金属导线 28、 芯片载体 202和具有第一金属材料层 22的多个引脚 203， 形成封装件。 在 本实施例中， 弓 I线键合的 IC芯片封装件具有两圈排列的引脚。 具有凸点的 IC芯片 30通 过倒装上芯设备配置干引脚 203的内引脚上， 且通过粘片材料 26配置于第 ·次塑封后的 封装件上， IC芯片 30上的凸点 31通过回流焊或者热压焊与多圈引脚 203的内引胸连接， 塑封材料 29包覆具有凸点的 IC芯片 27、 凸点 31、 第一次塑封后的封装件、 粘贴村料 26 和具有第一金属材料层 22的多个引脚 203 , 形成半导体封装中封装 CPIP) 系统结构 200 产品阵列。 在本实施例中， 具有凸点的 K:芯片 30上的凸点 31呈单圈排列， 且分别焊接 配置于呈三圈排列引脚 203的最夕卜圈。 下面将以图 5A至图 5N来详细说明一种半导体封装中封装 （PiP) 系统结构的制造流 程。
图 5A至图 5N为根据本发明的实施例绘制的半导体封装中封装 PiP) 系统结构的制 造流程剖面示意图， 所有剖面示意图都为沿图 4剖面所示的剖面示意图。
请参照图 5A, 提供具有上表面 20a和相对于上表面 20a的下表面 20b的薄板基材 20, 薄板基材 20 的材料可以是铜、 铜合金、 铁、 铁合金、 镍、 镍合金以及其他适用于制诈引 线框架的金属材料。薄板基材 20的厚度范围为 0.1mm 0.25mmb例如为 0. 27mm， 0.152mmb 0.203mnio对薄板基村 20的上表面 20a和下表面 20b迸行清洗和预处理， 例如用等离子水 去油污、 灰尘等， 以实现薄板基材 20的上表面 20a和下表面 20b清洁的目的。
请参照图 5B, 在薄板基村 20的上表面 2(¾和下表面 20b上分别配置具有窗口的掩膜材料 层 21a和掩膜材料层 2ib， 这里所述的窗口是指没有被掩膜材料层 2ia和掩膜材料层 21b覆盖 的薄板基材 20, 掩膜材料层 21a和掩膜材料层 21b保护被其覆盖的薄板基材 20, 在后面的工 艺步骤中将对被掩膜材料层: Ha和掩膜材料层 21b覆盖的薄板基材 20进行饨刻。 请参照图 5C, 在配置于薄板基材 20的上表面 20a上的掩膜材料层 21 a的窗口中配置 第一金属材料层 22，第一金属材料层 22具有第一金属材料层表面 22a，在配置于薄板基材 20的 T表面 20b上的掩膜村料层 21b的窗口中配置第二金属材料层 23 , 第二金属村料层 23具有第二金属材料层表面 23a。 第一金属材料层 22和第二金属材料层 23的配置方法为 电镀、 化学镀、 蒸发、 溅射等方法， 并且允许由不同的金属材料组成， 在本实施倒中， 优 先选择电镀或者化学镀诈为第一金属材料层 22和第二金属材料层 23的配置方法。 第一金 属材料层 22和第二金属材料层 23的 料是镍 (Ni)、 钯 (Pd)、 金 (Αιι)、 银 (Ag)、 锡 等金 属材料及其合金， 在本实施例中， 第一金属材料层 22和第二金属材料层 23例如是镍-钯- 金镀层， 对干第 ·金属材料层 22， 外面的金镀层和中间的钯镀层是保证金属导线 28在引 线框架 201上的引线键合质量和凸点 3 的倒装焊接质量， 里面的镍镀层是诈为扩散阻挡 层以防止由元素扩散-化学反应引起的过厚共晶化合物的生成，过厚的共晶化合物影响键合 区域的可靠性， 对于第二金属材料层 23， 外面的金镀层和中间的钯镀层是保证焊料在引线 框架 201的可浸润性，提高封装体在 PCB等电路板上表面贴装的质量， 里面的镍镀层是作 为扩散阻挡层以防止由元素扩散-化学反应引起的过厚共晶化合物的生成，过厚的共晶化合 物影响表面贴装焊接区域的可靠性。
请参照图 5D, 将薄板基材 20的下表面 20b上的掩膜材料层 21b移除， 在本实施例中 的移除方法可以是化学反应方法和机械方法， 化学反应方法是选用可溶性的碱性溶液， 如氢氧化钾 （KOH) 、 氢氧化钠 （NaOH) ， 采用喷淋等方式与薄板基材 20的下表面 20b 上的掩膜材料层 2ib迸行化学反应， 将其溶解从而达到移除的效果， 也可选择有 去膜液 将掩膜材料层 21b移除， 移除掩膜材料层 21 b后， 薄板基村 20的下表面 20b上仅剩下第 二金属材料层 23。
请参照图 5E,以薄板基村 20的下表面 20b上的第二金属材料层 23作为蚀刻的抗蚀层， 采用喷淋方式对薄板基材 20下表面 20b进行选择性部分蚀刻， 形成凹槽 24和台阶式结构 表面 24a， 蚀刻深度范围可以是占薄板基材 20的厚度的 40%- 90%。在本实施例中， 喷 ί#方 式优先采用上喷淋方式， 蚀刻液优先选择碱性蚀刻液， 如碱性氯化铜饨刻液、 氯化铵等碱 性蚀刻液， 以减少蚀刻液对第二金属材料层 23的破坏作用。
请参照图 5F, 在薄板基材 20的下表面 20b经选择性部分蚀刻形成的凹槽 24中填充绝 缘填充材料 25， 绝缘填充材料 25具有表面 25a, 该表面与第二金属材料层表面 23a处于同 一水平面上。 在本实施例中， 绝缘填充材料 25 是热固性塑封材料、 塞孔树脂、 油墨以及 阻焊绿油等绝缘材料， 绝缘填充材料 25 具有足够的耐酸、 耐碱性， 以保证后续的工艺不 会对已形成绝缘填充材料 25造成破坏， 绝缘填充材料 25的填充方法是通过注塑或者丝网 印刷等方法填充到凹槽 24 中， 配置后用机械研磨方法或者化学处理方法去除过多的绝缘 填充材料 25， 以消除绝缘填充材料 25的溢料， 使绝缘填充材料 25的表面 25a与第二金属 材料层 23a处于同一水平面上， 对于感光型阻焊绿油等绝缘填充材料 25， 通过显影方法去 除溢料。
请参照图 5G， 将薄板基材 20的上表面 20a上的掩膜材料层 21a移除， 在本实施倒中 的移除方法可以是化学反应方法和机械方法， 化学反应方法是选 ^可溶性的碱性溶液， 例 如氢氧化钾 （KDH) 、 氢氧化钠 （NaOH) , 采 ffl喷淋等方式与薄板基材 20的上表面 20a 上的掩膜材料层 21a化学反应， 将其溶解认而达到移除的效果， 也可选择有机去膜液将掩 膜材料层 21a移除， 移除掩膜村料层 21 a后， 薄板基村 20的上表面 20a上仅剩下第一金属 材料层 22。
请参照图 5H,以薄板基 20的上表面 20a上的第一金属村料层 22作为蚀刻的抗蚀层， 采用喷淋方式对薄板基材 20上表面 20a进行选择性部分蚀刻，蚀刻至台阶式结构表面 24a， 暴露出绝缘填充材料 25。 形成引线框架 201， 引线框架 201包括芯片载体 202和圈绕芯片 载体 202呈多圈棑列的引脚 203，引线框架 20: 中配置有绝缘填充材料 25，即芯片载体 202 和围绕芯片载体 202呈多圈排列的引脚 203通过绝缘填充村料 25固定在一起。 经选择性 部分蚀刻后形成的分离的引胸 203具有内引脚与外引脚， 内引脚在后续的工艺中连接引线 键合的 1C芯片 27的键合焊盘、具有凸点的 iC芯片 30的凸点 3】， 外引脚作为连接外部电 路的通道。形成台阶式结构 24b，台阶式结构 24b具有台阶式结构表面 24a。在本实施例中， 蚀刻液的喷淋方式优先采 ffl上喷淋方式， 蚀刻液优先选择碱性蚀刻液， 如碱性氯化铜蚀刻 液、 氯化铵等碱性蚀刻液， 以减少蚀刻液对第一金属材料层 22的破坏作用。
请参照图 5L通过粘贴村料 26将引线键合的 1C芯片 27配置于引线框架上表面 20a的 第一金属材料层 22位置， 且固定于芯片载体 202的中央部位， 在本实施例中， 粘贴材料 26 -可以是粘片胶带、 含银颗粒的环氧树脂等导热 料。
请参照图 5J,引线键合的 IC芯片 27上的多个键合焊盘通过金属导线 28连接至多个配 置有第一金属材料层 22的内引脚上， 以实现电气互联， 在本实施例中， 金属导线 28是金 线、 铝线、 铜线以及镀钯铜线等。
请参照图 5K, 采用注塑方法， 通过塑封材料 29包覆引线键合的 IC芯片 27、粘贴材料 26、 金属导线 28、 引线框架 20〗的部分区域和第一金属材料层 22, 形成 QFN封装形式的 内封装。 在本实施倒中， 塑封材料 29 可以是热固性聚合物等材料， 所填充的绝缘填充材 料 25具有与塑封材料 29相似的物理性质， 例如热膨胀系数， 以减少由热失配引起的产品 失效， 提高产品的可靠性， 绝缘填充材料 25与塑封材料 29可以是同一种材料。 塑封后进 行烘烤后固化， 塑封村料 29和绝缘填充材料 25与具有台阶式结构 24b的引线框架 201具 有相互锁定功能， 可以有效防止引线框架 201与塑封材料 29和绝缘填充材料 25的分层以 及引脚 203或芯片载体 202的脱落， 而且有效阻止湿气沿着引线框架 201 与塑封 料 29 和绝缘填充材料 25的结合界面扩散到封装体内部， 提高了封装体的可靠性。
请参照图 5L, 具有凸点的 IC芯片 30通过倒装上芯设备配置于引脚 203的内引胸上， ϋ通过粘片材料 26配置于第一次塑封后的封装件上， IC芯片 30上的凸点 31通过回流焊 或者热压焊与多圈引脚 203的内引脚连接， 以实现电气互联。 在本实施例中， IC芯片上凸 点为无铅悍料凸点、 含铅焊料凸点或者金属凸点。
请参照图 5Μ, 采用注塑方法， 通过环保型塑封材料 29包覆具有凸点的 IC芯片 27、 凸点 31、第一次塑封后的封装件、粘贴材料 26和具有第一金属材料层 22的多个引脚 203， 形成半导体封装中封装 （PiP) 系统结构 200产品阵列。 。 在本实施例中， 具有凸点的 IC 芯片 30上的凸点 31呈单圈排列， 旦分别焊接配置于呈：三圈排列引脚 203的最外圈， 塑封 材料 29可以是热固性聚合物等材料， 所填充的绝缘填充材料 25具有与塑封材料 29相似 的物理性质， 例如热膨账系数， 以减少由热失配引起的产品失效， 提高产品的可靠性。 形 成半导体封装中封装 （PiP) 系统结构 200产品阵列后， 对产品阵列进行激光打印。 请参照图 5N， 切割半导体封装中封装 （HP) 系统结构 200产品阵列， 彻底切割分离 塑封材料 29和绝缘填充材料 25， 形成单个半导体封装中封装 （PiP) 系统结构 200。 在本 实施倒中， 单个产品分离方法是刀片切割、 激光切割或者水刀切割等方法， ϋ仅切割塑封 材料 29和绝缘填充材料 25, 不切割引线框架金属材料， 图 5Ν中仅绘制出切割分离后的 2 个半导体封装中封装 （PiP) 系统结构 200产品阵列。
对本发明的实施例的描述是出于有效说明和描述本发明的目的，并非用以限定本发明, 任何所属本领域的技术人员应当理解： 在不脱离本发明的发明构思和范围的条件下， 可对 上述实施例进行变化。 故本发明并不限定于所披露的具体实施倒， 而是覆盖权利要求所定 义的本发明的实质和范围内的修改。

Claims

权利要求书
1、 一种半导体封装中封装系统结构， 其特征在于包括：
引线框架，沿厚度方向具有台阶式结构，具有上表面、下表面和台阶表面， 其中弓 [线框架包括芯片载体、 多个引脚：
芯片载体， 配置于引线框架中央部位， 芯片载体四边边缘部位沿厚度方向 具有台阶式结构， 以及
多个引脚， 配置于芯片载体四周， 围绕芯片载体呈多圈 列， 沿厚度方向 具有台阶式结构， 其中每个引脚包括配置于该上表面的内引脚和配置于该下 表面的外引脚；
第一金属村料层， 配置于引线框架的上表面位置；
第二金属村料层， 配置于引线框架的下表面位置；
引线键合的 IC芯片， 通过粘贴材料配置于引线框架上表面位置的第一金 属材料层上， 且配置于芯片载体的中央部位；
具有凸点的 IC芯片， 通过倒装焊接配置于具有第一金属材料层的多个引 脚的内引脚上；
引线键合的 IC芯片配置于具有凸点的 IC芯片与引线框架之间；绝缘填充 材料， 配置于引线框架的台阶式结构下；
金属导线， 引线键合的 IC芯片上的多个键合悍盘通过金属导线分别连接 至配置有第一金属材料层的多个引脚的内引脚；
塑封材料， 包覆引线键合的 IC芯片、 具有凸点的 IC芯片、 粘贴材料、 引 线框架和第一金属材料层， 形成封装件。
2、根据权利要求 i所述的一种半导体封装中封装系统结构， 其特征在于, 上述引线框架具有多个围绕芯片载体排列的引脚， 引脚横截面形状为圆形或 矩形， 排列圈数为单圈、 双圈、 三圈或三圈以上， 多圈引脚排列方式为平行 排列或交错排列。
3、根据权利要求 1所述的一种半导体封装中封装系统结构， 其特征在于， 具有凸点的 IC芯片上的凸点的排列方式为单圈、 双圈或三圈以上排列。
4、根据权利要求 1所述的一种半导体封装中封装系统结构， 其特征在于， 具有凸点的 IC芯片上的凸点为无铅焊料凸点、 含铅焊料凸点或者金属凸点。
5、 根据权利要求 1所述的一种半导体封装中封装系统结构的制造方法， 其特征在于包括：
配置掩膜材料层，在薄板基材的上表面和下表面配置具有窗口的掩膜材料 配置第一金属材料层和第二金属材料层，在配置于薄板基材上表面和下表 面的掩膜材料层的窗口中分别配置第一金属材料层和第二金属材料层；
下表面选择性部分蚀刻， 移除薄板基材下表面的掩膜材料层， 以第二金属 材料层为抗蚀层， 对薄板基材下表面进行选择性部分蚀刻， 形成凹槽；
配置绝缘填充材料，在薄板基村下表面经选择性部分蚀刻形成的凹槽中填 充绝缘材料；
上表面选择性部分蚀刻， 移除薄板基材上表面的掩膜材料层， 以第一金属 材料层为阻蚀层， 对薄板基材上表面进行选择性部分烛刻， 形成具有台阶式 结构的引线框架， 包括分离的芯片载体和多圈引脚；
配置引线键合的 IC芯片，通过粘贴材料将引线键合的 IC芯片配置于引线 框架上表面位置的第一金属材料层上， 且配置于芯片载体的中央部位；
金属导线键合连接， 引线键合的 IC芯片上的多个键合悍盘通过金属导线 分别连接至配置有第一金属材料层的多个引脚的内引脚；
第一次塑封， 用塑封材料包覆引线键合的 IC芯片、粘贴材料、 金属导线、 芯片载体和具有第一金属材料层的多个引脚， 形成封装件；
配置具有凸点的 IC芯片，通过倒装上芯设备将具有凸点的 IC芯片倒装焊 接配置于具有第一金属材料层的多个引脚的内引脚上， 通过回流焊或者热压 焊实现凸点与多个引脚的内引脚相连， 具有凸点的 IC芯片通过粘贴材料配置 于第一次塑封后的封装件上；
第二次塑封， 用塑封材料包覆具有凸点的 IC芯片、 凸点、 第一次塑封后 的封装件、 粘贴材料和具有第一金属材料层的多个引脚， 形成产品阵列； 切割分离形成单个封装系统， 切割分离形成独立的单个封装系统。
6、 根据权利要求 5所述的方法， 其特征在于， 半导体封装中封装系统结 构通过两次塑封工艺形成。
7、 根据权利要求 5所述的方法， 其特征在于， 切割分离形成单个封装件， 是用刀片切割、 激光切割或者水刀切割方法切割， 且仅切割塑封材料和绝缘 填充材料。
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