TWI553747B - 半導體裝置及形成穿孔的開口於覆晶疊合式封裝組件之底部基板中以減少填充材料的流出之方法 - Google Patents

半導體裝置及形成穿孔的開口於覆晶疊合式封裝組件之底部基板中以減少填充材料的流出之方法 Download PDF

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TWI553747B
TWI553747B TW100115013A TW100115013A TWI553747B TW I553747 B TWI553747 B TW I553747B TW 100115013 A TW100115013 A TW 100115013A TW 100115013 A TW100115013 A TW 100115013A TW I553747 B TWI553747 B TW I553747B
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substrate
semiconductor
semiconductor die
die
opening
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TW100115013A
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TW201203400A (en
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胡俊偉
李在學
譚琳
瞿文彬
馮玉鋒
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史達晶片有限公司
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Description

半導體裝置及形成穿孔的開口於覆晶疊合式封裝組件之底部基板中以減少填充材料的流出之方法
本發明大體上關於半導體裝置，且更特別地，關於一種半導體裝置及於覆晶疊合式封裝組件之底部基板中形成一穿孔開口以減少超額底部填充材料流出之方法。
半導體裝置通常係見於現代電子產品中。半導體裝置隨著電性元件之數量及密度而變。分立式半導體裝置大體上包含一種電性元件類型，例如，發光二極體(LED)、小訊號電晶體、電阻器、電容器、電感器或功率金屬氧化物半導體場效電晶體(MOSFET)。整合式半導體裝置典型地包含成千上萬的電性元件。整合式半導體裝置之範例包含微控制器、微處理器、電荷耦合裝置(CCD)、太陽電池及數位微型反射鏡裝置(DMD)。
半導體裝置執行例如高速計算、收發電磁波訊號、控制電子裝置、轉換太陽光成為電力和產生電視顯示器之視覺投影。半導體裝置係見於娛樂、通訊、電力轉換、網路、電腦及消費性產品領域中。半導體裝置也見於軍事應用、航空、汽車、工業控制及辦公室設備中。
半導體裝置利用半導體材料的電性特性。半導體材料之原子結構允許它的導電性受到施加電場或基極電流或透過摻雜製程來操縱。摻雜製程將雜質引入該半導體材料中以操縱並控制該半導體裝置之導電性。
一半導體裝置包含主動和被動電性結構。包含二極體及場效電晶體之主動結構控制電流之流動。藉由改變摻雜位準及施加一電場或基極電流，該電晶體不是增進就是壓制該電流流動。包含電阻器、電容器及電感器之被動結構建立執行各種電性功能所需之電壓及電流間之關係。該些主動及被動結構係電性連接以形成致能該半導體裝置來執行高速計算及格其它有用功能之電路。
半導體裝置大體上係使用例如前端製程及後端製程之二複雜製程來製造，每一個製程可能涉及成千上萬步驟。前端製程涉及在一半導體晶圓表面上形成複數個晶粒。每一個晶粒典型地係一模一樣且包含由電性連接主動及被動元件所形成之電路。後端製程涉及將來自已完成晶圓中之個別晶粒進行單粒化並封裝該晶粒以提供結構支撐及環境隔離。
半導體製程之一目標係製造更小的半導體裝置。較小的裝置典型地耗用較少電力，具有較高執行效率以及可更有效率地被製造。此外，較小的半導體裝置具有可期待用於更小終端產品之較小佔用空間。一較小晶粒尺寸可藉由改善該前端製程而產生具有較小且較高密度之主動及被動元件之晶粒而得。後端製程可藉由改善電性互連及封裝材料來產生具有較小佔用空間之半導體裝置封裝。
第1圖顯示一傳統覆晶疊合式封裝結構10。一覆晶型半導體晶粒12係安裝至具有凸塊16之基板14。例如環氧樹脂之底部填充材料18係沉積於半導體晶粒12及基板14間。凸塊19係形成於基板14相對側上以提供進一步電性內連線。半導體晶粒20、22及24被堆疊在基板26上並由密封劑28所覆蓋。半導體晶粒20-24係電性連接至具有凸塊32之基板26。
如第2a圖所示，該底部填充材料18係使用填封工具34自半導體晶粒12一側開始沉積。若底部填充材料18未均勻散佈，或者該底部填充材料係超量填佈，則該底部填充材料會如第2b圖所示地流出至基板26之接觸墊片36上。在該些接觸墊片典型地被放置於較靠近半導體晶粒12之佔用空間時，該底部填充材料的流出對於具有高輸入/輸出(I/O)密度之半導體裝置係特別地敏銳。在接觸墊片36上之超額底部填充材料18的流出防止凸塊32電性連接至基板14上之接觸墊片，其產生缺陷並減少製造良率。
存在著減少超額底部填充材料自該半導體晶粒下方流至該基板之接觸墊片上之需求。據此，在一實施例中，本發明係一種半導體裝置之製造方法，包括之步驟為提供一覆晶型半導體晶粒及第一基板、在該第一基板中放置該覆晶型半導體晶粒至該第一基板之中心位置處形成一開口、將該覆晶型半導體晶粒安裝至在該第一基板中之開口上之第一基板、安裝複數個半導體晶粒至一第二基板、在該複數個半導體晶粒及第二基板上沉積一密封劑、將該第二基板安裝至該第一基板、透過該覆晶型半導體晶粒及第一基板之間的開口填佈底部填充材料至第一基板內、及在該底部填充材料接近或到達該覆晶型半導體晶粒周圍時，中斷該底部填充材料之填佈以減少該底部填充材料的流出。
在另一實施例中，本發明係一種半導體裝置之製造方法，包括之步驟為提供一第一半導體晶粒及第一基板；在該第一基板內形成一開口；將該第一半導體晶粒安裝至在該第一基板中之開口上之第一基板；安裝複數個第二半導體晶粒至一第二基板；將該第二基板安裝至該第一基板；透過該第一半導體晶粒及第一基板間的開口填佈底部填充材料至第一基板內；及在該底部填充材料接近或到達該半導體晶粒周圍時中斷該底部填充材料之填佈。
在另一實施例中，本發明係一種半導體裝置之製造方法，包括之步驟為提供一半導體晶粒及基板、在該第一基板內形成一開口、將該第一半導體晶粒安裝至在該第一基板中之開口上之第一基板、提供一疊合式封裝半導體組件、安裝該疊合式封裝半導體組件至該半導體晶粒上之基板、及透過該半導體晶粒及基板間之開口填佈底部填充材料至基板內。
在另一實施例中，本發明係一種包括具有一開口之基板之半導體裝置。一半導體晶粒被安裝至具有該開口之基板中，位在該基板中放置該半導體晶粒至該基板之中心處。一疊合式封裝半導體組件係安裝至該半導體晶粒上之基板。一底部填充材料透過半導體晶粒及基板間之開口被填佈至該基板內。
本發明係描述於參考該些圖形以進行下列說明之一或更多實施例中，其中，類似編號代表相同或類似構件。儘管本發明已就取得本發明目的之最佳模式做說明，然而那些熟知此項技術之人士會理解到想要將包含於下列揭示與圖式所支持之所附申請專利範圍和它們等效例所定義之本發明精神及範圍內之替代例、修改例及等效例涵蓋在內。
半導體裝置大體上係使用二複合製程來製造：前端製程及後端製程。前端製程涉及在一半導體晶圓表面上形成複數個晶粒。在該晶圓上之每一個晶粒內含主動及被動電性元件，其係電性連接以形成功能性電性電路。例如電晶體及二極體之主動電性元件具有控制電流流動之能力。例如電容器、電感器、電阻器和變壓器之被動電性元件建立用以執行電性電路功能所需之電壓及電流間之關係。
被動和主動元件係由包含摻雜、沉積、微影成像、蝕刻及平坦化之一系列製程步驟來形成於該半導體晶圓表面上。摻雜藉由例如離子植入或熱擴散技術將雜質引入該半導體材料中。該摻雜製程改變主動裝置內之半導體材料導電性，以轉換該半導體材料成為一絕緣體、導體，或動態地改變該半導體材料導電性以回應一電場或基極電流。電晶體內含用以依據該電場或基極電流之應用來致能該電晶體，以增進或限制電流流動所需而安排之不同摻雜類型及程度之區域。
主動和被動元件係由具有不同電性特性之材料層所形成。該些層可藉由依沉積材料類型所部分決定之各種沉積技術來形成。例如，薄膜沉積技術可涉及化學氣相沉積(CVD)、物理氣相沉積(PVD)、電解電鍍及無電鍍製程。將每一層大體上進行圖案化以形成主動元件、被動元件或元件間之電性連接之各部分。
該些層可使用微影成像技術來進行圖案化，其涉及將例如光阻劑之感光性材料沉積在欲圖案化層上。利用光來使一圖案自一光罩轉移至該光阻劑。使用一溶劑將受光之光阻劑圖案部分移除，以露出圖案化下層部分。將剩餘光阻劑移除，而留下一圖案化層。替代性地，一些材料類型係藉由使用例如無電鍍及電解電鍍技術，將該材料直接沉積至前一沉積/蝕刻製程所形成之區域或孔隙內。
將一薄膜材料沉積於一現存圖案上可擴大下層圖案並產生不均勻平坦表面。需要一均勻平坦表面以產生較小且更高密度包裝之主動及被動元件。平坦化可被使用以移除來自該晶圓表面之材料並產生一均勻平坦表面。平坦化涉及利用一拋光片來拋光該晶圓表面。一研磨材料及腐蝕性化學藥品係於拋光期間添加至該晶圓表面。該化學藥品之研磨及腐蝕動作所結合之機械動作移除任何不規則拓樸，而產生一均勻平坦表面。
後端製程涉及切割或單粒化該已完成晶圓成為個別晶粒，並接著封裝該晶粒以提供結構性支撐和環境隔離。為了單粒化該晶粒，該晶圓係沿著所謂切割道或劃線之晶圓無功能區域來劃線並切斷。使用一雷射切割工具或鋸刀來單粒化該晶圓。在單粒化後，該個別晶粒被安裝至包含接腳或接觸墊片以與其它系統元件互相連接之封裝基板。形成於該半導體晶粒上之接觸墊片接著被連接至該封裝內之接觸墊片。可利用銲接凸塊、短柱凸塊、導電膏或接線來製造該些電性連接。一密封劑或其它密封材料係沉積於該封裝上以提供物理性支撐及電性隔離。該已完成封裝接著被插入至一電性系統中，且所產生之半導體裝置功能可由其它系統元件利用之。
第3圖說明具有內含將複數個半導體封裝安裝於它的表面上之晶片載體基板或印刷電路板(PCB)52之電子裝置50。電子裝置50可視應用而具有一半導體封裝類型或多種半導體封裝類型。不同半導體封裝類型係基於說明目的而顯示於第3圖。
電子裝置50可為一獨立系統，其使用該些半導體封裝來執行一或更多電性功能。替代性地，電子裝置50可以是一較大型系統之子元件。例如，電子裝置50可以是一圖形卡、網路介面卡、或可插入至一電腦中之其它訊號處理卡。該半導體封裝可包含微處理器、記憶體、特殊用途積體電路(ASIC)、邏輯電路、類比電路、射頻電路、或其它半導體晶粒或電性元件。
在第3圖中，印刷電路板52提供一般性基板以提供安裝於該印刷電路板上之半導體封裝之結構支撐及電性連接。訊號導線54係使用蒸鍍、電解電鍍、無電鍍、網印或其它合適金屬沉積製程來形成於印刷電路板52一表面上或各層內。訊號導線54提供該些半導體封裝、安裝元件及其它外部系統元件之每一個間之電性通訊。導線54也提供該些半導體封裝中每一個之電力及接地。
在一些實施例中，一半導體裝置具有二封裝層級。第一層級封裝係提供機械性及電性附接該半導體晶粒至一中間載體之技術。第二層級封裝涉及機械性及電性附接該中間載體至該印刷電路板上。在其它實施例中，一半導體裝置可以只具有該第一層級封裝，其中，該晶粒係機械性及電性地直接安裝至該印刷電路板上。
基於說明目的，一些包含打線封裝56及覆晶封裝58之第一層級封裝類型係示於印刷電路板52上。此外，所示一些包含球狀柵格陣列(BGA)60、凸塊晶片載體(BCC)62、雙列式封裝(DIP)64、平面柵格陣列(LGA)66、多晶片模組(MCM)68、四邊扁平無接腳封裝(QFN)70及四邊扁平封裝72之第二層級封裝類型係安裝於印刷電路板52上。依據系統需求，利用任何第一和第二層級封裝型結合所架構之任何半導體封裝結合以及其它電子元件可被連接至印刷電路板52。在一些實施例中，電子裝置50包含單一附接半導體封裝，而其它實施例需要多個互相連接之封裝。藉由結合單一基板上之一或更多半導體封裝，製造商可整合預製元件至電子裝置及系統中。因為該些半導體封裝包含複雜功能，故電子裝置可使用較便宜元件及一貫化製程來製造之。產生之裝置較不會失敗且製造費用也較少，因而對於消費者而言成本也較低。
第4a-4c圖顯示示範性半導體封裝。第4a圖說明安裝於印刷電路板52上之雙列式封裝64的進一步細節。半導體晶粒74包含一作用區，內含類比或數位電路，配置成形成於該晶粒內並根據該晶粒之電性設計產生電性互連之主動裝置、被動裝置、導電層及介電層。例如，該電路可包含一或更多電晶體、二極體、電感器、電容器、電阻器及形成於該半導體晶粒74之作用區內的其它電路構件。接觸墊片76係例如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)或銀(Ag)之一或更多導電材料層，且被電性連接至形成於半導體晶粒74內之電路構件。在雙列式封裝64組合期間，半導體晶粒74係使用一金矽共熔合金層或例如熱環氧化物或環氧樹脂之黏性材料來安裝至一中間載體78。該封裝本體包含例如聚合物或陶瓷之絕緣封裝材料。導體接腳80或接線82提供半導體晶粒74及印刷電路板52間之電性互連。密封劑84係沉積於該封裝上，藉此阻止濕氣及微粒進入該封裝並污染晶粒74及接線82而提供環境保護。
第4b圖說明安裝於印刷電路板52上之凸塊晶片載體62的進一步細節。半導體晶粒88係使用一底膠或環氧樹脂黏性材料92來安裝於載體90上。接線94提供接觸墊片96及98間之第一層級封裝內連線。密封化合物或密封劑100係沉積於半導體晶粒88及接線94上，以提供該裝置物理性支撐和電性隔離。接觸墊片102係使用例如電解電鍍或無電鍍之合適金屬沉積製程來形成於印刷電路板一表面上以阻止氧化作用。接觸墊片102係電性連接至印刷電路板52內之一或更多訊號導線54。凸塊104係形成於凸塊晶片載體62之接觸墊片98及印刷電路板52之接觸墊片102之間。
在第4c圖中，利用一覆晶型第一層級封裝技術將半導體晶粒58面向下地安裝至中間載體106。半導體晶粒58之作用區108包含類比或數位電路，配置成根據該晶粒的電性設計所形成之主動裝置、被動裝置、導電層及介電層。例如，該電路可包含一或更多電晶體、二極體、電感器、電容器、電阻器及在作用區108內之其它電路構件。半導體晶粒58係透過凸塊110來電性及機械性地連接至載體106。
球狀柵格陣列60係利用一球狀柵格陣列型第二層級封裝技術，使用凸塊112來電性及機械性地連接至印刷電路板52。半導體晶粒58係透過凸塊110、訊號線114及凸塊112來電性連接至印刷電路板52中之訊號導線54。一密封化合物或密封劑116係沉積於半導體晶粒58及載體106上，以提供該裝置物理性支撐及電性隔離。該覆晶半導體裝置提供自半導體晶粒58上之主動裝置至印刷電路板52上之導線的短導電路徑，用以減少訊號傳送距離、降低電容並改善整體電路執行效率。在另一實施例中，可使用覆晶型第一層級封裝技術將該半導體晶粒58直接機械性且電性地連接至印刷電路板52而不使用中間載體106。
第5a-5k圖說明與第3圖及第4a-4c圖相關之一種透過覆晶疊合式封裝組件之底部基板中的穿孔開口來填佈底部填充材料以控制該底部填充材料流出之製程。第5a圖顯示具有內含類比或數位電路之作用表面122之覆晶型半導體晶粒120，該些類比或數位電路配置成形成於該晶粒內並根據該晶粒之電性設計和功能產生電性互連的主動裝置、被動裝置、導電層及介電層。例如，該電路可包含一或更多電晶體、二極體及形成於該作用表面122內之其它電路構件，以配置例如數位訊號處理(DSP)、特殊用途積體電路、記憶體或其它訊號處理電路之類比電路或數位電路。半導體晶粒122也可包含例如電感器、電容器及電阻器之整合被動元件以提供射頻訊號處理。複數個凸塊124係形成於作用表面122上以提供電性內連線。
一基板126包含形成於該基板中以根據半導體晶粒120之電性設計和功能來提供電性內連線之導電層或導線128。該些導電層及導線128延伸橫過基板126至由絕緣層134所電性隔離之頂部表面130及相對底部表面132間之基板。複數個接觸墊片136係形成於半導體晶粒120之晶粒附接區135或佔用空間外的基板126之頂部表面130上。複數個接觸墊片137係形成於晶粒附接區135內之基板126的頂部表面130上。一穿孔開口138係貫穿基板126而形成於線139之對應位置，其為相對於晶粒附接區135內之基板126所放置之半導體晶粒120之中心。該穿孔開口138自頂部表面130延伸至底部表面132。複數個凸塊140係形成於底部表面132上以提供電性內連線。
第5b圖顯示具有穿孔開口138及凸塊140之基板126的底部表面132之圖形。該穿孔開口138係位在基板上126放置半導體晶粒120之中心之線139處。第5c圖顯示具有複數個穿孔開口142及凸塊140之底部表面132之替代性實施例。該些穿孔開口142係環繞在基板126上放置半導體晶粒120之中心位置進行均勻散佈。
在第5d圖中，半導體晶粒120係藉由迴銲凸塊124而以金屬冶金方式電性連接該些凸塊至接觸墊片137來安裝至基板126。
第5e圖顯示具有內含類比或數位電路之作用表面152之半導體晶粒150，該些類比或數位電路配置成形成於該晶粒內並根據該晶粒之電性設計和功能產生電性互連的主動裝置、被動裝置、導電層及介電層。例如，該電路可包含一或更多電晶體、二極體及形成於該作用表面152內之其它電路構件，以配置例如數位訊號處理、特殊用途積體電路、記憶體或其它訊號處理電路之類比電路或數位電路。半導體晶粒152也可包含例如電感器、電容器及電阻器之整合被動元件以提供射頻訊號處理。
一基板154包含形成於該基板中以根據半導體晶粒150之電性設計和功能來提供電性內連線之導電層或導線156。該些導電層及導線156延伸橫過基板154至由絕緣層162所電性隔離之頂部表面158及底部表面160間之基板。複數個接觸墊片164係形成於放置半導體晶粒150之外的基板154之頂部表面158上。複數個接觸墊片166係形成於基板154之底部表面160上。如第5f圖所示，半導體晶粒150係安裝至具有晶粒黏接層168之基板154。
一半導體晶粒170具有內含類比或數位電路之作用表面172，該些類比或數位電路配置成形成於該晶粒內並根據該晶粒之電性設計和功能產生電性互連的主動裝置、被動裝置、導電層及介電層。例如，該電路可包含一或更多電晶體、二極體及形成於作用表面172內之其它電路構件，以配置例如數位訊號處理、特殊用途積體電路、記憶體或其它訊號處理電路之類比電路或數位電路。半導體晶粒170也可包含例如電感器、電容器及電阻器之整合被動元件以提供射頻訊號處理。半導體晶粒170係安裝至具有晶粒黏接層174之半導體晶粒150。
一半導體晶粒176具有內含類比或數位電路之作用表面178，該些類比或數位電路配置成形成於該晶粒內並根據該晶粒之電性設計和功能產生電性互連的主動裝置、被動裝置、導電層及介電層。例如，該電路可包含一或更多電晶體、二極體及形成於作用表面178內之其它電路構件，以配置例如數位訊號處理、特殊用途積體電路、記憶體或其它訊號處理電路之類比電路或數位電路。半導體晶粒176也可包含例如電感器、電容器及電阻器之整合被動元件以提供射頻訊號處理。半導體晶粒176係安裝至具有晶粒黏接層180之半導體晶粒170。堆疊半導體晶粒150、170及176可具有如第5f圖所示之類似佔用空間或不同佔用空間。
在第5g圖中，半導體晶粒150、170及176係利用接線來電性連接至基板154之接觸墊片164。使用一錫膏印刷、壓縮成型、轉注成型、液體密封成型、真空疊合、旋塗或其它合適塗抹器將一密封劑184沉積於半導體晶粒150、170、176及基板154上。密封劑184可為聚合物複合材料，例如，具有填充劑之環氧樹脂、具有填充劑之環氧丙烯酯或具有獨特填充劑之聚合物。密封劑184係無導電性且在環境上保護該半導體裝置隔離於外部構件及污染。複數個凸塊186係形成於基板154之接觸墊片166上以提供電性內連線。安裝至基板154之堆疊半導體晶粒150、170及176構成一疊合式封裝半導體組件188。
在第5h圖及第5i圖中，該疊合式封裝半導體組件188係藉由迴銲凸塊186在該些凸塊及接觸墊片136間形成一金屬冶金性及電性連接而安裝至基板126。疊合式封裝半導體組件188與具有半導體晶粒120之基板126之結合被稱為覆晶疊合式封裝組件190。第5j圖顯示第二次迴銲以改進至接觸墊片136之電性連接之凸塊186。
在該疊合式封裝半導體組件188被安裝至基板126後，該覆晶疊合式封裝組件190被反轉而如第5k圖所示地底部表面132及凸塊140方位向上，一填封工具194將例如環氧樹脂之底部填充材料196自基板126之底部表面132透過穿孔開口138(或穿孔開口142)來填佈至半導體晶粒120及基板126間之區域。因為穿孔開口138相對於半導體晶粒120係位於中心處，故底部填充材料196係均勻平坦地自開口138之中心位置散佈至該晶粒周圍。底部填充材料196的填佈量及該底部填充材料的散佈方式可受到控制以極小化或消除材料流出並減少該底部填充材料中之空隙的形成。在該底部填充材料接近或到達半導體晶粒120周圍時，中斷或中止來自填封工具194之底部填充材料196的填佈。
第6圖顯示硬化底部填充材料196並進行電子測試後之覆晶疊合式封裝組件190。既然底部填充材料196係自基板126上放置半導體晶粒120之中心位置開始向外填佈至該晶粒所有側邊，該底部填充材料係平坦地散佈於該晶粒及基板之間。該底部填充材料196應同時到達環繞半導體晶粒120周圍之所有側邊。沒有半導體晶粒120之側邊會具有一長填充劑寬度。藉由極小化或消除底部填充材料流出而減少電性內連線缺陷。該開口138同時減少內部應力並增加可靠性。隨著較少底部填充材料流出，該輸入/輸出密度及佈局可被改進，也就是，接觸墊片136可被放置於較接近半導體晶粒120之佔用空間。
儘管本發明一或更多實施例已被詳述，但熟知此項技術之人士會理解到那些實施例之修正及改寫可被進行而不偏離下列申請專利範圍所提出之本發明範圍。
10．．．覆晶疊合式封裝結構
12．．．覆晶型半導體晶粒
14．．．基板
16．．．凸塊
18．．．底部填充材料
19．．．凸塊
20．．．半導體晶粒
22．．．半導體晶粒
24．．．半導體晶粒
26．．．基板
28．．．密封劑
32．．．凸塊
34．．．填封工具
36．．．接觸墊片
50．．．電子裝置
52．．．印刷電路板
54．．．導線
56．．．打線封裝
58．．．覆晶封裝
60．．．球狀柵格陣列
62．．．凸塊晶片載體
64．．．雙列式封裝
66．．．平面柵格陣列
68．．．多晶片模組
70．．．四邊扁平無接腳封裝
72．．．四邊扁平封裝
74．．．半導體晶粒
76．．．接觸墊片
78．．．中間載體
80．．．導體接腳
82．．．接線
84．．．密封劑
88．．．半導體晶粒
90．．．載體
92．．．底膠或環氧樹脂黏性材料
94．．．接線
96．．．接觸墊片
98．．．接觸墊片
100．．．密封化合物或密封劑
102．．．接觸墊片
104．．．凸塊
106．．．中間載體
108．．．作用區
110．．．凸塊
112．．．凸塊
114．．．訊號線
116．．．密封化合物或密封劑
120．．．覆晶型半導體晶粒
122．．．作用表面
124．．．凸塊
126．．．基板
128．．．導線
130．．．頂部表面
132．．．底部表面
134．．．絕緣層
135．．．晶粒附接區
136．．．接觸墊片
137．．．接觸墊片
138．．．穿孔開口
139．．．線
140．．．凸塊
142．．．穿孔開口
150‧‧‧半導體晶粒
152‧‧‧作用表面
154‧‧‧基板
156‧‧‧導電層或導線
158‧‧‧頂部表面
160‧‧‧底部表面
162‧‧‧絕緣層
164‧‧‧接觸墊片
166‧‧‧接觸墊片
168‧‧‧晶粒附接層
170‧‧‧半導體晶粒
172‧‧‧作用表面
174‧‧‧晶粒附接層
176‧‧‧半導體晶粒
178‧‧‧作用表面
180‧‧‧晶粒附接層
182‧‧‧接線
184‧‧‧密封劑
186‧‧‧凸塊
188‧‧‧疊合式封裝半導體組件
190‧‧‧覆晶疊合式封裝組件
194‧‧‧填封工具
196‧‧‧底部填充材料
第1圖說明一傳統覆晶型半導體晶粒的疊合式封裝結構。
第2a-2b圖顯示自產生缺陷之不均勻或過量填佈之底部填充材料的流出。
第3圖說明具有不同封裝類型被安裝至它表面上之印刷電路板。
第4a-4c圖說明安裝至該印刷電路板之代表性半導體封裝之進一步細部。
第5a-5k圖說明在一覆晶疊合式封裝組件之底部基板中形成一穿孔開口以控制底部填充材料填佈之製程。
第6圖說明硬化該底部填充材料後之覆晶疊合式封裝組件。
120．．．覆晶型半導體晶粒
122．．．作用表面
124．．．凸塊
126．．．基板
128．．．導線
130．．．頂部表面
132．．．底部表面
134．．．絕緣層
136．．．接觸墊片
137．．．接觸墊片
138．．．穿孔開口
139．．．線
140．．．凸塊
150．．．半導體晶粒
152．．．作用表面
154．．．基板
156．．．導電層或導線
158．．．頂部表面
160．．．底部表面
162．．．絕緣層
164．．．接觸墊片
166．．．接觸墊片
168．．．晶粒附接層
170．．．半導體晶粒
172．．．作用表面
174．．．晶粒附接層
176．．．半導體晶粒
178．．．作用表面
180．．．晶粒附接層
182．．．接線
184．．．密封劑
186．．．凸塊
190．．．覆晶疊合式封裝組件
196．．．底部填充材料

Claims (15)

  1. 一種半導體裝置之製造方法，包括：提供一第一半導體晶粒及第一基板；在該第一基板內形成一開口；安裝該第一半導體晶粒至第一基板，使其在該第一基板中之開口上；安裝第二半導體晶粒至一第二基板；安裝該第二基板至該第一基板，使其在該第一半導體晶粒上；在安裝該第二基板至該第一基板之後，透過在該第一半導體晶粒及第一基板間之開口填佈多個底部填充材料至第一基板內，其以一控制方式向外地朝向該第一半導體晶粒之周圍分佈該些底部填充材料；及在該底部填充材料接近該第一半導體晶粒周圍時，中斷該底部填充材料之填佈。
  2. 如申請專利範圍第1項之方法，其中，該第一基板內之開口係位在與該第一基板有關之第一半導體晶粒的中心位置處。
  3. 如申請專利範圍第1項之方法，進一步包含在該第一基板中形成均勻地散佈的複數個開口於接近放置該第一半導體晶粒至與該第一基板有關之中心處。
  4. 如申請專利範圍第1項之方法，進一步包含安裝該第二基板與該第一半導體晶粒接觸。
  5. 如申請專利範圍第1項之方法，進一步包含： 在該第一半導體晶粒之表面上形成複數個凸塊；及迴銲該些凸塊以安裝該第二基板至該第一基板。
  6. 一種半導體裝置之製造方法，包括：提供一半導體晶粒及基板；在該基板內形成一開口；安裝該半導體晶粒至該基板，使其在該基板中之開口上；提供一疊合式封裝(PoP)半導體組件；安裝該疊合式封裝半導體組件至該半導體晶粒上之基板；在安裝該疊合式封裝半導體組件至該基板之後，透過該半導體晶粒及基板間之開口填佈底部填充材料至基板內；及在該底部填充材料接近該半導體晶粒周圍時，中斷該底部填充材料之填佈。
  7. 如申請專利範圍第6項之方法，其中，該基板內之開口係位在放置該第一半導體晶粒之與該基板有關之中心處。
  8. 如申請專利範圍第6項之方法，進一步包含在該基板中形成均勻地散佈複數個開口於接近放置該半導體晶粒至與該基板有關之中心處。
  9. 如申請專利範圍第6項之方法，進一步包含：在該基板一表面上形成複數個凸塊；及迴銲該些凸塊以安裝該疊合式封裝半導體組件至該基 板。
  10. 如申請專利範圍第6項之方法，其進一步包含安裝該疊合式封裝半導體組件與該半導體晶粒接觸。
  11. 一種半導體裝置，包括：一基板，含有一開口；一半導體晶粒，安裝至具有該開口之基板中，位於該基板中放置該半導體晶粒至與該基板有關之中心處；一疊合式封裝(PoP)半導體組件，安裝至該半導體晶粒上之基板；及一底部填充材料，透過半導體晶粒及具有該疊合式封裝半導體組件安裝於其上的基板間之開口填佈至該基板內，其中該底部填充材料在該半導體晶粒的一周邊處終止並且在該基板中的該開口的一部分是不含該底部填充材料。
  12. 如申請專利範圍第11項之半導體裝置，進一步包含在該基板中形成均勻地散佈的複數個開口，係放置於接近該半導體晶粒至與該基板有關之中心處。
  13. 如申請專利範圍第11項之半導體裝置，其中，該半導體晶粒係一覆晶型半導體晶粒。
  14. 如申請專利範圍第11項之半導體裝置，進一步包含複數個凸塊，形成於該基板之表面上以安裝該疊合式封裝半導體組件至該基板。
  15. 如申請專利範圍第11項之半導體裝置，其中，該疊合式封裝半導體組件係接觸該半導體晶粒。
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