CN102254835A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN102254835A
CN102254835A CN2011101272739A CN201110127273A CN102254835A CN 102254835 A CN102254835 A CN 102254835A CN 2011101272739 A CN2011101272739 A CN 2011101272739A CN 201110127273 A CN201110127273 A CN 201110127273A CN 102254835 A CN102254835 A CN 102254835A
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China
Prior art keywords
substrate
semiconductor
semiconductor element
filler material
tube core
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CN2011101272739A
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English (en)
Inventor
胡俊伟
李在学
谭琳
瞿文彬
冯玉锋
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Stats Chippac Shanghai Co Ltd
Stats Chippac Pte Ltd
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Stats Chippac Shanghai Co Ltd
Stats Chippac Pte Ltd
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Publication of CN102254835A publication Critical patent/CN102254835A/zh
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Abstract

本发明涉及半导体器件及其制造方法。一种具有倒装芯片半导体管芯的半导体器件，所述倒装芯片半导体管芯利用多个第一凸块被安装到第一衬底。在倒装芯片半导体管芯到第一衬底的置放中心的位置中在第一衬底中形成一个开口或多个开口。多个半导体管芯被安装到第二衬底。半导体管芯与结合线电连接。密封剂在所述多个半导体管芯和第二衬底上。第二衬底利用多个第二凸块被安装到第一衬底。通过在倒装芯片半导体管芯和第一衬底之间的第一衬底中的开口分配底部填充剂材料。当底部填充剂材料接近或到达倒装芯片半导体管芯的周边时停止底部填充剂材料的分配以减少底部填充剂材料的渗出。底部填充剂材料被固化。

Description

半导体器件及其制造方法
技术领域
本发明总体上涉及半导体器件，并且更具体地说涉及半导体器件和在倒装芯片PoP组件的底部衬底中形成穿孔开口以减少过剩底部填充剂材料的渗出的方法。
背景技术
在现代电子产品中通常会发现有半导体器件。半导体器件在电部件的数量和密度上有变化。分立的半导体器件一般包括一种电部件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器、以及功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件通常包括数百到数百万的电部件。集成半导体器件的实例包括微控制器、微处理器、电荷耦合器件（CCD）、太阳能电池、以及数字微镜器件（DMD）。
半导体器件执行多种功能，例如高速计算、发射和接收电磁信号、控制电子器件、将日光转换成电、以及为电视显示器生成可视投影。在娱乐、通信、功率转换、网络、计算机、以及消费品领域中有半导体器件的存在。在军事应用、航空、汽车、工业控制器、以及办公设备中也有半导体器件的存在。
半导体器件利用半导体材料的电特性。半导体材料的原子结构允许通过施加电场或基极电流（base current）或者通过掺杂工艺来操纵（manipulated）它的导电性。掺杂把杂质引入半导体材料中以操纵和控制半导体器件的导电性。
半导体器件包括有源和无源电结构。有源结构（包括双极和场效应晶体管）控制电流的流动。通过改变掺杂水平并且施加电场或基极电流，晶体管促进或限制电流的流动。无源结构（包括电阻器、电容器、和电感器）产生执行多种电功能所必需的电压和电流之间的关系。无源和有源结构被电连接以形成电路，所述电路能够使半导体器件执行高速计算和其它有用的功能。
通常利用两个复杂的制造工艺来制造半导体器件，即前端制造和后端制造，每个可能包括数百个步骤。前端制造包括在半导体晶片的表面上形成多个管芯。每个管芯通常相同并且包括通过电连接有源和无源部件形成的电路。后端制造包括从已完成的晶片单体化（singulating）单个管芯并且封装管芯以提供结构支撑和环境隔离。
半导体制造的一个目标是制造更小的半导体器件。更小的半导体器件通常消耗更少功率、具有更高的性能、并且能够被更有效地制造。另外，更小的半导体器件具有更小的占用空间（footprint），其对于更小的最终产品而言是期望的。通过改善导致产生具有更小、更高密度的有源和无源部件的管芯的前端工艺可以实现更小的管芯尺寸。通过改善电互连和封装材料，后端工艺可以产生具有更小占用空间的半导体器件封装。
图1示出常规倒装芯片层叠封装（PoP）结构10。倒装芯片型半导体管芯12被安装到具有凸块16的衬底14。底部填充剂材料18（例如环氧树脂）被沉积在半导体管芯12和衬底14之间。凸块19形成在衬底14的相对侧上用于进一步的电互连。半导体管芯20、22、和24层叠在衬底26上并且被密封剂28覆盖。半导体管芯20－24利用结合线30电连接到衬底26。衬底26利用凸块32连接到衬底14。
利用滴涂工具（dispensing tool）34从半导体管芯12的一侧沉积底部填充剂材料18，如图2a中所示。如果底部填充剂材料18没有被均匀和一致地分布，或者如果底部填充剂材料被以超额体积分配，则底部填充剂材料可能渗出到衬底26的接触焊盘36上，如图2b中所示。渗出的底部填充剂对于具有高输入/输出（I/O）密度的半导体器件来说是特别严重的，因为接触焊盘通常被放置得更靠近半导体管芯12的占用空间。过剩的底部填充剂材料18在接触焊盘36上渗出阻止了凸块32电连接到衬底14上的接触焊盘，这引起缺陷并且降低了制造成品率。
发明内容
存在对减少过剩的底部填充剂材料从半导体管芯下渗出到衬底的接触焊盘上的需要。因此，在一个实施例中，本发明是制造半导体器件的方法，所述方法包括以下步骤：提供倒装芯片半导体管芯和第一衬底，在第一衬底中在倒装芯片半导体管芯到第一衬底的置放中心的位置中形成开口，在第一衬底中的开口上将倒装芯片半导体管芯安装到第一衬底，将多个半导体管芯安装到第二衬底，在所述多个半导体管芯和第二衬底上沉积密封剂，将第二衬底安装到第一衬底，通过倒装芯片半导体管芯和第一衬底之间的第一衬底中的开口分配底部填充剂材料，以及当底部填充剂材料接近或到达倒装芯片半导体管芯的周边时停止底部填充剂材料的分配以减少底部填充剂材料的渗出。
在另一个实施例中，本发明是制造半导体器件的方法，所述方法包括以下步骤：提供第一半导体管芯和第一衬底，在第一衬底中形成开口，在第一衬底中的开口上将第一半导体管芯安装到第一衬底，将多个第二半导体管芯安装到第二衬底，将第二衬底安装到第一衬底，通过第一半导体管芯和第一衬底之间的第一衬底中的开口分配底部填充剂材料，以及当底部填充剂材料接近或到达倒装芯片半导体管芯的周边时停止底部填充剂材料的分配。
在另一个实施例中，本发明是制造半导体器件的方法，所述方法包括以下步骤：提供半导体管芯和衬底，在第一衬底中形成开口，在第一衬底中的开口上将第一半导体管芯安装到第一衬底，提供PoP半导体组件，将PoP半导体组件安装到半导体管芯上的衬底，以及通过半导体管芯和衬底之间的衬底中的开口分配底部填充剂材料。
在另一个实施例中，本发明是一种包括具有开口的衬底的半导体器件。半导体管芯被安装到衬底，其中所述衬底中的开口位于半导体管芯到衬底的置放位置的中心。PoP半导体组件被安装到半导体管芯上的衬底。底部填充剂材料通过半导体管芯和衬底之间的衬底中的开口被分配。
附图说明
图1示出常规倒装芯片半导体管芯PoP结构；
图2a-2b示出底部填充剂材料由于不均匀或超额体积分配而导致的渗出，所述渗出引起缺陷；
图3示出具有安装到其表面的不同类型封装的PCB；
图4a-4c示出安装到所述PCB的典型半导体封装的更多细节；
图5a-5k示出在倒装芯片PoP组件的底部衬底中形成穿孔开口以控制底部填充剂材料的分配的过程；以及
图6示出在底部填充剂材料的固化之后的倒装芯片PoP组件。
具体实施方式
参考附图在下列描述中的一个或多个实施例中描述本发明，在附图中相似的数字表示相同或类似的元件。虽然根据用来实现本发明的目的的最佳方式描述本发明，但是本领域技术人员将理解的是，它旨在覆盖可以被包含在由被下列公开和各图所支持的所附权利要求及其等效物限定的本发明的精神和范围内的替代物、变型、和等效物。
一般利用两个复杂的制造工艺制造半导体器件：前端制造和后端制造。前端制造包括在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包括有源和无源电部件，所述有源和无源电部件被电连接以形成功能电路。有源电部件，例如晶体管和二极管，具有控制电流的流动的能力。无源电部件，例如电容器、电感器、电阻器、和变压器，产生执行电路功能所必需的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、刻蚀、和平面化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过例如离子注入或热扩散的技术将杂质引入到半导体材料中。所述掺杂工艺改变有源器件中的半导体材料的导电性，将半导体材料转变成绝缘体、导体，或响应于电场或基极电流动态改变半导体材料导电性。晶体管包括有变化的掺杂类型和程度的区域，所述区域根据需要被设置为使晶体管能够在施加电场或基极电流时促进或限制电流的流动。
通过具有不同电特性的材料的层形成有源和无源部件。所述层可以通过部分地由被沉积的材料的类型决定的多种沉积技术形成。例如，薄膜沉积可以包括化学汽相沉积（CVD）、物理汽相沉积（PVD）、电解电镀、以及无电极电镀（electroless plating）工艺。每个层通常被图案化以形成有源部件、无源部件、或部件之间的电连接的各部分。
可以利用光刻图案化所述层，所述光刻包括在将被图案化的层上沉积光敏材料，例如光致抗蚀剂。利用光将图案从光掩模转移到光致抗蚀剂。利用溶剂将经受光的光致抗蚀剂图案部分除去，暴露将被图案化的下层的各部分。光致抗蚀剂的剩余物被除去，留下被图案化的层。可替换地，利用例如无电极电镀或电解电镀的技术通过直接将材料沉积到通过先前的沉积/刻蚀工艺形成的区域或空隙中来图案化一些类型的材料。
在现有图案上沉积材料的薄膜可能会放大下面的图案并且引起不均匀的平面。需要均匀的平面来制造更小和更密集包装的有源和无源部件。可以利用平面化从晶片的表面除去材料和制造均匀平面。平面化包括利用抛光垫抛光晶片的表面。在抛光期间，磨料和腐蚀性化学品被添加到晶片的表面。组合的磨料机械作用和化学品腐蚀作用除去了任何不规则的表面形貌（topography），产生均匀的平面。
后端制造指的是将已完成的晶片切割或单体化成单个管芯，并且然后封装管芯用于结构支撑和环境隔离。为单体化管芯，沿被叫做划片街区（saw street）或划线的晶片非功能区域刻划和断开所述晶片。利用激光切割工具或锯条来单体化晶片。在单体化之后，单个管芯被安装到封装衬底，所述封装衬底包括用来与其它系统部件互连的引脚或接触焊盘。形成在半导体管芯上的接触焊盘然后被连接到封装内的接触焊盘。可以利用焊料凸块、柱形凸块（stud bump）、导电胶、或线结合（wirebond）来制作电连接。密封剂或其它成型材料被沉积到封装上以提供物理支撑和电隔离。已完成的封装然后被插入电系统中并且半导体器件的功能可以用到其它系统部件。
图3示出具有芯片载体衬底或印刷电路板（PCB）52的电子器件50，所述芯片载体衬底或印刷电路板（PCB）52具有多个安装在它的表面上的半导体封装。电子器件50可以具有一种半导体封装、或多种半导体封装，这取决于应用。为了说明的目的，在图3中示出不同类型的半导体封装。
电子器件50可以是利用半导体封装来执行一个或多个电功能的独立系统。可替换地，电子器件50可以是更大系统的子部件。例如，电子器件50可以是能被插入计算机中的图形卡、网络接口卡、或其它信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、RF电路、分立器件、或其它半导体管芯或电部件。
在图3中，PCB 52提供普通的衬底用于安装在PCB上的半导体封装的结构支撑和电互连。利用蒸发、电解电镀、无电极电镀、丝网印刷、或其它合适的金属沉积工艺将导电信号迹线（trace）54形成在PCB 52的表面上或各层内。信号迹线54提供半导体封装、安装的部件、以及其它外部系统部件中的每一个之间的电通信。迹线54也将电源和地连接提供给半导体封装中的每一个。
在一些实施例中，半导体器件可以具有两个封装级。第一级封装是用来将半导体管芯以机械和电的方式附着到中间载体的技术。第二级封装包括将所述中间载体以机械和电的方式附着到PCB。在其它实施例中，半导体器件可以仅具有第一级封装，其中管芯被以机械和电的方式直接安装到PCB。
为了说明的目的，几种第一级封装，包括线结合封装56和倒装芯片58，被示出在PCB 52上。另外，几种第二级封装，包括球栅阵列（BGA）60、凸块芯片载体（BCC）62、双列直插式封装（DIP）64、岸面栅格阵列（land grid array，LGA）66、多芯片模块（MCM）68、四侧无引脚扁平封装（quad flat non-leaded package，QFN）70、以及四侧扁平封装72被示出安装在PCB 52上。根据系统要求，利用第一和第二级封装形式的任何组合配置的半导体封装的任何组合、以及其它电子部件，可以被连接到PCB 52。在一些实施例中，电子器件50包括单个附着的半导体封装，虽然其它实施例要求多互连封装。通过在单个衬底上组合一个或多个半导体封装，制造商可以将预先制作的部件并入电子器件和系统中。因为所述半导体封装包括复杂功能，所以可以利用更便宜的部件和流水线制造工艺来制造电子器件。所得到的器件较少可能失效并且制造起来花费较少，对用户而言导致更低的成本。
图4a-4c示出示范性半导体封装。图4a示出安装在PCB 52上的DIP 64的更多细节。半导体管芯74包括包含模拟或数字电路的有源区，所述模拟或数字电路被实现为根据管芯的电设计形成在管芯内并且被电互连的有源器件、无源器件、导电层、和介电层。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及形成在半导体管芯74的有源区内的其它电路元件。接触焊盘76是导电材料（例如铝（AL）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）、或银（Ag））的一个或多个层，并且电连接到形成在半导体管芯74内的电路元件。在DIP 64的组装期间，利用金硅共晶层或粘附材料（例如热的环氧或环氧树脂）将半导体管芯74安装到中间载体78。封装体包括绝缘封装材料，例如聚合物或陶瓷。导体引线80和线结合82在半导体管芯74和PCB 52之间提供电互连。密封剂84被沉积在封装上用于通过防止湿气与粒子进入所述封装以及污染管芯74或线结合82来进行环境保护。
图4b示出安装在PCB 52上的BCC 62的更多细节。半导体管芯88利用底层填充材料或环氧树脂粘附材料92被安装到载体90上。线结合94在接触焊盘96和98之间提供第一级封装互连。模塑料或密封剂100被沉积在半导体管芯88和线结合94上以为所述器件提供物理支撑和电隔离。接触焊盘102利用电解电镀或无电极电镀这样合适的金属沉积形成在PCB 52的表面上以防止氧化。接触焊盘102电连接到PCB 52中的一个或多个导电信号迹线54。凸块104被形成在BCC 62的接触焊盘98与PCB 52的接触焊盘102之间。
在图4c中，利用倒装芯片型第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区108包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计形成的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及在有源区108内的其它电路元件。半导体管芯58通过凸块110被电连接和机械连接到载体106。
BGA 60 利用凸块112电连接和机械连接到具有BGA型第二级封装的PCB 52。半导体管芯58通过凸块110、信号线114、以及凸块112电连接到导电信号迹线54。模塑料或密封剂116被沉积在半导体管芯58和载体106上以为所述器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电轨迹的短导电路径以便减小信号传播距离、降低电容、并且改善总的电路性能。在另一个实施例中，半导体管芯58可以在没有中间载体106的情况下利用倒装芯片型第一级封装被以机械和电的方式直接连接到PCB 52。
相对于图3和图4a-4c，图5a-5k示出通过倒装芯片PoP组件的底部衬底中的穿孔开口分配底部填充剂材料以控制底部填充剂材料的渗出的过程。图5a示出具有有源表面122的倒装芯片型半导体管芯120，所述有源表面122包括被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层的模拟或数字电路。例如，所述电路可以包括一个或多个晶体管、二极管、以及形成在有源表面122内的其它电路元件以实现模拟电路或数字电路例如数字信号处理器（DSP）、ASIC、存储器、或其它信号处理电路。半导体管芯120也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。多个凸块124形成在有源表面122上用于电互连。
衬底126包括导电层或迹线128，所述导电层或迹线128形成在衬底中以根据半导体管芯120的电设计和功能提供电互连。所述导电层或迹线128延伸穿过衬底126并且贯穿被绝缘层134电分离的顶表面130和相对的底表面132之间的衬底。多个接触焊盘136形成在管芯附着区135或半导体管芯120的占用空间以外的衬底126的顶表面130上。多个接触焊盘137形成在管芯附着区135内的衬底126的顶表面130上。在对应于线139的位置处形成穿过衬底126的穿孔开口138，所述位置是半导体管芯120相对于管芯附着区135内的衬底126的置放位置的中心。穿孔开口138从顶表面130延伸到底表面132。多个凸块140形成在底表面132上用于电互连。
图5b示出具有穿孔开口138和凸块140的衬底126的底表面132的视图。穿孔开口138位于线139处（其是半导体管芯120在衬底126上的置放位置的中心）。图5c示出具有多个穿孔开口142和凸块140的底表面132的替换实施例。穿孔开口142均匀分布在半导体管芯120在衬底126上的中心置放位置周围。
在图5d中，通过回流凸块124将凸块用冶金的方法并且电性地连接到接触焊盘137，导体管芯120被安装到衬底126。
图5e示出具有有源表面152的半导体管芯150，所述有源表面152包括被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层的模拟或数字电路。例如，所述电路可以包括一个或多个晶体管、二极管、以及形成在有源表面152内的其它电路元件以实现模拟电路或数字电路例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯150也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。
衬底154包括导电层或迹线156，所述导电层或迹线156形成在衬底中以根据半导体管芯150的电设计和功能提供电互连。所述导电层或迹线156延伸穿过衬底154并且贯穿被绝缘层162电分离的顶表面158和底表面160之间的衬底。多个接触焊盘164形成在半导体管芯150的置放位置以外的衬底154的顶表面158上。多个接触焊盘166形成在衬底154的底表面160上。半导体管芯150利用管芯附着粘合剂168被安装到衬底154，如图5f中所示。
半导体管芯170具有有源表面172，所述有源表面172包括被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层的模拟或数字电路。例如，所述电路可以包括一个或多个晶体管、二极管、以及形成在有源表面172内的其它电路元件以实现模拟电路或数字电路例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯170也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。半导体管芯170利用管芯附着粘合剂174被安装到半导体管芯150。
半导体管芯176具有有源表面178，所述有源表面178包括被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层的模拟或数字电路。例如，所述电路可以包括一个或多个晶体管、二极管、以及形成在有源表面178内的其它电路元件以实现模拟电路或数字电路例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯176也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。半导体管芯176利用管芯附着粘合剂180被安装到半导体管芯170。层叠的半导体管芯150、170、和176可以具有类似的占用空间、或如图5f中所示的不同的占用空间。
在图5g中，半导体管芯150、170、和176利用结合线182电连接到衬底154的接触焊盘164。利用浆料印刷（paste printing）、压缩模塑、传递模塑、液体密封剂模塑、真空层压、旋涂、或其它合适的施加器（applicator）在半导体管芯150、170、176和衬底154上沉积密封剂184。密封剂184可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂184不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。多个凸块186形成在衬底154的接触焊盘166上用于电互连。安装到衬底154的层叠的半导体管芯150、170、和176构成PoP半导体组件188。
在图5h和5i中，通过回流凸块186在凸块和接触焊盘136之间形成冶金和电连接，PoP半导体组件188被安装到衬底126。PoP半导体组件188和具有半导体管芯120的衬底126的组合被称为倒装芯片PoP组件190。图5j示出凸块186被二次回流以改善到接触焊盘136的电连接。
在PoP半导体组件188被安装到衬底126之后，倒装芯片PoP组件190被倒转，底表面132和凸块140面向上，如图5k中所示。滴涂工具194通过穿孔开口138（或穿孔开口142）将底部填充剂材料196（例如环氧树脂）从衬底126的底表面132分配到半导体管芯120和衬底126之间的区域。因为穿孔开口138相对于半导体管芯120位于中心，所以底部填充剂材料196从开口138的中心位置被均匀和一致地分布到管芯的周边。可以控制被分配的底部填充剂材料196的量、以及底部填充剂材料的分布以最小化或消除渗出并且减少底部填充剂材料中的空隙形成。当底部填充剂材料196接近或到达半导体管芯120的周边时，停止或中止从滴涂工具194分配底部填充剂材料196。
图6示出在底部填充剂材料的固化以及电子测试之后的倒装芯片PoP封装190。由于底部填充剂材料196从半导体管芯120在衬底126上的置放中心的位置被向外分配到管芯的所有侧，底部填充剂材料均匀分布在管芯和衬底之间。底部填充剂材料196应当同时到达半导体管芯120的周边周围的所有侧。半导体管芯120没有一个侧会具有长的填充物宽度。通过最小化或消除底部填充剂材料渗出，减少了电互连缺陷。开口138也减小了内部应力并且增加了可靠性。在较少底部填充剂渗出的情况下，可以改善I/O密度和布局，即接触焊盘136可以放置得更靠近半导体管芯120的占用空间。
虽然已经详细说明本发明的一个或多个实施例，但是本领域技术人员将理解的是，在不脱离由下列权利要求所阐述的本发明的范围的情况下可以对那些实施例进行变型和修改。

Claims (25)

1.一种制造半导体器件的方法，包括：
提供倒装芯片半导体管芯和第一衬底；
在第一衬底中在倒装芯片半导体管芯到第一衬底的置放中心的位置中形成开口；
在第一衬底中的开口上将倒装芯片半导体管芯安装到第一衬底；
将多个半导体管芯安装到第二衬底；
在所述多个半导体管芯和第二衬底上沉积密封剂；
将第二衬底安装到第一衬底；
通过倒装芯片半导体管芯和第一衬底之间的第一衬底中的开口分配底部填充剂材料；以及
当底部填充剂材料接近或到达倒装芯片半导体管芯的周边时停止底部填充剂材料的分配以减少底部填充剂材料的渗出。
2.根据权利要求1的方法，进一步包括在第一衬底中形成多个开口，所述多个开口均匀地分布在倒装芯片半导体管芯到第一衬底的中心置放位置周围。
3.根据权利要求1的方法，进一步包括：
在第一衬底的表面上形成多个凸块；以及
回流所述凸块以将第二衬底安装到第一衬底。
4.根据权利要求3的方法，进一步包括二次回流所述凸块。
5.根据权利要求1的方法，进一步包括：
在倒装芯片半导体管芯的表面上形成多个凸块；以及
回流所述凸块以将倒装芯片半导体管芯安装到第一衬底。
6.根据权利要求1的方法，进一步包括固化底部填充剂材料。
7.一种制造半导体器件的方法，包括：
提供第一半导体管芯和第一衬底；
在第一衬底中形成开口；
在第一衬底中的开口上将第一半导体管芯安装到第一衬底；
将多个第二半导体管芯安装到第二衬底；
将第二衬底安装到第一衬底；
通过第一半导体管芯和第一衬底之间的第一衬底中的开口分配底部填充剂材料；以及
当底部填充剂材料接近或到达倒装芯片半导体管芯的周边时停止底部填充剂材料的分配。
8.根据权利要求7的方法，其中第一衬底中的开口位于第一半导体管芯到第一衬底的置放位置的中心。
9.根据权利要求7的方法，进一步包括在第一衬底中形成多个开口，所述多个开口均匀地分布在倒装芯片半导体管芯到第一衬底的中心置放位置周围。
10.根据权利要求7的方法，进一步包括在第二半导体管芯和第二衬底上沉积密封剂。
11.根据权利要求7的方法，进一步包括：
在第一衬底的表面上形成多个凸块；以及
回流所述凸块以将第二衬底安装到第一衬底。
12.根据权利要求7的方法，其中第一半导体管芯是倒装芯片半导体管芯。
13.根据权利要求7的方法，进一步包括固化底部填充剂材料。
14.一种制造半导体器件的方法，包括：
提供半导体管芯和衬底；
在第一衬底中形成开口；
在第一衬底中的开口上将第一半导体管芯安装到第一衬底；
提供层叠封装（PoP）半导体组件；
将PoP半导体组件安装到半导体管芯上的衬底；以及
通过半导体管芯和衬底之间的衬底中的开口分配底部填充剂材料。
15.根据权利要求14的方法，进一步包括当底部填充剂材料接近或到达半导体管芯的周边时停止底部填充剂材料的分配。
16.根据权利要求14的方法，其中衬底中的开口位于半导体管芯到衬底的置放位置的中心。
17.根据权利要求14的方法，进一步包括在衬底中形成多个开口，所述多个开口均匀地分布在半导体管芯到衬底的中心置放位置周围。
18.根据权利要求14的方法，进一步包括：
在衬底的表面上形成多个凸块；以及
回流所述凸块以将PoP半导体组件安装到衬底。
19.根据权利要求14的方法，其中半导体管芯是倒装芯片半导体管芯。
20.根据权利要求14的方法，进一步包括固化底部填充剂材料。
21.一种半导体器件，包括：
具有开口的衬底；
被安装到衬底的半导体管芯，其中所述衬底中的开口位于半导体管芯到衬底的置放位置的中心；
被安装到半导体管芯上的衬底的层叠封装（PoP）半导体组件；以及
通过半导体管芯和衬底之间的衬底中的开口分配的底部填充剂材料。
22.根据权利要求21的半导体器件，进一步包括在衬底中形成多个开口，所述多个开口均匀地分布在半导体管芯到衬底的中心置放位置周围。
23.根据权利要求21的半导体器件，其中半导体管芯是倒装芯片半导体管芯。
24.根据权利要求21的半导体器件，进一步包括多个凸块，所述多个凸块形成在衬底的表面上以将PoP半导体组件安装到衬底。
25.根据权利要求21的半导体器件，其中底部填充剂材料被固化。
CN2011101272739A 2010-05-17 2011-05-17 半导体器件及其制造方法 Pending CN102254835A (zh)

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