CN102244012A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN102244012A
CN102244012A CN2011101236198A CN201110123619A CN102244012A CN 102244012 A CN102244012 A CN 102244012A CN 2011101236198 A CN2011101236198 A CN 2011101236198A CN 201110123619 A CN201110123619 A CN 201110123619A CN 102244012 A CN102244012 A CN 102244012A
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semiconductor element
projection
interconnection structure
adhesion layer
carrier
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CN102244012B (zh
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R.A.帕盖拉
林耀剑
J.M.库
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Changdian Integrated Circuit Shaoxing Co ltd
Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明涉及半导体器件及其制造方法。一种具有半导体管芯的半导体器件，所述半导体管芯具有多个形成在第一半导体管芯的表面上的凸块。可渗透粘附层形成在临时载体上。粘附层可以包括多个狭槽。通过将凸块嵌入可渗透粘附层中，半导体管芯被安装到载体。半导体管芯和互连结构可以通过间隙分开。密封剂被沉积在第一半导体管芯上。嵌入可渗透粘附层中的凸块在沉积密封剂时减小第一半导体管芯的移位。载体被除去。互连结构形成在半导体管芯上。互连结构电连接到凸块。导热凸块形成在半导体管芯上，并且热沉被安装到互连结构并且热连接到导热凸块。

Description

半导体器件及其制造方法
技术领域
本发明总体上涉及半导体器件，并且更具体地说涉及半导体器件和在密封期间将形成在半导体管芯上的凸块嵌入可渗透粘附层中以减小管芯移位的方法。
背景技术
在现代电子产品中通常会发现有半导体器件。半导体器件在电部件的数量和密度上有变化。分立的半导体器件一般包括一种电部件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器、以及功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件通常包括数百到数百万的电部件。集成半导体器件的实例包括微控制器、微处理器、电荷耦合器件（CCD）、太阳能电池、以及数字微镜器件（DMD）。
半导体器件执行多种功能，例如高速计算、发射和接收电磁信号、控制电子器件、将日光转换成电、以及为电视显示器生成可视投影。在娱乐、通信、功率转换、网络、计算机、以及消费品领域中有半导体器件的存在。在军事应用、航空、汽车、工业控制器、以及办公设备中也有半导体器件的存在。
半导体器件利用半导体材料的电特性。半导体材料的原子结构允许通过施加电场或基极电流（base current）或者通过掺杂工艺来操纵（manipulated）它的导电性。掺杂把杂质引入半导体材料中以操纵和控制半导体器件的导电性。
半导体器件包括有源和无源电结构。有源结构（包括双极和场效应晶体管）控制电流的流动。通过改变掺杂水平并且施加电场或基极电流，晶体管促进或限制电流的流动。无源结构（包括电阻器、电容器、和电感器）产生执行多种电功能所必需的电压和电流之间的关系。无源和有源结构被电连接以形成电路，所述电路能够使半导体器件执行高速计算和其它有用的功能。
通常利用两个复杂的制造工艺来制造半导体器件，即前端制造和后端制造，每个可能包括数百个步骤。前端制造包括在半导体晶片的表面上形成多个管芯。每个管芯通常相同并且包括通过电连接有源和无源部件形成的电路。后端制造包括从已完成的晶片单体化（singulating）单个管芯并且封装管芯以提供结构支撑和环境隔离。
半导体制造的一个目标是制造更小的半导体器件。更小的半导体器件通常消耗更少功率、具有更高的性能、并且能够被更有效地制造。另外，更小的半导体器件具有更小的占地面积（footprint），其对于更小的最终产品而言是期望的。通过改善导致产生具有更小、更高密度的有源和无源部件的管芯的前端工艺可以实现更小的管芯尺寸。通过改善电互连和封装材料，后端工艺可以产生具有更小占地面积的半导体器件封装。
在扇出型晶片级芯片规模封装（FO-WLCSP）中，半导体管芯通常被安装到具有粘附层的临时支撑载体。密封剂或模塑料被沉积在半导体管芯上用于免受外部元件和污染物的影响的环境保护。当密封剂被沉积在管芯周围时密封工艺把力强加在半导体管芯上。在密封期间载体上的粘附层可能不足以将半导体管芯保持在原位。所述力可能使半导体管芯垂直或横向移位或移动。
在密封之后，临时载体和粘附层被除去并且装配互连结构被形成在半导体管芯和密封剂上。必须通过互连结构的绝缘层形成多个通孔以制造到半导体管芯上的接触焊盘的电连接。所述通孔通过机械钻孔或激光切割形成。通孔形成经常会在接触焊盘上留下残余物和其它污染物，这可能干扰电连接并且降低电性能。
发明内容
存在对在密封期间减小半导体管芯的移位并且避免在管芯上的接触焊盘上形成通孔的需要。因此，在一个实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供临时载体，在临时载体上形成可渗透粘附层，提供具有多个凸块的第一半导体管芯，所述凸块形成在第一半导体管芯的表面上，通过将所述凸块嵌入到可渗透粘附层中来将第一半导体管芯安装到临时载体，以及在第一半导体管芯上沉积密封剂。被嵌入到可渗透粘附层中的凸块在沉积密封剂时减小第一半导体管芯的移位。该方法进一步包括以下步骤：除去临时载体和可渗透粘附层，以及在半导体管芯上形成互连结构。所述互连结构被电连接到凸块。
在另一个实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供载体，在载体上形成粘附层，提供具有多个凸块的第一半导体管芯，所述凸块形成在第一半导体管芯的表面上，通过将所述凸块嵌入到粘附层中来将第一半导体管芯安装到载体，在第一半导体管芯上沉积密封剂，除去载体，以及在半导体管芯上形成互连结构。
在另一个实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供具有多个凸块的第一半导体管芯，所述凸块形成在第一半导体管芯的表面上，将第一半导体管芯的凸块嵌入到粘附层中，在第一半导体管芯上沉积密封剂，以及在半导体管芯上形成互连结构。
在另一个实施例中，本发明是一种半导体器件，该半导体器件包括粘附层和具有多个凸块的第一半导体管芯，所述凸块形成在第一半导体管芯的表面上。所述凸块被嵌入粘附层中。密封剂被沉积在第一半导体管芯上。互连结构被形成在半导体管芯上。
附图说明
图1示出具有安装到其表面的不同类型封装的PCB；
图2a-2c示出安装到所述PCB的典型半导体封装的更多细节；
图3a-3g示出在密封期间将形成在半导体管芯上的凸块嵌入可渗透粘附层中以减小管芯移位的过程；
图4示出具有嵌入到装配互连结构内的凸块的半导体管芯；
图5a-5f示出利用半导体管芯和互连结构之间的间隙将凸块嵌入可渗透粘附层中的过程；
图6示出具有被嵌入互连结构以及半导体管芯和互连结构之间的间隙内的凸块的半导体管芯；
图7a-7h示出将凸块嵌入形成在粘附层中的狭槽中的过程；
图8a-8d示出将凸块嵌入形成在粘附层（所述粘附层保留在互连结构上）中的狭槽中的过程；
图9示出具有嵌入互连结构内的伪凸块的半导体管芯；
图10示出具有嵌入互连结构内的导热凸块的半导体管芯；
图11示出具有安装到互连结构的导热凸块和热沉的半导体管芯；
图12示出具有嵌入互连结构内的大凸块的半导体管芯；
图13示出具有形成在互连结构内的RDL的半导体管芯；以及
图14示出被安装到互连结构的第二半导体管芯。
具体实施方式
参考附图在下列描述中的一个或多个实施例中描述本发明，在附图中相似的数字表示相同或类似的元件。虽然根据用来实现本发明的目的的最佳方式描述本发明，但是本领域技术人员将理解的是，它旨在覆盖可以被包含在由被下列公开和各图所支持的所附权利要求及其等效物限定的本发明的精神和范围内的替代物、变型、和等效物。
一般利用两个复杂的制造工艺制造半导体器件：前端制造和后端制造。前端制造包括在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包括有源和无源电部件，所述有源和无源电部件被电连接以形成功能电路。有源电部件，例如晶体管和二极管，具有控制电流的流动的能力。无源电部件，例如电容器、电感器、电阻器、和变压器，产生执行电路功能所必需的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、刻蚀、和平面化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过例如离子注入或热扩散的技术将杂质引入到半导体材料中。所述掺杂工艺改变有源器件中的半导体材料的导电性，将半导体材料转变成绝缘体、导体，或响应于电场或基极电流动态改变半导体材料导电性。晶体管包括有变化的掺杂类型和程度的区域，所述区域根据需要被设置为使晶体管能够在施加电场或基极电流时促进或限制电流的流动。
通过具有不同电特性的材料的层形成有源和无源部件。所述层可以通过部分地由被沉积的材料的类型决定的多种沉积技术形成。例如，薄膜沉积可以包括化学汽相沉积（CVD）、物理汽相沉积（PVD）、电解电镀、以及无电极电镀（electroless plating）工艺。每个层通常被图案化以形成有源部件、无源部件、或部件之间的电连接的各部分。
可以利用光刻图案化所述层，所述光刻包括在将被图案化的层上沉积光敏材料，例如光致抗蚀剂。利用光将图案从光掩模转移到光致抗蚀剂。利用溶剂将经受光的光致抗蚀剂图案部分除去，暴露将被图案化的下层的各部分。光致抗蚀剂的剩余物被除去，留下被图案化的层。可替换地，利用例如无电极电镀或电解电镀的技术通过直接将材料沉积到通过先前的沉积/刻蚀工艺形成的区域或空隙中来图案化一些类型的材料。
在现有图案上沉积材料的薄膜可能会放大下面的图案并且引起不均匀的平面。需要均匀的平面来制造更小和更密集包装的有源和无源部件。可以利用平面化从晶片的表面除去材料和制造均匀平面。平面化包括利用抛光垫抛光晶片的表面。在抛光期间，磨料和腐蚀性化学品被添加到晶片的表面。组合的磨料机械作用和化学品腐蚀作用除去了任何不规则的表面形貌（topography），产生均匀的平面。
后端制造指的是将已完成的晶片切割或单体化成单个管芯，并且然后封装管芯用于结构支撑和环境隔离。为单体化管芯，沿被叫做划片街区（saw street）或划线的晶片非功能区域刻划和断开所述晶片。利用激光切割工具或锯条来单体化晶片。在单体化之后，单个管芯被安装到封装衬底，所述封装衬底包括用来与其它系统部件互连的引脚或接触焊盘。形成在半导体管芯上的接触焊盘然后被连接到封装内的接触焊盘。可以利用焊料凸块、柱形凸块（stud bump）、导电胶、或线结合（wirebond）来制作电连接。密封剂或其它成型材料被沉积到封装上以提供物理支撑和电隔离。已完成的封装然后被插入电系统中并且半导体器件的功能可以用到其它系统部件。
图1示出具有芯片载体衬底或印刷电路板（PCB）52的电子器件50，所述芯片载体衬底或印刷电路板（PCB）52具有多个安装在它的表面上的半导体封装。电子器件50可以具有一种半导体封装、或多种半导体封装，这取决于应用。为了说明的目的，在图1中示出不同类型的半导体封装。
电子器件50可以是利用半导体封装来执行一个或多个电功能的独立系统。可替换地，电子器件50可以是更大系统的子部件。例如，电子器件50可以是能被插入计算机中的图形卡、网络接口卡、或其它信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、RF电路、分立器件、或其它半导体管芯或电部件。
在图1中，PCB 52提供普通的衬底用于安装在PCB上的半导体封装的结构支撑和电互连。利用蒸发、电解电镀、无电极电镀、丝网印刷、或其它合适的金属沉积工艺将导电信号迹线（trace）54形成在PCB 52的表面上或各层内。信号迹线54提供半导体封装、安装的部件、以及其它外部系统部件中的每一个之间的电通信。迹线54也将电源和地连接提供给半导体封装中的每一个。
在一些实施例中，半导体器件可以具有两个封装级。第一级封装是用来将半导体管芯以机械和电的方式附着到中间载体的技术。第二级封装包括将所述中间载体以机械和电的方式附着到PCB。在其它实施例中，半导体器件可以仅具有第一级封装，其中管芯被以机械和电的方式直接安装到PCB。
为了说明的目的，几种第一级封装，包括线结合封装56和倒装芯片58，被示出在PCB 52上。另外，几种第二级封装，包括球栅阵列（BGA）60、凸块芯片载体（BCC）62、双列直插式封装（DIP）64、岸面栅格阵列（land grid array，LGA）66、多芯片模块（MCM）68、四侧无引脚扁平封装（quad flat non-leaded package，QFN）70、以及四侧扁平封装72被示出安装在PCB 52上。根据系统要求，利用第一和第二级封装形式的任何组合配置的半导体封装的任何组合、以及其它电子部件，可以被连接到PCB 52。在一些实施例中，电子器件50包括单个附着的半导体封装，虽然其它实施例要求多互连封装。通过在单个衬底上组合一个或多个半导体封装，制造商可以将预先制作的部件并入电子器件和系统中。因为所述半导体封装包括复杂功能，所以可以利用更便宜的部件和流水线制造工艺来制造电子器件。所得到的器件较少可能失效并且制造起来花费较少，对用户而言导致更低的成本。
图2a-2c示出示范性半导体封装。图2a示出安装在PCB 52上的DIP 64的更多细节。半导体管芯74包括包含模拟或数字电路的有源区，所述模拟或数字电路被实现为根据管芯的电设计形成在管芯内并且被电互连的有源器件、无源器件、导电层、和介电层。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及形成在半导体管芯74的有源区内的其它电路元件。接触焊盘76是导电材料（例如铝（AL）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）、或银（Ag））的一个或多个层，并且电连接到形成在半导体管芯74内的电路元件。在DIP 64的组装期间，利用金硅共晶层或粘附材料（例如热的环氧或环氧树脂）将半导体管芯74安装到中间载体78。封装体包括绝缘封装材料，例如聚合物或陶瓷。导体引线80和线结合82在半导体管芯74和PCB 52之间提供电互连。密封剂84被沉积在封装上用于通过防止湿气与粒子进入所述封装以及污染管芯74或线结合82来进行环境保护。
图2b示出安装在PCB 52上的BCC 62的更多细节。半导体管芯88利用底层填充材料或环氧树脂粘附材料92被安装到载体90上。线结合94在接触焊盘96和98之间提供第一级封装互连。模塑料或密封剂100被沉积在半导体管芯88和线结合94上以为所述器件提供物理支撑和电隔离。接触焊盘102利用电解电镀或无电极电镀这样合适的金属沉积形成在PCB 52的表面上以防止氧化。接触焊盘102电连接到PCB 52中的一个或多个导电信号迹线54。凸块104被形成在BCC 62的接触焊盘98与PCB 52的接触焊盘102之间。
在图2c中，利用倒装芯片型第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区108包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计形成的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及在有源区108内的其它电路元件。半导体管芯58通过凸块110被电连接和机械连接到载体106。
BGA 60 利用凸块112电连接和机械连接到具有BGA型第二级封装的PCB 52。半导体管芯58通过凸块110、信号线114、以及凸块112电连接到导电信号迹线54。模塑料或密封剂116被沉积在半导体管芯58和载体106上以为所述器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电轨迹的短导电路径以便减小信号传播距离、降低电容、并且改善总的电路性能。在另一个实施例中，半导体管芯58可以在没有中间载体106的情况下利用倒装芯片型第一级封装被以机械和电的方式直接连接到PCB 52。
相对于图1和2a-2c，图3a-3g示出在密封期间将形成在半导体管芯上的凸块嵌入可渗透粘附层中以减小管芯移位的过程。图3a示出包括用于结构支撑的牺牲基底材料（例如硅、聚合物、聚合物复合材料、金属、陶瓷、玻璃、玻璃纤维环氧树脂、氧化铍、或其它合适的低成本、刚性材料）的临时衬底或载体120。可渗透粘附层或胶带122被施加在载体120上。可渗透粘附层122可以是耐热和机械应力的单或多层聚合物，例如b阶段（b-staged）可固化环氧树脂。
在图3b中，半导体管芯124具有有源表面126，所述有源表面126包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面126内的其它电路元件以实现模拟电路或数字电路，例如数字信号处理器（DSP）、ASIC、存储器、或其它信号处理电路。半导体管芯124也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。
利用PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在有源表面126上形成导电层128。导电层128可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层128用作电连接到有源表面126上的电路的接触焊盘。
利用蒸发、电解电镀、无电极电镀、球滴、或丝网印刷工艺在接触焊盘128上沉积导电凸块材料。所述凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到接触焊盘128。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块130。在一些应用中，凸块130二次回流以改善到接触焊盘128的电连接。凸块也可以被压缩结合到接触焊盘128。
利用施加到后表面132的力F将半导体管芯124安装到载体120以使凸块130渗透到粘附层122中。在有源表面126接近或接触界面层122的顶表面后去除力F。图3c示出利用嵌入可渗透粘附层122中的凸块130安装到载体120的所有半导体管芯124。凸块130可以或可以不接触载体120的表面。可渗透粘附层122被固化以使粘附层变硬并且牢固地保持凸块130。
在图3d中，利用浆料印刷（paste printing）、压缩模塑、传递模塑、液体密封剂模塑、真空层压、旋涂、或其它合适的施加器（applicator）在半导体管芯124和载体120上沉积密封剂或模塑料134。密封剂134可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂134不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。
在凸块130被嵌入可渗透粘附层122中并且粘附层被固化的情况下，半导体管芯124在沉积密封剂134期间保持不动。嵌入的凸块130将半导体管芯124牢固地保持在原位，在密封剂134被沉积和固化时减小了管芯的横向或垂直移位。如果可渗透粘附层122的玻璃化转变温度（Tg）小于密封剂134的Tg，则粘附层可以与密封剂同时被固化。
在图3e中，通过化学腐蚀、机械剥离、CMP、机械研磨、热烘、UV光、激光扫描、或湿法脱模来除去临时载体120和可渗透粘附层122。凸块130从接触焊盘128被暴露。
在图3f中，底侧装配互连结构136形成在半导体管芯124的有源表面126和密封剂134上。装配互连结构136包括利用图案化和金属沉积工艺（例如溅射、电解电镀、和无电极电镀）形成的导电层138。导电层138可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层138的一部分被电连接到半导体管芯124的凸块130和接触焊盘128。导电层138的其它部分可以根据半导体器件的设计和功能是电共有的（electrically common）或被电隔离。
装配互连结构136进一步包括绝缘或钝化层140，所述绝缘或钝化层140形成在导电层138之间并且包括一层或多层的二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、五氧化二钽（Ta2O5）、氧化铝（Al2O3）、或具有类似绝缘和结构特性的其它材料。绝缘层140利用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化形成。凸块130被嵌入绝缘层140内。
在图3g中，使用蒸发、电解电镀、无电极电镀、球滴或丝网印刷工艺在装配互连结构136上沉积导电凸块材料并将导电凸块材料电连接到导电层138。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层138。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块142。在一些应用中，凸块142二次回流以改善到导电层138的电接触。所述凸块也可以被压缩结合到导电层138。凸块142表示一种可以形成在导电层138上的互连结构。所述互连结构也可以使用结合线、柱形凸块、微凸块、或其它电互连。
利用锯条或激光切割工具144将半导体管芯124单体化成单个FO-WLCSP 146。
图4示出单体化之后的FO-WLCSP 146。半导体管芯124电连接到装配互连结构136和凸块142。利用嵌入可渗透粘附层122中的凸块130，半导体管芯124在沉积密封剂134期间牢固地保持在原位。嵌入的凸块130将半导体管芯124牢固地保持在原位，在密封剂134被沉积和固化时减小了管芯的横向或垂直移位。通过消除如背景技术中所述的在互连结构中形成可湿的接触焊盘或通孔以暴露接触焊盘的需要，嵌入的凸块130还简化了制造工艺。
在另一个实施例中，从图3b继续，半导体管芯124利用施加到后表面132的力F被安装到载体120以使凸块130渗透到粘附层122中。在这种情况下，凸块130透入粘附层122至这样的深度：该深度使有源表面126从可渗透粘附层122的顶表面移动了间隙148，如图5a中所示。图5b示出利用嵌入可渗透粘附层122中的凸块130安装到载体120的所有半导体管芯124，同时在有源表面126和粘附层之间留下间隙148。凸块130可以或可以不接触载体120的表面。可渗透粘附层122被固化以使粘附层变硬并且牢固地保持凸块130。
在图5c中，利用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、旋涂、或其它合适的施加器在半导体管芯124和载体120上沉积密封剂或模塑料150。密封剂150填充有源表面126和可渗透粘附层122之间的间隙148。密封剂150可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂150不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。
在凸块130被嵌入可渗透粘附层122中并且粘附层被固化的情况下，半导体管芯124在沉积密封剂150期间保持不动。嵌入的凸块130将半导体管芯124牢固地保持在原位，在密封剂150被沉积和固化时减小了管芯的横向或垂直移位。如果可渗透粘附层122的Tg小于密封剂150的Tg，则粘附层可以与密封剂同时被固化。
在图5d中，通过化学腐蚀、机械剥离、CMP、机械研磨、热烘、UV光、激光扫描、或湿法脱模来除去临时载体120和可渗透粘附层122。密封剂150保持覆盖有源表面126并且充当半导体管芯124和装配互连结构152之间的应力消除缓冲器。凸块130从密封剂150暴露。
在图5e中，底侧装配互连结构152形成在密封剂150上。装配互连结构152包括利用图案化和金属沉积工艺（例如溅射、电解电镀、和无电极电镀）形成的导电层154。导电层154可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层154的一部分被电连接到半导体管芯124的凸块130和接触焊盘128。导电层154的其它部分可以根据半导体器件的设计和功能是电共有的或被电隔离。
装配互连结构152进一步包括绝缘或钝化层156，所述绝缘或钝化层156形成在导电层154之间并且包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。绝缘层156利用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化形成。凸块130被部分嵌入绝缘层156内。
在图5f中，使用蒸发、电解电镀、无电极电镀、球滴或丝网印刷工艺在装配互连结构152上沉积导电凸块材料并将导电凸块材料电连接到导电层154。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层154。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块158。在一些应用中，凸块158二次回流以改善到导电层154的电接触。所述凸块也可以被压缩结合到导电层154。凸块158表示一种可以形成在导电层154上的互连结构。所述互连结构也可以使用结合线、柱形凸块、微凸块、或其它电互连。
利用锯条或激光切割工具160将半导体管芯124单体化成单个FO-WLCSP 162。
图6示出单体化之后的FO-WLCSP 162。半导体管芯124电连接到装配互连结构152和凸块158。利用嵌入可渗透粘附层122中的凸块130，半导体管芯124在沉积密封剂150期间牢固地保持在原位。嵌入的凸块130将半导体管芯124牢固地保持在原位，在密封剂150被沉积和固化时减小了管芯的横向或垂直移位。通过消除如背景技术中所述的在互连结构中形成可湿的接触焊盘或通孔以暴露接触焊盘的需要，嵌入的凸块130还简化了制造工艺。在半导体管芯124和可渗透粘附层122之间具有间隙148的情况下，密封剂150覆盖有源表面126以在半导体管芯和装配互连结构之间提供应力消除。
图7a示出具有临时衬底或载体170的另一个实施例，所述临时衬底或载体170包括用于结构支撑的牺牲基底材料，例如硅、聚合物、聚合物复合材料、金属、陶瓷、玻璃、玻璃纤维环氧树脂、氧化铍、或其它合适的低成本、刚性材料。粘附层或胶带172被施加在载体170上。粘附层172可以是耐热和机械应力的单或多层聚合物，例如b阶段可固化环氧树脂。
通过机械钻孔、刻蚀、或激光切割在粘附层172中形成多个开口或狭槽173。狭槽173对应于形成在将被安装到载体170的半导体管芯174上的凸块180的位置并且可以用作对准标记，避免了对精确结合设备的需要。狭槽173的深度基本上等于、或者稍微大于或小于凸块180的高度，并且狭槽173的宽度基本上等于、或者稍微小于凸块180的宽度，以在凸块和粘附层122之间形成紧密结合。可选的图案化的膏剂或胶175可以被沉积到狭槽173中用于到凸块180的更好粘附，如图7b中所示。
在图7c中，半导体管芯174具有有源表面176，所述有源表面176包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面176内的其它电路元件以实现模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯174也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。
利用PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在有源表面126上形成导电层178。导电层178可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层178用作电连接到有源表面176上的电路的接触焊盘。
利用蒸发、电解电镀、无电极电镀、球滴、或丝网印刷工艺在接触焊盘178上沉积导电凸块材料。所述凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到接触焊盘178。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块180。在一些应用中，凸块180二次回流以改善到接触焊盘178的电连接。凸块也可以被压缩结合到接触焊盘178。
利用施加到后表面181的力F，半导体管芯174被对准并且被安装到载体170以使凸块180渗透到粘附层122的狭槽173中。在有源表面176接近或接触界面层172的顶表面后去除力F。图7d示出利用嵌入粘附层172的狭槽173内的凸块180安装到载体170的所有半导体管芯174。可渗透粘附层172被固化以使粘附层变硬并且牢固地保持凸块180。
在图7e中，利用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、旋涂、或其它合适的施加器在半导体管芯174和载体170上沉积密封剂或模塑料184。密封剂184可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂184不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。
在凸块180被嵌入粘附层172中并且粘附层被固化的情况下，半导体管芯174在沉积密封剂184期间保持不动。嵌入的凸块180将半导体管芯174牢固地保持在原位，在密封剂184被沉积和固化时减小了管芯的横向或垂直移位。如果可渗透粘附层172的Tg小于密封剂184的Tg，则粘附层可以与密封剂同时被固化。
在图7f中，通过化学腐蚀、机械剥离、CMP、机械研磨、热烘、UV光、激光扫描、或湿法脱模来除去临时载体170和粘附层172。凸块180从接触焊盘178被暴露。
在图7g中，底侧装配互连结构186形成在半导体管芯174的有源表面176和密封剂184上。装配互连结构186包括利用图案化和金属沉积工艺（例如溅射、电解电镀、和无电极电镀）形成的导电层188。导电层188可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层188的一部分被电连接到半导体管芯174的凸块180和接触焊盘178。导电层188的其它部分可以根据半导体器件的设计和功能是电共有的或被电隔离。
装配互连结构186进一步包括绝缘或钝化层190，所述绝缘或钝化层190形成在导电层188之间并且包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。绝缘层190利用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化形成。凸块180被嵌入绝缘层190内。
在图7h中，使用蒸发、电解电镀、无电极电镀、球滴、或丝网印刷工艺在装配互连结构186上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层188。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块192。在一些应用中，凸块192二次回流以改善到导电层188的电接触。所述凸块也可以被压缩结合到导电层188。凸块192表示一种可以形成在导电层188上的互连结构。所述互连结构也可以使用结合线、柱形凸块、微凸块、或其它电互连。
利用锯条或激光切割工具193将半导体管芯174单体化成单个FO-WLCSP。
在另一个实施例中，从图7d继续，利用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、旋涂、或其它合适的施加器在半导体管芯174和载体170上沉积密封剂或模塑料194，如图8a中所示。密封剂194可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂194不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。
在图8b中，通过化学腐蚀、机械剥离、CMP、机械研磨、热烘、UV光、激光扫描、或湿法脱模来除去临时载体170。在该情况下，粘附层172保留在有源表面176和凸块180上。
在图8c中，底侧装配互连结构196形成在半导体管芯174的有源表面176和密封剂184上。装配互连结构196包括利用图案化和金属沉积工艺（例如溅射、电解电镀、和无电极电镀）形成的导电层198。导电层198可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层198的一部分被电连接到半导体管芯174的凸块180和接触焊盘178。导电层198的其它部分可以根据半导体器件的设计和功能是电共有的或被电隔离。
装配互连结构196进一步包括绝缘或钝化层200，所述绝缘或钝化层200形成在导电层198之间并且包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。绝缘层200利用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化形成。
在图8d中，使用蒸发、电解电镀、无电极电镀、球滴、或丝网印刷工艺在装配互连结构196上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层198。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块202。在一些应用中，凸块202二次回流以改善到导电层198的电接触。所述凸块也可以被压缩结合到导电层198。凸块202表示一种可以形成在导电层198上的互连结构。所述互连结构也可以使用结合线、柱形凸块、微凸块、或其它电互连。
利用锯条或激光切割工具204将半导体管芯174单体化成单个FO-WLCSP。
图9示出一个实施例，从图4继续，多个伪凸块210形成在有源表面126上。伪凸块210与凸块130同时形成并且透入粘附层122，如图3b中所述。互连结构136形成在伪凸块210上使得伪凸块被嵌入绝缘层140内。伪凸块210不具有到有源表面126内的电路或到导电层138的电连接，而是在半导体管芯124和装配互连结构136之间提供附加机械式联锁强度。
图10示出一个实施例，从图4继续，多个通孔被形成为通过互连结构136。所述通孔被填充了Al、Cu、或具有高热导率的其他材料以形成导热通孔212。凸块142a电连接到导电层138用于功率供给和信号传输。导热通孔212用冶金的方法连接到凸块142b以提供热耗散路径来将热从半导体管芯124带走。
图11示出一个实施例，从图10继续，热沉或散热器214被安装到装配互连结构136并且被连接到导热通孔212。PCB 216被安装到热沉214和凸块142。导热通孔212、热沉214、和PCB 216的组合提供从半导体管芯带走热的热耗散路径。可选的热界面材料（TIM）218可以形成在热沉212的一个或两个表面上。TIM 218可以是氧化铝、氧化锌、氮化硼、或粉状银。TIM 218帮助散布和耗散由半导体管芯124生成的热。
图12示出一个实施例，从图4继续，凸块220形成在有源表面126上。为了更低的电阻、更大的电流载送能力、以及改良的电性能，凸块220具有比凸块130大的截面面积。
图13示出一个实施例，从图6继续，再分配层（RDL）222形成在密封剂150上并且电连接到装配互连结构152内的导电层154。RDL 222电连接在凸块130和凸块158之间。
图14示出一个实施例，从图4继续，半导体管芯224具有有源表面226，所述有源表面226包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面226内的其它电路元件以实现模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯224也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。多个接触焊盘228形成在有源表面226上并且电连接到有源表面上的电路。多个凸块230形成在接触焊盘228上。通过电连接凸块230到导电层138，半导体管芯224被安装到装配互连结构136。分立的无源或有源部件也可以被安装到装配互连结构136。
虽然已经详细说明本发明的一个或多个实施例，但是本领域技术人员将理解的是，在不脱离由下列权利要求所阐述的本发明的范围的情况下可以对那些实施例进行变型和修改。

Claims (25)

1.一种制造半导体器件的方法，包括：
提供临时载体；
在临时载体上形成可渗透粘附层；
提供具有多个凸块的第一半导体管芯，所述凸块形成在第一半导体管芯的表面上；
通过将所述凸块嵌入到可渗透粘附层中来将第一半导体管芯安装到临时载体；
在第一半导体管芯上沉积密封剂，其中被嵌入到可渗透粘附层中的凸块在沉积密封剂时减小第一半导体管芯的移位；
除去临时载体和可渗透粘附层；以及
在半导体管芯上形成互连结构，所述互连结构被电连接到所述凸块。
2.根据权利要求1的方法，进一步包括将凸块嵌入互连结构中。
3.根据权利要求1的方法，进一步包括在第一半导体管芯的表面和互连结构之间提供间隙。
4.根据权利要求1的方法，进一步包括在第一半导体管芯的表面上形成伪凸块，所述伪凸块被嵌入互连结构中。
5.根据权利要求1的方法，进一步包括：
在第一半导体管芯的表面上形成导热凸块；以及
安装热沉到互连结构，所述热沉被热连接到导热凸块。
6.根据权利要求1的方法，进一步包括安装第二半导体管芯或部件到与第一半导体管芯相对的互连结构的表面。
7.一种制造半导体器件的方法，包括：
提供载体；
在载体上形成粘附层；
提供具有多个凸块的第一半导体管芯，所述凸块形成在第一半导体管芯的表面上；
通过将所述凸块嵌入到粘附层中来将第一半导体管芯安装到载体；
在第一半导体管芯上沉积密封剂；
除去载体；以及
在半导体管芯上形成互连结构。
8.根据权利要求7的方法，其中被嵌入粘附层中的凸块在沉积密封剂时减小第一半导体管芯的移位。
9.根据权利要求7的方法，进一步包括在粘附层中形成多个狭槽。
10.根据权利要求7的方法，进一步包括在第一半导体管芯的表面和互连结构之间提供间隙。
11.根据权利要求7的方法，进一步包括在除去载体之后保留粘附层。
12.根据权利要求7的方法，进一步包括在密封剂上形成再分配层。
13.根据权利要求7的方法，进一步包括安装第二半导体管芯或部件到与第一半导体管芯相对的互连结构的表面。
14.根据权利要求7的方法，其中所述凸块中的第一凸块具有比所述凸块中的第二凸块大的截面面积。
15.一种制造半导体器件的方法，包括：
提供具有多个凸块的第一半导体管芯，所述凸块形成在第一半导体管芯的表面上；
将第一半导体管芯的凸块嵌入到粘附层中；
在第一半导体管芯上沉积密封剂；以及
在半导体管芯上形成互连结构。
16.根据权利要求15的方法，进一步包括：
提供载体；
在载体上形成粘附层；以及
在沉积密封剂之后除去载体。
17.根据权利要求15的方法，进一步包括在粘附层中形成多个狭槽。
18.根据权利要求15的方法，进一步包括：
在第一半导体管芯的表面上形成导热凸块；以及
安装热沉到互连结构，所述热沉被热连接到导热凸块。
19.根据权利要求15的方法，进一步包括安装第二半导体管芯或部件到与第一半导体管芯相对的互连结构的表面。
20.根据权利要求15的方法，进一步包括在密封剂上形成再分配层。
21.一种半导体器件，包括：
粘附层；
具有多个凸块的第一半导体管芯，所述凸块形成在第一半导体管芯的表面上，所述凸块被嵌入粘附层中；
沉积在第一半导体管芯上的密封剂；以及
形成在半导体管芯上的互连结构。
22.根据权利要求21的半导体器件，进一步包括：
形成在第一半导体管芯的表面上的导热凸块；以及
安装到互连结构的热沉，所述热沉被热连接到导热凸块。
23.根据权利要求21的半导体器件，进一步包括形成在密封剂上的再分配层。
24.根据权利要求21的半导体器件，其中粘附层包括多个狭槽。
25.根据权利要求21的半导体器件，进一步包括安装到与第一半导体管芯相对的互连结构的表面的第二半导体管芯或部件。
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WO2017185580A1 (zh) * 2016-04-25 2017-11-02 湘能华磊光电股份有限公司 倒装led芯片集成封装的光源组件结构及其制作方法
CN107611045A (zh) * 2017-09-29 2018-01-19 中芯长电半导体（江阴）有限公司 一种三维芯片封装结构及其封装方法
CN107768342A (zh) * 2016-08-19 2018-03-06 英飞凌科技美国公司 具有用于将电感器连接到一个或一个以上晶体管的预成形电连接部的功率开关封装
US10181423B2 (en) 2012-10-02 2019-01-15 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier in semiconductor packaging
CN109755374A (zh) * 2019-03-20 2019-05-14 中芯长电半导体（江阴）有限公司 晶圆级扇出型led的封装结构及封装方法
CN110326100A (zh) * 2017-01-30 2019-10-11 普利莫1D公司 用于将配线插入到半导体芯片的沟槽中的方法以及用于实现该方法的设备
CN110494975A (zh) * 2017-05-16 2019-11-22 雷索恩公司 氧化接合的晶圆堆叠中的管芯封装
US10515828B2 (en) 2012-10-02 2019-12-24 STATS ChipPAC Pte. Ltd. Method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP
CN110931441A (zh) * 2018-09-19 2020-03-27 力成科技股份有限公司 封装结构及其制造方法
US10777528B2 (en) 2013-01-03 2020-09-15 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming embedded wafer level chip scale packages

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8466997B2 (en) * 2009-12-31 2013-06-18 Stmicroelectronics Pte Ltd. Fan-out wafer level package for an optical sensor and method of manufacture thereof
US8436255B2 (en) * 2009-12-31 2013-05-07 Stmicroelectronics Pte Ltd. Fan-out wafer level package with polymeric layer for high reliability
US8884422B2 (en) * 2009-12-31 2014-11-11 Stmicroelectronics Pte Ltd. Flip-chip fan-out wafer level package for package-on-package applications, and method of manufacture
US20110156240A1 (en) * 2009-12-31 2011-06-30 Stmicroelectronics Asia Pacific Pte. Ltd. Reliable large die fan-out wafer level package and method of manufacture
US8502394B2 (en) * 2009-12-31 2013-08-06 Stmicroelectronics Pte Ltd. Multi-stacked semiconductor dice scale package structure and method of manufacturing same
KR20110124993A (ko) * 2010-05-12 2011-11-18 삼성전자주식회사 반도체 칩 및 이를 포함하는 반도체 패키지 및 반도체 칩의 제조 방법
US8680673B2 (en) * 2010-12-21 2014-03-25 Stmicroelectronics Pte Ltd. Integrated heat pillar for hot region cooling in an integrated circuit
US8890304B2 (en) * 2011-06-08 2014-11-18 Tessera, Inc. Fan-out microelectronic unit WLP having interconnects comprising a matrix of a high melting point, a low melting point and a polymer material
US8597986B2 (en) * 2011-09-01 2013-12-03 Taiwan Semiconductor Manufacturing Co., Ltd. System in package and method of fabricating same
US9013037B2 (en) 2011-09-14 2015-04-21 Stmicroelectronics Pte Ltd. Semiconductor package with improved pillar bump process and structure
US8779601B2 (en) 2011-11-02 2014-07-15 Stmicroelectronics Pte Ltd Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
US8916481B2 (en) 2011-11-02 2014-12-23 Stmicroelectronics Pte Ltd. Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
US9006889B2 (en) * 2011-11-11 2015-04-14 Skyworks Solutions, Inc. Flip chip packages with improved thermal performance
US20130187284A1 (en) * 2012-01-24 2013-07-25 Broadcom Corporation Low Cost and High Performance Flip Chip Package
CN103579128B (zh) * 2012-07-26 2016-12-21 碁鼎科技秦皇岛有限公司 芯片封装基板、芯片封装结构及其制作方法
US8716856B2 (en) * 2012-08-02 2014-05-06 Globalfoundries Singapore Pte. Ltd. Device with integrated power supply
US9287204B2 (en) * 2012-12-20 2016-03-15 Stats Chippac, Ltd. Semiconductor device and method of bonding semiconductor die to substrate in reconstituted wafer form
WO2014136484A1 (ja) * 2013-03-07 2014-09-12 住友ベークライト株式会社 装置、接着剤用組成物、接着シート
TWI514602B (zh) * 2013-03-28 2015-12-21 Zenith Materials Technology Corp Can be a combination of two-way combination of solar modules
US9524958B2 (en) * 2013-06-27 2016-12-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of individual die bonding followed by simultaneous multiple die thermal compression bonding
US9543373B2 (en) 2013-10-23 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
TWI549234B (zh) 2014-01-17 2016-09-11 矽品精密工業股份有限公司 用於接置半導體裝置之層結構及其製法
US9397138B2 (en) * 2014-03-25 2016-07-19 Xintec Inc. Manufacturing method of semiconductor structure
KR102287754B1 (ko) 2014-08-22 2021-08-09 삼성전자주식회사 칩 적층 반도체 패키지
KR102274742B1 (ko) * 2014-10-06 2021-07-07 삼성전자주식회사 패키지 온 패키지와 이를 포함하는 컴퓨팅 장치
US9706668B2 (en) * 2014-10-24 2017-07-11 Samsung Electro-Mechanics Co., Ltd. Printed circuit board, electronic module and method of manufacturing the same
US9831572B2 (en) 2014-12-17 2017-11-28 Avago Technologies General Ip (Singapore) Pte. Ltd. Socketless land grid array
US10515884B2 (en) * 2015-02-17 2019-12-24 Advanced Semiconductor Engineering, Inc. Substrate having a conductive structure within photo-sensitive resin
US9425171B1 (en) * 2015-06-25 2016-08-23 Nvidia Corporation Removable substrate for controlling warpage of an integrated circuit package
TWI733690B (zh) * 2015-08-14 2021-07-21 新加坡商Ｐｅｐ創新私人有限公司 半導體加工方法
SG10201509996UA (en) * 2015-12-04 2017-07-28 Rokko Systems Pte Ltd Improved substrate processing and apparatus
CN105470199A (zh) * 2015-12-09 2016-04-06 华天科技（西安）有限公司 一种带散热片封装件的分离方法
US11272618B2 (en) 2016-04-26 2022-03-08 Analog Devices International Unlimited Company Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits
US20170330855A1 (en) * 2016-05-13 2017-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. System and Method for Immersion Bonding
US10811334B2 (en) 2016-11-26 2020-10-20 Texas Instruments Incorporated Integrated circuit nanoparticle thermal routing structure in interconnect region
US10529641B2 (en) 2016-11-26 2020-01-07 Texas Instruments Incorporated Integrated circuit nanoparticle thermal routing structure over interconnect region
US11004680B2 (en) 2016-11-26 2021-05-11 Texas Instruments Incorporated Semiconductor device package thermal conduit
US10861763B2 (en) 2016-11-26 2020-12-08 Texas Instruments Incorporated Thermal routing trench by additive processing
US10256188B2 (en) 2016-11-26 2019-04-09 Texas Instruments Incorporated Interconnect via with grown graphitic material
US11676880B2 (en) 2016-11-26 2023-06-13 Texas Instruments Incorporated High thermal conductivity vias by additive processing
WO2018125061A1 (en) * 2016-12-27 2018-07-05 Intel Corporation Stacking multiple dies having dissimilar interconnect structure layout and pitch
IT201700055983A1 (it) 2017-05-23 2018-11-23 St Microelectronics Srl Procedimento per produrre dispositivi a semiconduttore, dispositivo a semiconduttore e circuito corrispondenti
KR102019349B1 (ko) 2017-10-19 2019-09-09 삼성전자주식회사 반도체 패키지
JP7015691B2 (ja) * 2017-12-27 2022-02-03 新光電気工業株式会社 半導体装置
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US11276676B2 (en) * 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
US11721657B2 (en) 2019-06-14 2023-08-08 Stmicroelectronics Pte Ltd Wafer level chip scale package having varying thicknesses
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
KR102643424B1 (ko) * 2019-12-13 2024-03-06 삼성전자주식회사 반도체 패키지
US20230163014A1 (en) * 2020-03-30 2023-05-25 Mitsui Chemicals Tohcello, Inc. Method for manufacturing electronic device
KR20210131548A (ko) 2020-04-24 2021-11-03 삼성전자주식회사 반도체 패키지
KR102338179B1 (ko) * 2020-05-26 2021-12-10 주식회사 에스엘바이오닉스 반도체 발광소자 및 이의 제조방법
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component
JP2022002237A (ja) * 2020-06-19 2022-01-06 日本電気株式会社 量子デバイス及びその製造方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0724289A2 (en) * 1995-01-30 1996-07-31 Matsushita Electric Industrial Co., Ltd. Semiconductor unit package, semiconductor unit packaging method, and encapsulant for use in semiconductor unit packaging
CN101208789A (zh) * 2005-06-29 2008-06-25 皇家飞利浦电子股份有限公司 制造组件的方法及组件
CN101231989A (zh) * 2007-01-25 2008-07-30 南茂科技股份有限公司 增进散热效益的半导体封装载膜与封装构造
US20080213941A1 (en) * 2003-11-10 2008-09-04 Pendse Rajendra D Bump-on-Lead Flip Chip Interconnection
CN101266966A (zh) * 2007-03-16 2008-09-17 日月光半导体制造股份有限公司 多芯片封装模块及其制造方法
CN101308804A (zh) * 2008-07-08 2008-11-19 日月光半导体制造股份有限公司 射频模块的封装结构及其制造方法
US7692297B2 (en) * 2004-07-08 2010-04-06 Nec Electronics Corporation Semiconductor device, semiconductor device module and method of manufacturing the semiconductor device
US20100327465A1 (en) * 2009-06-25 2010-12-30 Advanced Semiconductor Engineering, Inc. Package process and package structure

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5250843A (en) 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
US5161090A (en) * 1991-12-13 1992-11-03 Hewlett-Packard Company Heat pipe-electrical interconnect integration for chip modules
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
JP3073644B2 (ja) * 1993-12-28 2000-08-07 株式会社東芝 半導体装置
US5841193A (en) 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US20010052647A1 (en) * 1998-05-07 2001-12-20 3M Innovative Properties Company Laminated integrated circuit package
SG115455A1 (en) 2002-03-04 2005-10-28 Micron Technology Inc Methods for assembly and packaging of flip chip configured dice with interposer
US6911624B2 (en) 2002-08-23 2005-06-28 Micron Technology, Inc. Component installation, removal, and replacement apparatus and method
DE10240461A1 (de) 2002-08-29 2004-03-11 Infineon Technologies Ag Universelles Gehäuse für ein elektronisches Bauteil mit Halbleiterchip und Verfahren zu seiner Herstellung
DE10240460A1 (de) 2002-08-29 2004-03-11 Infineon Technologies Ag Universelles Halbleitergehäuse mit vorvernetzten Kunststoffeinbettmassen und Verfahren zur Herstellung desselben
US7576436B2 (en) 2002-12-13 2009-08-18 Advanced Semiconductor Engineering, Inc. Structure of wafer level package with area bump
US7152313B2 (en) * 2003-11-26 2006-12-26 Intel Corporation Package substrate for integrated circuit and method of making the substrate
TWI303870B (en) * 2005-12-30 2008-12-01 Advanced Semiconductor Eng Structure and mtehod for packaging a chip
KR100800473B1 (ko) * 2006-06-30 2008-02-04 삼성전자주식회사 재배선 칩 패드를 갖는 적층 칩 및 이를 이용한 적층 칩패키지
TWI313037B (en) * 2006-12-12 2009-08-01 Siliconware Precision Industries Co Ltd Chip scale package structure and method for fabricating the same
KR100891805B1 (ko) * 2007-05-25 2009-04-07 주식회사 네패스 웨이퍼 레벨 시스템 인 패키지 및 그 제조 방법
US7868445B2 (en) 2007-06-25 2011-01-11 Epic Technologies, Inc. Integrated structures and methods of fabrication thereof with fan-out metallization on a chips-first chip layer
JP2009105209A (ja) 2007-10-23 2009-05-14 Nec Corp 電子装置及びその製造方法
US7812449B2 (en) 2008-09-09 2010-10-12 Stats Chippac Ltd. Integrated circuit package system with redistribution layer
US7666709B1 (en) 2008-12-10 2010-02-23 Stats Chippac, Ltd. Semiconductor device and method of placing semiconductor die on a temporary carrier using fiducial patterns

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0724289A2 (en) * 1995-01-30 1996-07-31 Matsushita Electric Industrial Co., Ltd. Semiconductor unit package, semiconductor unit packaging method, and encapsulant for use in semiconductor unit packaging
US20080213941A1 (en) * 2003-11-10 2008-09-04 Pendse Rajendra D Bump-on-Lead Flip Chip Interconnection
US7692297B2 (en) * 2004-07-08 2010-04-06 Nec Electronics Corporation Semiconductor device, semiconductor device module and method of manufacturing the semiconductor device
CN101208789A (zh) * 2005-06-29 2008-06-25 皇家飞利浦电子股份有限公司 制造组件的方法及组件
CN101231989A (zh) * 2007-01-25 2008-07-30 南茂科技股份有限公司 增进散热效益的半导体封装载膜与封装构造
CN101266966A (zh) * 2007-03-16 2008-09-17 日月光半导体制造股份有限公司 多芯片封装模块及其制造方法
CN101308804A (zh) * 2008-07-08 2008-11-19 日月光半导体制造股份有限公司 射频模块的封装结构及其制造方法
US20100327465A1 (en) * 2009-06-25 2010-12-30 Advanced Semiconductor Engineering, Inc. Package process and package structure

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10181423B2 (en) 2012-10-02 2019-01-15 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier in semiconductor packaging
US11961764B2 (en) 2012-10-02 2024-04-16 STATS ChipPAC Pte. Ltd. Semiconductor device and method of making a wafer-level chip-scale package
US11222793B2 (en) 2012-10-02 2022-01-11 STATS ChipPAC Pte. Ltd. Semiconductor device with encapsulant deposited along sides and surface edge of semiconductor die in embedded WLCSP
US11011423B2 (en) 2012-10-02 2021-05-18 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier in semiconductor packaging
US10515828B2 (en) 2012-10-02 2019-12-24 STATS ChipPAC Pte. Ltd. Method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP
CN103915353A (zh) * 2013-01-03 2014-07-09 新科金朋有限公司 半导体器件以及使用标准化载体形成嵌入式晶片级芯片尺寸封装的方法
US11488933B2 (en) 2013-01-03 2022-11-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming embedded wafer level chip scale packages
US11488932B2 (en) 2013-01-03 2022-11-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages
US10777528B2 (en) 2013-01-03 2020-09-15 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming embedded wafer level chip scale packages
US10658330B2 (en) 2013-01-03 2020-05-19 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages
CN103915353B (zh) * 2013-01-03 2019-05-07 新科金朋有限公司 半导体器件以及使用标准化载体形成嵌入式晶片级芯片尺寸封装的方法
US9485868B2 (en) 2013-12-05 2016-11-01 Nantong Fujitsu Microelectronics Co., Ltd. Package structure
CN103745958B (zh) * 2013-12-05 2016-08-17 南通富士通微电子股份有限公司 封装结构
CN103745958A (zh) * 2013-12-05 2014-04-23 南通富士通微电子股份有限公司 封装结构
CN103915355A (zh) * 2013-12-05 2014-07-09 南通富士通微电子股份有限公司 封装结构的形成方法
CN103730428B (zh) * 2013-12-05 2017-09-08 通富微电子股份有限公司 封装结构
US9397070B2 (en) 2013-12-05 2016-07-19 Nantong Fujitsu Microelectronics Co., Ltd. Method for forming package structure
CN103730428A (zh) * 2013-12-05 2014-04-16 南通富士通微电子股份有限公司 封装结构
CN103915355B (zh) * 2013-12-05 2017-01-25 通富微电子股份有限公司 封装结构的形成方法
CN103730429B (zh) * 2013-12-05 2017-06-20 通富微电子股份有限公司 封装结构
US10455751B2 (en) 2016-01-04 2019-10-22 Boe Technology Group Co., Ltd. Maintenance fixture for printed circuit board assembly
CN105578785A (zh) * 2016-01-04 2016-05-11 京东方科技集团股份有限公司 一种治具及其操作方法
WO2017185580A1 (zh) * 2016-04-25 2017-11-02 湘能华磊光电股份有限公司 倒装led芯片集成封装的光源组件结构及其制作方法
CN107768342A (zh) * 2016-08-19 2018-03-06 英飞凌科技美国公司 具有用于将电感器连接到一个或一个以上晶体管的预成形电连接部的功率开关封装
CN110326100A (zh) * 2017-01-30 2019-10-11 普利莫1D公司 用于将配线插入到半导体芯片的沟槽中的方法以及用于实现该方法的设备
CN110326100B (zh) * 2017-01-30 2023-08-15 普利莫1D公司 用于将配线插入到半导体芯片的沟槽中的方法以及用于实现该方法的设备
CN110494975A (zh) * 2017-05-16 2019-11-22 雷索恩公司 氧化接合的晶圆堆叠中的管芯封装
CN107611045A (zh) * 2017-09-29 2018-01-19 中芯长电半导体（江阴）有限公司 一种三维芯片封装结构及其封装方法
CN110931441A (zh) * 2018-09-19 2020-03-27 力成科技股份有限公司 封装结构及其制造方法
CN109755374A (zh) * 2019-03-20 2019-05-14 中芯长电半导体（江阴）有限公司 晶圆级扇出型led的封装结构及封装方法

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Patentee before: STATS ChipPAC Pte. Ltd.

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