CN101266966A - 多芯片封装模块及其制造方法 - Google Patents

多芯片封装模块及其制造方法 Download PDF

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CN101266966A
CN101266966A CNA2007100893158A CN200710089315A CN101266966A CN 101266966 A CN101266966 A CN 101266966A CN A2007100893158 A CNA2007100893158 A CN A2007100893158A CN 200710089315 A CN200710089315 A CN 200710089315A CN 101266966 A CN101266966 A CN 101266966A
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semiconductor element
chip
substrate
encapsulation module
core encapsulation
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CN101266966B (zh
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梁准荣
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Advanced Semiconductor Engineering Inc
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Abstract

一种多芯片封装模块包括第一基板、第一芯片、第一半导体元件、第一封胶以及第二半导体元件。第一芯片设置在第一基板上。倒置的第一半导体元件设置在第一芯片上方。第一封胶包覆第一芯片以及第一半导体元件，第一封胶具有开口而暴露出部分的第一半导体元件。第二半导体元件的底面设置有若干个第一导电凸块，第二半导体元件设置在第一半导体元件上，并位于开口中，第二半导体元件透过这些第一导电凸块与第一半导体元件电性连接。

Description

多芯片封装模块及其制造方法
技术领域
本发明涉及一种封装模块及其制造方法，特别是关于一种多芯片封装模块及其制造方法。
背景技术
现阶段计算机工业的目标包括更高的效能、更低的成本、更小的机身以及更大的集成电路(Integrated circuits，IC)封装密度。随着新一代集成电路产品的问世，新产品的功能更为强大而所需的元件数目却反而减少。
半导体装置是由硅或是砷化镓晶圆经过沉积、微影、扩散、蚀刻及植入等一连串的程序建构而成。通常很多独立的装置会从同一片晶圆制造出来。当这些装置被切割成独立的矩型单元，每一个都成为一个集成电路芯片(IC die)。为了要在芯片和其它电路之间形成接口，通常会将芯片设置在导线架上或是周围有很多引脚的基板上。每一个芯片上都有用以接合的焊垫，可以在打线接合(wire-bonding)过程中让极细的金线或铝线由此连接到导线架的引脚上，或是用于覆晶接合。
覆晶接合(flipped chip attachment)则是将一翻覆的芯片(以下简称覆晶)连接到电路板或是另一基板上。覆晶具有由周围的线路图案或阵列的终端组成的接合表面，用以倒置在基板上。一般来说，覆晶的接合表面通常具有下列电性连接件其中之一：球闸状阵列(Ball grid array，BGA)或是略大于芯片的载体(slightly larger that IC carrier，SLICC)。球闸状阵列(BGA)是一种具有微小焊球阵列的电性连接结构，其设置在覆晶的接合表面用以接合至基板。略大于芯片的载体(SLICC)与球闸状阵列相似，但其焊球直径以及间距较小。
就球闸状阵列(BGA)或略大于芯片的载体(SLICC)而言，焊球或是其它导电球的配置必须是电路板上与之相连的焊垫的镜向设置，如此一来焊球才可以精确地与焊垫相连。透过回焊焊球的方式，覆晶与电路板得以连接在一起。焊球也可以使用导电聚合物或是金凸块替代。
打线接合以及软带接合(TAB attachment)初期通常是将半导体芯片以适当的黏着剂(例如是环氧树脂)黏贴在小电路板的表面。如果是打线接合，便接着将导电一次一条地分别从半导体芯片上的接合垫延伸到电路板上对应的金属引脚或导线末端上。如果是软带接合，则将绝缘软带上承载的金属引脚两端分别黏接到半导体芯片上的接合垫以及电路板上对应的金属引脚或导线末端。最后用封胶包覆导线以及软带上的金属引脚以防止受伤及污染。
然而，在有限的引脚数目、更薄的机身、更轻的重量以及更低的成本的要求下，移动电话、手提电脑或其它消费类产品等可携式电子产品需要更多元的半导体功能以及更好的性能。这样的需求迫使业界必须积极地整合个别功能的半导体芯片，才有办法达成上述的要求。
发明内容
本发明的目的在于提供一种多芯片封装模块及其制造方法，可以将多个芯片设置在其中，让模块的功能强大完整，创造一个最佳化的系统在模块中。
为实现上述目的，本发明提供一种多芯片封装模块包括第一基板、第一芯片、第一半导体元件、第一封胶以及第二半导体元件。第一芯片设置在第一基板上。倒置的第一半导体元件设置在第一芯片上方。第一封胶包覆第一芯片以及第一半导体元件，第一封胶具有开口而暴露出部分的第一半导体元件。第二半导体元件的底面设置有若干个第一导电凸块，第二半导体元件设置在第一半导体元件上，并位于开口中，第二半导体元件透过这些第一导电凸块与第一半导体元件电性连接。
根据本发明的目的，再提出一种多芯片封装模块的制造方法，包括下列步骤：(a)提供第一基板；(b)将第一芯片设置在第一基板上；(c)将第一半导体元件翻覆并设置在第一芯片之上；(d)将第一芯片与第一半导体元件分别电性连接至第一基板；(e)将第一芯片以及第一半导体元件以封胶密封，但形成开口在第一半导体元件上以暴露出部分的第一半导体元件；以及(f)将第二半导体元件的若干个第一导电凸块焊接至第一半导体元件，使得第二半导体元件设置在第一半导体元件上并位于开口中。
与现有技术相比，本发明的多芯片封装模块及其制造方法具有多项优点。由于更多的芯片可以设置在封装模块中，使得封装件的体积可进一步的缩小，并具有较佳的性能。具有多种功能的第二半导体元件可以被组合进多芯片封装模块中以扩充及多元化其功能。此外，由于一旦客户提供订单时，具有特定功能的第二半导体元件马上可以组装在具有基本功能并且预先组装好的半成品封装件上，因此具备特定功能的多芯片封装模块将可以更快速地被制造出来。如此一来，传统上必须利用庞大又复杂的电路设计来实践的功能完整的模块，本发明只要利用弹性化的设计以及组合不同功能芯片就可以让封装模块具有完整的功能与较佳的性能，可以同时加速并简化制造流程。
以下结合附图与实施例对本发明作进一步的说明。
附图说明
图1为本发明第一实施例的多芯片封装模块的剖面图。
图2A～2E为图1多芯片封装模块的制造方法的示意图。
图3为本发明第二实施例的多芯片封装模块的剖面图。
图4A～4E为图3所示多芯片封装模块的制造方法的示意图。
图5为本发明第三实施例的多芯片封装模块的剖面图。
图6A～6D为图5所示多芯片封装模块的制造方法的示意图。
具体实施方式
本发明的多芯片封装模块的顶面包括一倒置的半导体元件，其部分基板裸露以供另一半导体元件设置。本发明就是利用这样的方式让多个芯片得以汇聚在单个封装模块内。
有关本发明的详细说明及技术内容，现就结合附图说明如下：
第一实施例
图1为依照本发明第一实施例的多芯片封装模块的剖面图。本实施例的多芯片封装模块100包括基板110、芯片120、第一半导体元件140、封胶150以及第二半导体元件160。芯片120设置在基板110上，较佳的是芯片120的若干个导电凸块122焊接于基板110，用以电性连接芯片120以及基板110。倒置的第一半导体元件140设置在芯片120上方。封胶150包覆芯片120以及第一半导体元件140，封胶150具有开155而暴露出部分的第一半导体元件140。第二半导体元件160的底面设置有若干个导电凸块168，第二半导体元件160设置在第一半导体元件140上，并位于开155中。第二半导体元件160透过若干个导电凸块168与第一半导体元件140电性连接。
半导体元件可以是次封装件，也就是包括至少一芯片设置在基板上。举例来说，第一半导体元件140是次封装件，至少包括基板142、芯片144以及封胶148。基板142设置在芯片120上方。芯片144设置在基板142上并与基板142电性连接，例如是透过打线接合的方式。封胶148包覆芯片144以及基板142。第一半导体元件140以其底面朝上的方式设置在芯片120上，封胶150的开口155暴露部分的基板142。如图1所示，第一半导体元件140较佳的是再承载另一芯片146或是更多芯片以扩展封装件100的功能。此外，第二半导体元件160也较佳的是次封装件，至少包括基板162、芯片164以及封胶166。基板162的底面设置若干个导电凸块168。芯片164设置在基板162的顶面上，并利用例如是打线接合的方式与基板162电性连接。封胶166包覆芯片164以及基板162。虽然图1中清楚揭示第一半导体元件140以及第二半导体元件160的细部结构，然而多芯片封装模块100内的半导体元件结构并不限定于此。举例来说，第一半导体元件140可以只包括单一芯片，而第二半导体元件160可以包括两个芯片。
进一步的说，另一芯片可以设置在芯片120上并打线接合至基板110。更多的芯片因此可以设置在多芯片封装模块100中，使得模块内的系统功能更为强大完整。
在第一半导体元件140以及第二半导体元件160之间的间隔较佳的是填充底填材料169。若干个焊球105设置在基板110的底面，用以电性连接另一基板或电路板。
图2A～2E为依照图1的多芯片封装模块的制造方法的示意图。本实施例的芯片封装模块的制造方法包括下列步骤：首先，提供基板110，并透过焊接导电凸块122的方式将芯片120设置在基板110上，如图2A所示。然后，将第一半导体元件140翻覆并设置在芯片120上，如图2B所示。芯片120以及第一半导体元件140分别透过导电凸块122及导线149电性连接至基板110。接着，将芯片120以及第一半导体元件140以封胶150密封，但形成开口155在第一半导体元件140上以暴露出部分的第一半导体元件140，如图2C所示。之后，将第二半导体元件160的若干个导电凸块168焊接至第一半导体元件10，使得第二半导体元件160设置在第一半导体元件140上并位于开155中，如图2D所示。最后，填充底填材料169在第一半导体元件140以及第二半导体元件160之间，并将若干个焊球105设置在基板110的底面，如图2E所示。具有多种功能的第二半导体元件可以被组合进多芯片封装模块100中以扩充及多元化其功能。此外，由于一旦客户提供订单时，具有特定功能的第二半导体元件马上可以组装在具有基本功能并且预先组装好的半成品封装件上，因此具备特定功能的多芯片封装模块将可以更快速地被制造出来。
第二实施例
图3为依照本发明第二实施例的多芯片封装模块的剖面图。本实施例与上述实施例的不同之处仅在于芯片120、基板110及其连接方式。这些差异将在下段做详细说明，而保留原有标号的则为相同的元件，因此将不再赘述。
请参考图3，本实施例的多芯片封装模块200包括基板110、芯片120、第一半导体元件140、封胶150以及第二半导体元件160。芯片120设置在基板110上，较佳的是芯片120的若干条导线222电性连接芯片120以及基板110。倒置的第一半导体元件140设置在芯片120上方。多芯片封装模块200还包括间隔材230设置在芯片120及第一半导体元件140之间。间隔材230较佳的是硅间隔物(silicon spacer)或聚酰亚胺膜(polyimide film)。间隔材230将芯片120与第一半导体元件140隔开，产生空间让导线222得以从芯片120延展至基板110。封胶150包覆芯片120、间隔材230以及第一半导体元件140，封胶150具有开口155而暴露出部分的第一半导体元件140。第二半导体元件160设置在第一半导体元件140上，并位于开155中。
半导体元件可以是次封装件，也就是包括至少一芯片设置在基板上。虽然图3中清楚揭示两芯片144及146是设置在第一半导体元件140内以及单一芯片164设置在第二半导体元件160内，然而多芯片封装模块200内的半导体元件结构并不限定于此。举例来说，第一半导体元件140可以只包括单一芯片，而第二半导体元件160可以包括两个芯片。
图4A～4E为依照图3的多芯片封装模块的制造方法的示意图。本实施例的芯片封装模块200的制造方法包括下列步骤：首先，提供基板110，并将芯片120设置在基板110上，如第4A图所示。然后，芯片120透过导线222接合的方式与基板110电性连接，如第4B图所示。接着，将间隔材230设置在芯片120上，如第4C图所示。之后，将第一半导体元件140翻覆并设置在芯片120之上，并利用打线接合的方式与基板110电性连接，如第4D图所示。芯片120以及第一半导体元件140分别透过导线222及149电性连接至基板110。接着，以第一实施例所述的方式，依序地以封胶150密封并设置第二半导体元件160以完成图4E中的多芯片封装模块200。
第三实施例
图5为依照本发明第三实施例的多芯片封装模块的剖面图。本实施例与上述实施例的不同之处仅在于芯片120、基板110以及芯片120与第一半导体元件140之间的连接方式。这些差异将在下段做详细说明，而保留原有标号的则为相同的元件，因此将不再赘述。
请参考图5，本实施例的多芯片封装模块300包括基板110、芯片120、第一半导体元件140、第一封胶330、第二封胶150以及第二半导体元件160。芯片120设置在基板110上，较佳的是芯片120的若干条导线222电性连接芯片120以及基板110。第一封胶330包覆芯片120及导线222。倒置的第一半导体元件140设置在芯片120上方，较佳的是堆叠在第一封胶330上。第二封胶150包覆芯片120、第一封胶330以及第一半导体元件140，第二封胶150具有开口155而暴露出部分的第一半导体元件140。第二半导体元件160设置在第一半导体元件140上，并位于开155中。
图6A～6D为依照图5的多芯片封装模块的制造方法的示意图。本实施例的芯片封装模块300的制造方法包括下列步骤：首先，提供基板110，将芯片120设置在基板110上，并透过导线222接合的方式与基板110电性连接，如图6A所示。然后，第一封胶330包覆芯片120以及导线222，如图6B所示。接着，将第一半导体元件140翻覆并设置在芯片120之上，较佳的是设置在第一封胶330上，并利用打线接合的方式与基板110电性连接，如图6C所示。芯片120以及第一半导体元件140分别透过导线222及149电性连接至基板110。最后，以第一实施例所述的方式，依序地以第二封胶150密封并设置第二半导体元件160以完成图6D中的多芯片封装模块300。
与现有技术相比，本发明上述实施例所揭露的多芯片封装模块及其制造方法具有多项优点。由于更多的芯片可以设置在封装模块中，使得封装件的体积可进一步的缩小，并具有较佳的性能。具有多种功能的第二半导体元件可以被组合进多芯片封装模块中以扩充及多元化其功能。此外，由于一旦客户提供订单时，具有特定功能的第二半导体元件马上可以组装在具有基本功能并且预先组装好的半成品封装件上，因此具备特定功能的多芯片封装模块将可以更快速地被制造出来。如此一来，传统上必须利用庞大又复杂的电路设计来实践的功能完整的模块，本发明只要利用弹性化的设计以及组合不同功能芯片就可以让封装模块具有完整的功能与较佳的性能，可以同时加速并简化制造流程。

Claims (16)

1. 一种多芯片封装模块，包括：
第一基板；
第一芯片，设置在所述第一基板上；
第一半导体元件，设置在所述第一芯片上方；
第一封胶，包覆所述第一芯片以及所述第一半导体元件；以及
第二半导体元件，其底面设置有若干个第一导电凸块，所述第二半导体元件设置在所述第一半导体元件上；
其特征在于：所述第一半导体元件是以倒置的方式设置在所述第一芯片上方，所述第一封胶具有开口而暴露出部分的所述第一半导体元件，所述第二半导体元件位于所述开口中并通过所述第一导电凸块与所述第一半导体元件电性连接。
2. 如权利要求1所述的多芯片封装模块，其特征在于所述多芯片封装模块进一步包括若干个第二导电凸块，用以电性连接所述第一芯片以及所述第一基板。
3. 如权利要求1所述的多芯片封装模块，其特征在于所述多芯片封装模块进一步包括若干条导线，用以电性连接所述第一芯片以及所述第一基板。
4. 如权利要求3所述的多芯片封装模块，其特征在于所述多芯片封装模块进一步包括第二封胶包覆所述第一芯片。
5. 如权利要求3所述的多芯片封装模块，其特征在于所述多芯片封装模块进一步包括间隔材，设置在所述第一芯片及所述第一半导体元件之间。
6. 如权利要求1所述的多芯片封装模块，其特征在于所述第一半导体元件是一次封装件，所述第一半导体元件至少包括：
第二基板；
第二芯片，设置在所述第二基板上；以及
第二封胶，包覆所述第二芯片以及所述第二基板；
其特征在于：所述第一半导体元件以该第二基板底面朝上的倒置方式设置在所述第一芯片上，所述第一封胶的所述开口暴露部分的所述第二基板。
7. 如权利要求1所述的多芯片封装模块，其特征在于所述第二半导体元件是一次封装件，所述第二半导体元件至少包括：
第二基板，所述第二基板的一底面设置所述第一导电凸块；
第二芯片，设置在所述第二基板的一顶面上；以及
第二封胶，包覆所述第二芯片以及所述第二基板。
8. 如权利要求1所述的多芯片封装模块，其特征在于所述多芯片封装模块进一步包括底填材料，填充于所述第一半导体元件以及所述第二半导体元件之间。
9. 一种多芯片封装模块的制造方法，包括下列步骤：
提供第一基板；
将第一芯片设置在所述第一基板上；
将第一半导体元件设置在所述第一芯片之上；
将所述第一芯片与所述第一半导体元件分别电性连接至所述第一基板；
将所述第一芯片以及所述第一半导体元件以封胶密封；以及
将第二半导体元件的若干个第一导电凸块焊接至所述第一半导体元件；
其特征在于：所述第一半导体元件是以翻覆的方式设置在所述第一芯片之上，所述封胶密封步骤进一步包括形成开口在第一半导体元件上以暴露出部分的所述第一半导体元件，所述第二半导体元件设置在所述第一半导体元件上并位于所述开口中。
10. 如权利要求9所述的方法，其特征在于所述方法进一步包括设置若干个第二导电凸块，用以电性连接所述第一芯片以及所述第一基板。
11. 如权利要求9所述的方法，其特征在于所述方法进一步包括设置若干条导线，用以电性连接所述第一芯片以及所述第一基板。
12. 如权利要求11所述的方法，其特征在于所述方法进一步包括以封胶密封所述第一芯片。
13. 如权利要求11所述的方法，其特征在于所述方法进一步包括：提供间隔材，并将其设置在所述第一芯片以及所述第一半导体元件之间。
14. 如权利要求11所述的方法，其特征在于所述第一半导体元件是一次封装件，所述第一半导体元件至少包括：
第二基板，设置在所述第一芯片上；
第二芯片，设置在所述第二基板上；以及
第二封胶，包覆所述第二芯片以及所述第二基板；
其特征在于：所述第一半导体元件以其底面朝上的方式设置在所述第一芯片上，所述第一封胶的所述开口暴露部分的所述第二基板。
15. 如权利要求9所述的方法，其特征在于所述第二半导体元件是一次封装件，所述第二半导体元件至少包括：
第二基板，所述第二基板的一底面设置所述第一导电凸块；
第二芯片，设置在所述第二基板的一顶面上；以及
第二封胶，包覆所述第二芯片以及所述第二基板。
16. 如权利要求9所述的方法，其特征在于所述方法进一步包括：填充底填材料于所述第一半导体元件以及所述第二半导体元件之间。
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CN102237342A (zh) * 2010-05-05 2011-11-09 中兴通讯股份有限公司 一种无线通讯模块产品
CN102244012A (zh) * 2010-05-13 2011-11-16 新科金朋有限公司 半导体器件及其制造方法
CN103972202A (zh) * 2013-01-31 2014-08-06 联想(北京)有限公司 电路装置及pcb板
CN111952197A (zh) * 2020-08-25 2020-11-17 济南南知信息科技有限公司 一种半导体装置及其封装方法

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CN102237342A (zh) * 2010-05-05 2011-11-09 中兴通讯股份有限公司 一种无线通讯模块产品
WO2011137676A1 (zh) * 2010-05-05 2011-11-10 中兴通讯股份有限公司 一种无线通讯模块产品
CN102237342B (zh) * 2010-05-05 2016-01-20 中兴通讯股份有限公司 一种无线通讯模块产品
CN102244012A (zh) * 2010-05-13 2011-11-16 新科金朋有限公司 半导体器件及其制造方法
US9257411B2 (en) 2010-05-13 2016-02-09 Stats Chippac, Ltd. Semiconductor device and method of embedding bumps formed on semiconductor die into penetrable adhesive layer to reduce die shifting during encapsulation
CN102244012B (zh) * 2010-05-13 2016-03-30 新科金朋有限公司 半导体器件及其制造方法
CN103972202A (zh) * 2013-01-31 2014-08-06 联想(北京)有限公司 电路装置及pcb板
CN111952197A (zh) * 2020-08-25 2020-11-17 济南南知信息科技有限公司 一种半导体装置及其封装方法
CN111952197B (zh) * 2020-08-25 2022-05-27 青岛融合装备科技有限公司 一种半导体装置及其封装方法

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