CN101308804A - 射频模块的封装结构及其制造方法 - Google Patents
射频模块的封装结构及其制造方法 Download PDFInfo
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Abstract
一种射频模块的封装结构及其制造方法。封装结构包括一多层电路基板、一第一晶粒、一第二晶粒、数个焊料凸块、一第一封胶体和一第二封胶体。基板包括一含金属的中间层,且具有相对的一第一面和一第二面。第一和第二晶粒分别设置于第一面及第二面上,并分别电性连接于基板。第一封胶体设置于第一面上,并覆盖住第一晶粒。焊料凸块设置于第二面上,且分别经由基板而电性连接于第一与第二晶粒。第二封胶体设置于第二面上。其中,第二封胶体覆盖住第二晶粒且包围焊料凸块的侧壁,且焊料凸块的表面裸露于该第二封胶体外。
Description
【技术领域】
本发明是有关于一种封装结构及其制造方法,且特别是有关于一种射频模块的封装结构及其制造方法。
【背景技术】
一般而言,射频模块包括有射频组件与基频组件。然而,为了避免射频组件与基频组件相互干扰,故在传统上,常以并排式(side by side)的多芯片模块封装(Multi-chip module package,MCM)来解决此问题。但是,这一种封装结构具有模块面积较大的缺点,使得产品失去市场竞争力。除了并排式结构之外,传统上也有使用堆栈(die stacked)的方式来封装射频组件与基频组件。请参照图1,其绘示一种传统堆栈封装射频模块的示意图。如图1所示,传统堆栈封装射频模块的封装结构100在上、下两片晶粒110和120之间加入一金属盖115,以形成电磁屏蔽的效果,来避免晶粒110和120相互干扰。但是,这一种封装结构具有模块厚度较厚的缺点。而且,提供金属盖所须的成本及其所须搭配的制程,也会造成生产成本大幅增加,使得产品失去市场竞争力。
【发明内容】
本发明是有关于一种射频模块的封装结构及其制造方法。基频组件与射频组件分设于多层电路基板的第一面与第二面,而此多层电路基板至少具有一含金属的中间层,以达到电磁屏蔽的功能。此外,焊料凸块的一表面裸露于第二封胶体外,使得封装结构可通过一输入/输出座板连接此些焊料凸块,进而可电性连接于一外部电路。于此,本发明提出的封装结构具有薄型化、易客制化模块的优点,进而提升其产品的市场价值。
本发明提出一种射频模块的封装结构的制造方法,其包括下列步骤。首先,提供一多层电路基板,此基板包括一含金属的中间层并具有相对的一第一面和一第二面。接着,设置一第一晶粒于第一面上,使得第一晶粒电性连接于基板。然后,形成一第一封胶体于第一面上,以覆盖住第一晶粒。再来,设置一第二晶粒于第二面上,使得第二晶粒电性连接于基板。接着,设置数个焊料凸块于第二面上,使得此些焊料凸块分别经由基板电性连接至第一晶粒与第二晶粒。然后,形成一封胶于第二面上,以覆盖住第二晶粒和此些焊料凸块。之后,部分切除封胶,以形成一第二封胶体覆盖住第二晶粒,且焊料凸块的表面裸露于该第二封胶体外。
本发明提出一种射频模块的封装结构,其包括一多层电路基板、一第一晶粒、一第二晶粒、数个焊料凸块、一第一封胶体和一第二封胶体。基板包括一含金属的中间层,且具有相对的一第一面和一第二面。第一晶粒和第二晶粒分别设置于第一面及第二面上,并分别电性连接于基板。第一封胶体设置于第一面上,并覆盖住第一晶粒。焊料凸块设置于第二面上,且分别经由基板而电性连接于第一晶粒与第二晶粒。第二封胶体设置于第二面上。其中,第二封胶体覆盖住第二晶粒且包围这些焊料凸块的侧壁,使得焊料凸块的一表面裸露在该第二封胶体外。
为让本发明的上述内容能更明显易懂,下文特举较佳实施例,并配合所附图式,作详细说明如下:
【附图说明】
图1绘示一种传统堆栈封装射频模块的示意图。
图2A~2J分别绘示依照本发明一较佳实施例的制造射频模块的封装结构的各步骤的示意图。
【具体实施方式】
本发明有关于一种射频模块的封装结构及其制造方法。基频组件与射频组件分别设置于多层电路基板的第一面与第二面,而此多层电路基板至少具有一含金属的中间层,以达到电磁屏蔽的功能。此外,在制造方法上,经过一部分切除的步骤,使得焊料凸块的一表面裸露于第二封胶体外。如此,将可以使用一输入/输出座板与焊料凸块电性连接,使得封装结构通过输入/输出座板而与一外部电路电性连接。于此,本发明提出的封装结构具有薄型化、易客制化模块的优点,进而提升其产品的市场价值。
以下提出一较佳实施例,并配合图标作本发明的说明。然而,实施例与图标所提出的射频模块的封装结构与制程步骤仅为举例说明之用,并非对本发明欲保护的范围做限缩。
<射频模块的封装结构的制造方法>
依照本发明一较佳实施例的射频模块的封装结构,兹详细说明如下,以作为熟悉此技术领域者据以实施的参考。另外,实施例中的图标亦省略不必要的组件,以利清楚显示本发明的技术特点。请参照图2A~2J,其分别绘示依照本发明一较佳实施例的制造射频模块的封装结构的各步骤的示意图。
首先,如图2A所示,提供一多层电路基板210,其至少包括一含金属的中间层215,并具有相对的一第一面210a和一第二面210b。
接着,如图2B所示,设置一第一晶粒220于第一面210a上,且使得第一晶粒220电性连接于基板210。在电性连接的方式上,可以如图所示通过数条金线225而电性连接第一晶粒220与基板210。或者,也可以使用覆晶接合的方式,使第一晶粒220与基板210具电性连接。于此,本发明不对第一晶粒220与基板210的连接方式多作限制。
然后,如图2C所示,形成一第一封胶体230于第一面210a上,以覆盖住第一晶粒220。
再来,如图2D所示,设置一第二晶粒240于第二面210b上,且电性连接第二晶粒240于基板210。同样地,在电性连接的方式上,可以如图所示通过数条金线245而电性连接第二晶粒240与基板210。或者,也可以使用覆晶接合的方式,使第二晶粒240与基板210具电性连接。于此,本发明亦不多作限制。
接着,如图2E所示,设置数个焊料凸块250于第二面210b上,此些焊料凸块250分别经由基板210而电性连接于第一晶粒220与第二晶粒240。其中,这些焊料凸块250较佳且非限定地可以由锡膏(solder paste)来构成。
然后,如图2F所示,形成一封胶260于第二面210b上,以覆盖住第二晶粒240和此些焊料凸块250。
之后,如图2G所示,部分切除封胶260,以形成一第二封胶体260’覆盖住第二晶粒240。此步骤例如为一半切制程(half cut),而且经此部分切除的步骤后,焊料凸块250’的一表面250’a裸露于第二封胶体260’外。并且,经部分切除封胶260之后所形成的第二封胶体260’具有至少一凸部260’p,凸部260’p的位置实质上对应至第二晶粒240。
接着,如图2H所示,提供一输入/输出座板(I/O frame board)270。且此座板270具有可容置凸部260’p的开口270h,且开口270h的一深度d大于等于凸部260’p的一厚度t。并在此步骤中,基板210将设置于输入/输出座板270上,而输入/输出座板270例如为一双层电路基板,其可以用来电性连接基板210上的焊料凸块250’于一外部电路。而且,基板210以第二面210b朝下的方式,通过焊料凸块250’而焊于输入/输出座板270上,以使得输入/输出座板270透过焊料凸块250’而电性连接至第一晶粒220和第二晶粒240。
之后,如第2I~2J图所示,切割(sawing)完成上述步骤的基板210与输入/输出座板270,以形成数个射频模块的封装结构200。于此切割步骤中所形成的封装结构200包括一个输入/输出基体(I/O block)270’。如此一来,封装结构200将可通过输入/输出基体270’与一外部电路电性连接。
其中,在本发明的实施例中,由于焊料凸块250’可以通过输入/输出基体270’而与一外部电路电性连接(请参照图2J)。故相较于习知技术使用焊球作电性连接的结构,本发明的焊料凸块250’之间的一间距D比较小,其较佳地可缩小至大约为0.3mm至0.4mm。并且本发明实施例中,较佳且非限定地,可以用多层电路基板210的一接地层作为前述含金属的中间层215。
<射频模块的封装结构>
请参照图2J。依照本发明实施例的制造方法所提出的一种射频模块的封装结构200,其包括一多层电路基板210、一第一晶粒220、一第二晶粒240、数个焊料凸块250’、一第一封胶体230和一第二封胶体260’。第一晶粒220与第二晶粒240,比如为一基频组件与一射频组件,分别设置于多层电路基板210的第一面210a与第二面210b,而此多层电路基板210至少具有一含金属的中间层215,以达电磁屏蔽的功能。第一封胶体230设置于第一面210a上,并覆盖住第一晶粒220。焊料凸块250’设置于第二面210b上,且分别经由基板210而电性连接于第一晶粒220与第二晶粒240。在本发明实施例中,一封胶260覆盖住第二晶粒240及焊料凸块250’,其经过部分切除后形成一第二封胶体260’。其中,所形成的第二封胶体260’覆盖住第二晶粒240,且包围焊料凸块250’的侧壁,且焊料凸块250’的表面250’a裸露于第二封胶体260’外。
在本发明的一实施例中,一输入/输出基体270’设于第二面210b,以与焊料凸块250’电性连接,使得封装结构200可以通过输入/输出基体270’与一外部电路(未绘示)电性连接,以具容易客制化模块的优势。并且,在本发明进一步的实施例中,经部分切除后所形成的第二封胶体260’具有一凸部260’p,且凸部260’p的位置实质上对应至第二晶粒240。而,输入/输出基体270’具有可容置第二封胶体260’的凸部260’p的一开口270h,且开口270h的深度d大于等于第二封胶体260’的凸部260’p的厚度t。于此实施例中,这种输入/输出基体270’的应用将可使封装结构200更为薄型化。如此一来,应用如本发明实施例提出的射频模块的封装结构200,其产品将更具市场优势。
本发明上述实施例所揭露的射频模块的封装结构,具有薄型化、易客制化模块的优点。其中,将基频组件与射频组件分设于多层电路基板的第一面与第二面。此多层电路基板具有一含金属的中间层,以达到电磁屏蔽的功能。此外,在制造方法上,可以使用半切的方式进行部分切除,使得焊料凸块的一表面裸露于第二封胶体外。如此,封装结构将可通过一输入/输出座板连接此些焊料凸块,而电性连接于一外部电路,以达薄型化、易客制化模块的优势。进而,能提升其产品的市场价值。
综上所述,虽然本发明已以较佳实施例揭露如上,然其并非用以限定本发明。本发明所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,当可作各种的更动与润饰。因此,本发明的保护范围当视后附的申请专利范围所界定者为准。
Claims (10)
1.一种射频模块的封装结构的制造方法,包括:
提供一多层电路基板,该基板包括一含金属的中间层,并具有相对的一第一面和一第二面;
设置一第一晶粒于该第一面上,使得该第一晶粒电性连接于该基板;
形成一第一封胶体于该第一面上,以覆盖住该第一晶粒;
设置一第二晶粒于该第二面上,使得该第二晶粒电性连接于该基板;
设置多个焊料凸块于该第二面上,使得该些焊料凸块分别经由该基板电性连接至该第一晶粒与该第二晶粒;
形成一封胶于该第二面上,以覆盖住该第二晶粒和该些焊料凸块;和
部分切除该封胶,以形成一第二封胶体覆盖住该第二晶粒,且该些焊料凸块的表面裸露于该第二封胶体外。
2.根据权利要求1所述的制造方法,其特征在于,经部分切除的该步骤所形成的该第二封胶体具有至少一凸部,该凸部的位置实质上对应至该第二晶粒,该制造方法更包括:
提供一输入/输出座板(I/O frame board),且该输入/输出座板具有可容置该第二封胶体的至少该凸部的至少一开口,且该开口的一深度大于等于该第二封胶体的该凸部的一厚度;和
设置该基板于该输入/输出座板(I/O frame board)上,其中该输入/输出座板用以电性连接该基板的该些焊料凸块于一外部电路。
3.根据权利要求2所述的制造方法,其特征在于,在设置该基板的该步骤中,使该基板的该第二面朝下且通过该些焊料凸块将该基板焊于该输入/输出座板上,以使得该输入/输出座板透过该些焊料凸块电性连接至该第一晶粒和该第二晶粒。
4.根据权利要求1所述的制造方法,其特征在于,在提供该基板的该步骤中,该含金属的中间层为一接地层。
5.根据权利要求1所述的制造方法,其特征在于,在设置该些焊料凸块的该步骤中,令该些焊料凸块之间的一间距约为0.3mm-0.4mm。
6.一种射频模块的封装结构,包括:
一多层电路基板,包括一含金属的中间层,该基板具有相对的一第一面和一第二面;
一第一晶粒,设置于该第一面上,并电性连接于该基板;
一第一封胶体,设置于该第一面上,并覆盖住该第一晶粒;
一第二晶粒,设置于该第二面上,并电性连接于该基板;
多个焊料凸块,设置于该第二面上,且分别经由该基板电性连接至该第一晶粒与该第二晶粒;和
一第二封胶体,设置于该第二面上,并覆盖住该第二晶粒,该第二封胶体包围该些焊料凸块的侧壁,使得该些焊料凸块的一表面裸露在该第二封胶体外。
7.根据权利要求6所述的封装结构,其特征在于,该第二封胶体具有至少一凸部,该凸部的位置实质上对应至该第二晶粒,该封装结构更包括:
一输入/输出基体(I/O block),具有可容置该第二封胶体的至少该凸部的至少一开口,该输入/输出基体位于该第二面,且位于该第二封胶体的该凸部之外围并与该些焊料凸块电性连接,且该输入/输出基体的一厚度大于等于该第二封胶体的该凸部的一厚度,其中该封装结构通过该输入/输出基体与一外部电路电性连接。
8.根据权利要求7所述的封装结构,其特征在于,该输入/输出基体为一双层电路基板。
9.根据权利要求6所述的封装结构,其特征在于,该含金属的中间层为一接地层。
10.根据权利要求6所述的封装结构,其特征在于,该些焊料凸块之间的一间距约为0.3mm-0.4mm。
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