TWI467729B - 射頻模組之封裝結構及其製造方法 - Google Patents

射頻模組之封裝結構及其製造方法 Download PDF

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TWI467729B
TWI467729B TW97125555A TW97125555A TWI467729B TW I467729 B TWI467729 B TW I467729B TW 97125555 A TW97125555 A TW 97125555A TW 97125555 A TW97125555 A TW 97125555A TW I467729 B TWI467729 B TW I467729B
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die
substrate
electrically connected
solder bumps
package structure
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TW201003887A (en
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Jian Cheng Chen
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Advanced Semiconductor Eng
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Description

射頻模組之封裝結構及其製造方法
本發明是有關於一種封裝結構及其製造方法，且特別是有關於一種射頻模組之封裝結構及其製造方法。
一般而言，射頻模組包括有射頻元件與基頻元件。然而，為了避免射頻元件與基頻元件相互干擾，故在傳統上，常以並排式(side by side)之多晶片模組封裝(Multi-chip module package，MCM)來解決此問題。但是，這一種封裝結構具有模組面積較大之缺點，使得產品失去市場競爭力。除了並排式結構之外，傳統上也有使用堆疊(die stacked)的方式來封裝射頻元件與基頻元件。請參照第1圖，其繪示一種傳統堆疊封裝射頻模組的示意圖。如第1圖所示，傳統堆疊封裝射頻模組的封裝結構100係在上、下兩片晶粒110和120之間加入一金屬蓋115，以形成電磁屏蔽之效果，來避免晶粒110和120相互干擾。但是，這一種封裝結構具有模組厚度較厚之缺點。而且，提供金屬蓋所須之成本及其所須搭配之製程，也會造成生產成本大幅增加，使得產品失去市場競爭力。
本發明係有關於一種射頻模組之封裝結構及其製造方法。基頻元件與射頻元件係分設於多層電路基板的第一 面與第二面，而此多層電路基板至少具有一含金屬的中間層，以達到電磁屏蔽之功能。此外，銲料凸塊之一表面係裸露於第二封膠體外，使得封裝結構可藉由一輸入/輸出座板連接此些銲料凸塊，進而可電性連接於一外部電路。於此，本發明提出之封裝結構具有薄型化、易客製化模組之優點，進而提升其產品的市場價值。
本發明提出一種射頻模組之封裝結構的製造方法，其包括下列步驟。首先，提供一多層電路基板，此基板包括一含金屬的中間層並具有相對的一第一面和一第二面。接著，設置一第一晶粒於第一面上，使得第一晶粒電性連接於基板。然後，形成一第一封膠體於第一面上，以覆蓋住第一晶粒。再來，設置一第二晶粒於第二面上，使得第二晶粒電性連接於基板。接著，設置數個銲料凸塊於第二面上，使得此些銲料凸塊分別經由基板電性連接至第一晶粒與第二晶粒。然後，形成一封膠於第二面上，以覆蓋住第二晶粒和此些銲料凸塊。之後，部分切除封膠，以形成一第二封膠體覆蓋住第二晶粒，且銲料凸塊的表面係裸露於該第二封膠體外。
本發明提出一種射頻模組之封裝結構，其包括一多層電路基板、一第一晶粒、一第二晶粒、數個銲料凸塊、一第一封膠體和一第二封膠體。基板包括一含金屬的中間層，且具有相對的一第一面和一第二面。第一晶粒和第二晶粒係分別設置於第一面及第二面上，並分別電性連接於基板。第一封膠體係設置於第一面上，並覆蓋住第一晶 粒。銲料凸塊係設置於第二面上，且分別經由基板而電性連接於第一晶粒與第二晶粒。第二封膠體係設置於第二面上。其中，第二封膠體係覆蓋住第二晶粒且包圍這些銲料凸塊之側壁，使得銲料凸塊之一表面係裸露在該第二封膠體外。
為讓本發明之上述內容能更明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下：
本發明係有關於一種射頻模組之封裝結構及其製造方法。基頻元件與射頻元件係分別設置於多層電路基板的第一面與第二面，而此多層電路基板至少具有一含金屬的中間層，以達到電磁屏蔽之功能。此外，在製造方法上，係經過一部分切除之步驟，使得銲料凸塊之一表面裸露於第二封膠體外。如此，將可以使用一輸入/輸出座板與銲料凸塊電性連接，使得封裝結構藉由輸入/輸出座板而與一外部電路電性連接。於此，本發明提出之封裝結構具有薄型化、易客製化模組之優點，進而提升其產品的市場價值。
以下係提出一較佳實施例，並配合圖示作本發明之說明。然而，實施例與圖示所提出的射頻模組之封裝結構與製程步驟僅為舉例說明之用，並非對本發明欲保護之範圍做限縮。
＜射頻模組之封裝結構之製造方法＞
依照本發明一較佳實施例之射頻模組之封裝結構，茲 詳細說明如下，以作為熟悉此技術領域者據以實施之參考。另外，實施例中之圖示亦省略不必要之元件，以利清楚顯示本發明之技術特點。請參照第2A~2J圖，其分別繪示依照本發明一較佳實施例之製造射頻模組之封裝結構之各步驟的示意圖。
首先，如第2A圖所示，提供一多層電路基板210，其至少包括一含金屬的中間層215，並具有相對的一第一面210a和一第二面210b。
接著，如第2B圖所示，設置一第一晶粒220於第一面210a上，且使得第一晶粒220電性連接於基板210。在電性連接的方式上，係可以如圖所示藉由數條金線225而電性連接第一晶粒220與基板210。或者，也可以使用覆晶接合的方式，使第一晶粒220與基板210具電性連接。於此，本發明係不對第一晶粒220與基板210的連接方式多作限制。
然後，如第2C圖所示，形成一第一封膠體230於第一面210a上，以覆蓋住第一晶粒220。
再來，如第2D圖所示，設置一第二晶粒240於第二面210b上，且電性連接第二晶粒240於基板210。同樣地，在電性連接的方式上，係可以如圖所示藉由數條金線245而電性連接第二晶粒240與基板210。或者，也可以使用覆晶接合的方式，使第二晶粒240與基板210具電性連接。於此，本發明亦不多作限制。
接著，如第2E圖所示，設置數個銲料凸塊250於第 二面210b上，此些銲料凸塊250係分別經由基板210而電性連接於第一晶粒220與第二晶粒240。其中，這些銲料凸塊250較佳且非限定地係可以由錫膏(solder paste)來構成。
然後，如第2F圖所示，形成一封膠260於第二面210b上，以覆蓋住第二晶粒240和此些銲料凸塊250。
之後，如第2G圖所示，部分切除封膠260，以形成一第二封膠體260'覆蓋住第二晶粒240。此步驟例如為一半切製程(half cut)，而且經此部分切除之步驟後，銲料凸塊250'之一表面250'a係裸露於第二封膠體260'外。並且，經部分切除封膠260之後所形成的第二封膠體260'具有至少一凸部260'p，凸部260'p之位置實質上係對應至第二晶粒240。
接著，如第2H圖所示，提供一輸入/輸出座板(I/O frame board)270。且此座板270具有可容置凸部260'p的開口270h，且開口270h之一深度d大於等於凸部260'p之一厚度t。並在此步驟中，基板210係將設置於輸入/輸出座板270上，而輸入/輸出座板270例如為一雙層電路基板，其可以用來電性連接基板210上之銲料凸塊250'於一外部電路。而且，基板210係以第二面210b朝下的方式，藉由銲料凸塊250'而銲於輸入/輸出座板270上，以使得輸入/輸出座板270透過銲料凸塊250'而電性連接至第一晶粒220和第二晶粒240。
之後，如第2I~2J圖所示，切割(sawing)完成上述步 驟之基板210與輸入/輸出座板270，以形成數個射頻模組之封裝結構200。於此切割步驟中所形成之封裝結構200包括一個輸入/輸出基體(I/O block)270'。如此一來，封裝結構200將可藉由輸入/輸出基體270'與一外部電路電性連接。
其中，在本發明之實施例中，由於銲料凸塊250'可以藉由輸入/輸出基體270'而與一外部電路電性連接(請參照第2J圖)。故相較於習知技術使用銲球作電性連接之結構，本發明的銲料凸塊250'之間的一間距D比較小，其較佳地可縮小至大約為0.3mm至0.4mm。並且本發明實施例中，較佳且非限定地，係可以用多層電路基板210之一接地層作為前述含金屬的中間層215。
＜射頻模組之封裝結構＞
請參照第2J圖。依照本發明實施例之製造方法所提出之一種射頻模組之封裝結構200，其包括一多層電路基板210、一第一晶粒220、一第二晶粒240、數個銲料凸塊250'、一第一封膠體230和一第二封膠體260'。第一晶粒220與第二晶粒240，比如為一基頻元件與一射頻元件，係分別設置於多層電路基板210的第一面210a與第二面210b，而此多層電路基板210至少具有一含金屬的中間層215，以達電磁屏蔽之功能。第一封膠體230係設置於第一面210a上，並覆蓋住第一晶粒220。銲料凸塊250'係設置於第二面210b上，且分別經由基板210而電性連接於 第一晶粒220與第二晶粒240。在本發明實施例中，一封膠260係覆蓋住第二晶粒240及銲料凸塊250'，其經過部分切除後係形成一第二封膠體260'。其中，所形成之第二封膠體260'係覆蓋住第二晶粒240，且包圍銲料凸塊250'之側壁，且銲料凸塊250'的表面250'a係裸露於第二封膠體260'外。
在本發明之一實施例中，一輸入/輸出基體270'係設於第二面210b，以與銲料凸塊250'電性連接，使得封裝結構200可以藉由輸入/輸出基體270'與一外部電路(未繪示)電性連接，以具容易客製化模組之優勢。並且，在本發明進一步的實施例中，經部分切除後所形成之第二封膠體260'具有一凸部260'p，且凸部260'p之位置實質上係對應至第二晶粒240。而，輸入/輸出基體270'具有可容置第二封膠體260'之凸部260'p之一開口270h，且開口270h的深度d係大於等於第二封膠體260'之凸部260'p的厚度t。於此實施例中，這種輸入/輸出基體270'的應用將可使封裝結構200更為薄型化。如此一來，應用如本發明實施例提出之射頻模組之封裝結構200，其產品將更具市場優勢。
本發明上述實施例所揭露之射頻模組之封裝結構，具有薄型化、易客製化模組之優點。其中，係將基頻元件與射頻元件分設於多層電路基板的第一面與第二面。此多層電路基板具有一含金屬的中間層，以達到電磁屏蔽之功能。此外，在製造方法上，係可以使用半切的方式進行部 分切除，使得銲料凸塊之一表面係裸露於第二封膠體外。如此，封裝結構將可藉由一輸入/輸出座板連接此些銲料凸塊，而電性連接於一外部電路，以達薄型化、易客製化模組之優勢。進而，能提升其產品的市場價值。
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100、200‧‧‧封裝結構
115‧‧‧金屬蓋
110、120‧‧‧晶粒
210a‧‧‧第一面
210b‧‧‧第二面
210‧‧‧多層電路基板
215‧‧‧中間層
220‧‧‧第一晶粒
225、245‧‧‧金線
230‧‧‧第一封膠體
240‧‧‧第二晶粒
250、250'‧‧‧銲料凸塊
250'a‧‧‧銲料凸塊之裸露表面
260‧‧‧封膠
260'‧‧‧第二封膠體
260'p‧‧‧凸部
270‧‧‧輸入/輸出座板
270'‧‧‧輸入/輸出基體
270h‧‧‧開口
D‧‧‧間距
d‧‧‧深度
t‧‧‧厚度
第1圖繪示一種傳統堆疊封裝射頻模組的示意圖。
第2A~2J圖分別繪示依照本發明一較佳實施例之製造射頻模組之封裝結構之各步驟的示意圖。
200‧‧‧封裝結構
210a‧‧‧第一面
210b‧‧‧第二面
210‧‧‧多層電路基板
215‧‧‧中間層
220‧‧‧第一晶粒
230‧‧‧第一封膠體
240‧‧‧第二晶粒
250'‧‧‧銲料凸塊
260'‧‧‧第二封膠體
260'p‧‧‧凸部
270'‧‧‧輸入/輸出基體
270h‧‧‧開口
D‧‧‧間距

Claims (16)

  1. 一種射頻模組之封裝結構的製造方法，包括：提供一多層電路基板，該基板包括一含金屬的中間層，並具有相對的一第一面和一第二面；設置一第一晶粒於該第一面上，使得該第一晶粒電性連接於該基板；形成一第一封膠體於該第一面上，以覆蓋住該第一晶粒；設置一第二晶粒於該第二面上，使得該第二晶粒電性連接於該基板；設置複數個銲料凸塊於該第二面上且位於該第二晶粒之兩側，使得該些銲料凸塊分別經由該基板電性連接至該第一晶粒與該第二晶粒；形成一封膠於該第二面上，以覆蓋住該第二晶粒和該些銲料凸塊；部分切除該封膠，以形成一第二封膠體覆蓋住該第二晶粒，且該第二封膠體具有至少一凸部，該凸部之位置實質上係對應至該第二晶粒，該些銲料凸塊之表面係裸露於該第二封膠體外；提供一輸入/輸出座板(I/O frame board)，該輸入/輸出座板具有可容置該第二封膠體之至少該凸部的至少一開口，且該開口之一深度大於等於該第二封膠體之該凸部之一厚度，該開口之一寬度大於該第二封膠體之該凸部之一寬度；和 設置該基板於該輸入/輸出座板(I/O frame board)上，其中該輸入/輸出座板係用以電性連接該基板之該些銲料凸塊於一外部電路。
  2. 如申請專利範圍第1項所述之製造方法，其中在設置該基板之該步驟中，係使該基板之該第二面朝下且藉由該些銲料凸塊將該基板銲於該輸入/輸出座板上，以使得該輸入/輸出座板透過該些銲料凸塊電性連接至該第一晶粒和該第二晶粒。
  3. 如申請專利範圍第1項所述之製造方法，其中在設置該第一晶粒之該步驟中，係以打線連接的方式電性連接該第一晶粒至該基板。
  4. 如申請專利範圍第1項所述之製造方法，其中在設置該第一晶粒之該步驟中，係以覆晶接合的方式電性連接該第一晶粒至該基板。
  5. 如申請專利範圍第1項所述之製造方法，其中在設置該第二晶粒之該步驟中，係以打線連接的方式電性連接該第二晶粒至該基板。
  6. 如申請專利範圍第1項所述之製造方法，其中在設置該第二晶粒之該步驟中，係以覆晶接合的方式電性連接該第二晶粒至該基板。
  7. 如申請專利範圍第1項所述之製造方法，其中在提供該基板之該步驟中，該含金屬的中間層係為一接地層。
  8. 如申請專利範圍第1項所述之製造方法，其中在 設置該些銲料凸塊之該步驟中，係令該些銲料凸塊之間的一間距約為0.3mm-0.4mm。
  9. 一種射頻模組之封裝結構，包括：一多層電路基板，包括一含金屬的中間層，該基板具有相對的一第一面和一第二面；一第一晶粒，設置於該第一面上，並電性連接於該基板；一第一封膠體，設置於該第一面上，並覆蓋住該第一晶粒；一第二晶粒，設置於該第二面上，並電性連接於該基板；複數個銲料凸塊，設置於該第二面上並位於該第二晶粒之兩側，且分別經由該基板電性連接至該第一晶粒與該第二晶粒；一第二封膠體，設置於該第二面上，並覆蓋住該第二晶粒，該第二封膠體具有至少一凸部，該凸部之位置實質上係對應至該第二晶粒，該第二封膠體係包圍該些銲料凸塊之側壁，使得該些銲料凸塊之一表面係裸露在該第二封膠體外；一輸入/輸出基體(I/O block)，具有可容置該第二封膠體之至少該凸部的至少一開口，該輸入/輸出基體係位於該第二面，且位於該第二封膠體之該凸部之外圍並與該些銲料凸塊電性連接，且該輸入/輸出基體之一厚度係大於等於該第二封膠體之該凸部之一厚度，該開口之一寬度大於該 第二封膠體之該凸部之一寬度，其中該封裝結構係藉由該輸入/輸出基體與一外部電路電性連接。
  10. 如申請專利範圍第9項所述之封裝結構，其中該輸入/輸出基體係為一雙層電路基板。
  11. 如申請專利範圍第9項所述之封裝結構，更包括：複數條第一金線，電性連接該第一晶粒和該基板。
  12. 如申請專利範圍第9項所述之封裝結構，其中該第一晶粒係為一覆晶晶粒。
  13. 如申請專利範圍第9項所述之封裝結構，更包括：複數條第二金線，電性連接該第二晶粒和該基板。
  14. 如申請專利範圍第9項所述之封裝結構，其中該第二晶粒係為一覆晶晶粒。
  15. 如申請專利範圍第9項所述之封裝結構，其中該含金屬的中間層係為一接地層。
  16. 如申請專利範圍第9項所述之封裝結構，其中該些銲料凸塊之間的一間距約為0.3mm-0.4mm。
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