WO2021073401A1 - 一种芯片封装方法及封装结构 - Google Patents

一种芯片封装方法及封装结构 Download PDF

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Publication number
WO2021073401A1
WO2021073401A1 PCT/CN2020/117655 CN2020117655W WO2021073401A1 WO 2021073401 A1 WO2021073401 A1 WO 2021073401A1 CN 2020117655 W CN2020117655 W CN 2020117655W WO 2021073401 A1 WO2021073401 A1 WO 2021073401A1
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metal bonding
substrate
layer
bonding layer
chip packaging
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PCT/CN2020/117655
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English (en)
French (fr)
Inventor
李林萍
盛荆浩
江舟
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杭州见闻录科技有限公司
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Priority to US17/598,270 priority Critical patent/US11552028B2/en
Priority to JP2021560508A priority patent/JP7075546B2/ja
Priority to EP20876619.6A priority patent/EP3929978B1/en
Publication of WO2021073401A1 publication Critical patent/WO2021073401A1/zh

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    • H—ELECTRICITY
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    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/0064—Packages or encapsulation for protecting against electromagnetic or electrostatic interferences
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L19/00—Details of, or accessories for, apparatus for measuring steady or quasi-steady pressure of a fluent medium insofar as such details or accessories are not special to particular types of pressure gauges
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Definitions

  • the present invention relates to the technical field of semiconductor device manufacturing, in particular to a chip packaging method and packaging structure with shielding function.
  • the existing wafer-level chip-scale package (WLCSP) is applied in the anti-electromagnetic wave design to reduce electromagnetic interference (EMI), mainly after the active and passive components are placed on the board, the active and passive components are wrapped with plastic materials in a compression molding method. Cover, plus a metal cover, cover the monomer and connect it to the ground to achieve EMI protection.
  • the present invention provides a chip packaging method and packaging structure to solve the problem that the anti-electromagnetic interference effect of wafer-level chip size packaging in the prior art cannot meet the needs of people.
  • a chip packaging method includes:
  • a wafer is provided, the wafer includes a first surface and a second surface that are opposed to each other, and at least two functional circuit areas and a plurality of bonding pads located around the functional circuit area are formed on the first surface of the wafer ;
  • the passivation layer including a middle area and an edge area surrounding the middle area;
  • a substrate is provided, the substrate includes a third surface and a fourth surface that are opposed to each other, a second metal bonding layer to be bonded to the first metal bonding layer is formed in the third surface of the substrate, and After the wafer and the substrate are bonded, a first shielding layer is provided corresponding to the functional circuit area, and the first shielding layer is connected to the second metal bonding layer;
  • the first metal bonding layer is bonded to the second metal bonding layer, and the second metal bonding layer exposes at least a part of the middle region of the passivation layer, so that the third surface and the The surface of the passivation layer away from the wafer is bonded together;
  • a second shielding layer is formed on the second surface of the wafer and the cutting groove, and the second shielding layer is electrically connected to the first metal bonding layer.
  • Etching the intermediate area of the substrate and the passivation layer to form an opening the opening at least penetrates the substrate and the passivation layer to expose the solder pad;
  • the opening is filled to form a conductive structure.
  • the method further includes:
  • Etching the intermediate area of the substrate and the passivation layer to form an opening the opening at least penetrates the substrate and the passivation layer to expose the solder pad;
  • the opening is filled to form a conductive structure.
  • the etching the intermediate area of the substrate and the passivation layer to form an opening specifically includes:
  • the surface of the substrate away from the third surface is etched through an etching process to sequentially etch the substrate, the second metal bonding layer, and the passivation layer, exposing the bonding pad to form Open holes.
  • the method further includes:
  • a ball is planted on the surface of the conductive structure.
  • the forming a first metal bonding layer on the passivation layer specifically includes:
  • a damascene process is used to fill the first groove to form the first metal bonding layer, the surface of the first metal bonding layer facing away from the passivation layer and the surface of the passivation layer facing away from the pad The surface is flush.
  • the method further includes:
  • the surfaces of the first metal bonding layer and the passivation layer are planarized so that the surfaces of the first metal bonding layer and the passivation layer are flush.
  • the providing of the substrate includes a third surface and a fourth surface that are opposed to each other, and a second metal bonding layer is formed on the third surface of the substrate, which specifically includes:
  • the substrate base including a third surface and a fourth surface that are opposed to each other;
  • a first shielding layer is formed, the first shielding layer is connected to the second metal bonding layer, and after the wafer and the substrate are bonded, the first shielding layer is connected to the functional circuit area Corresponding.
  • the method further includes:
  • the surfaces of the second metal bonding layer and the substrate base are planarized so that the surfaces of the second metal bonding layer and the substrate base are flush.
  • the method further includes:
  • a third groove is opened on the third surface, and the position of the third groove is opposite to the position of the functional circuit area on the wafer after bonding.
  • the material of the first shielding layer and the second shielding layer are the same, and both are metallic materials.
  • the first metal bonding layer and the second metal bonding layer are made of the same material, and both are metal materials.
  • the present invention also provides a chip packaging structure, which is characterized in that it is fabricated and formed by using any one of the above chip packaging methods, and the chip packaging structure includes:
  • a functional circuit area and solder pads located around the functional circuit area are provided on the surface of the wafer facing the substrate;
  • a passivation layer located on the solder pad and attached to the surface of the substrate
  • a first metal bonding layer located in the surface of the passivation layer away from the wafer;
  • a second metal bonding layer located in the surface of the substrate facing the wafer, wherein a bonding interface is formed between the first metal bonding layer and the second metal bonding layer;
  • a first shielding layer covering the surface of the substrate facing the wafer and electrically connected to the second metal bonding layer
  • a second shielding layer covering the surface of the wafer other than the surface facing the substrate and the sidewall of the passivation layer.
  • it further comprises a planting ball located on the conductive structure.
  • the material of the first shielding layer and the second shielding layer are the same, and both are metallic materials.
  • the material of the first shielding layer is copper, silver, nickel or nickel-iron alloy.
  • the first metal bonding layer and the second metal bonding layer are made of the same material, and both are metal materials.
  • the material of the first metal bonding layer includes copper, gold or copper-tin alloy.
  • the thickness of the first metal bonding layer ranges from 100 nm to 1000 nm, including the endpoint value.
  • the thickness of the passivation layer ranges from 1 ⁇ m to 5 ⁇ m, inclusive.
  • the material of the passivation layer includes Si, amorphous AlN, Si 3 N 4 or silicon oxide.
  • the material of the first metal bonding layer and the second metal bonding layer are the same.
  • the thickness of the second metal bonding layer ranges from 1 ⁇ m to 5 ⁇ m, inclusive.
  • the thickness of the substrate ranges from 30 ⁇ m to 100 ⁇ m, including the endpoint value.
  • the substrate faces the surface of the wafer, and an area corresponding to the functional circuit area is further provided with a groove.
  • the chip packaging structure is a chip including a filter, and the functional circuit area corresponding to the filter is a resonant circuit.
  • the chip packaging method provided by the present invention provides a passivation layer on the bonding pad of the wafer, and then forms a first metal bonding layer on the passivation layer, and a second metal bond on the substrate. Layer, through the bonding of the first metal bonding layer and the second metal bonding layer, the substrate and the wafer are bonded and packaged together.
  • the substrate is provided with a first shielding layer, the first shielding layer and the second metal
  • the bonding layer is arranged in contact; after the wafer and the substrate are bonded, the wafer is half-cut to expose the first metal bonding layer, and then a second shielding layer is formed, and the second shielding layer is bonded to the first metal
  • the layers are electrically connected to obtain an electromagnetic shielding structure composed of the first shielding layer, the second metal bonding layer, the second shielding layer and the first metal bonding layer.
  • the shielding structure is approximately closed, thereby improving the electromagnetic shielding effect .
  • FIG. 1 is a flowchart of a chip packaging method provided by an embodiment of the present invention
  • FIGS. 2 to 17 are corresponding process diagrams of a chip packaging method provided by an embodiment of the present invention.
  • FIG. 18 is a schematic diagram of a chip package structure provided by an embodiment of the present invention.
  • 19 is a schematic diagram of another chip package structure provided by an embodiment of the present invention.
  • FIG. 20 is a schematic diagram of another chip package structure provided by an embodiment of the present invention.
  • the present invention provides a chip packaging method, including:
  • a wafer is provided, the wafer includes a first surface and a second surface that are opposed to each other, and at least two functional circuit areas and a plurality of bonding pads located around the functional circuit area are formed on the first surface of the wafer ;
  • the passivation layer including a middle area and an edge area surrounding the middle area;
  • a substrate is provided, the substrate includes a third surface and a fourth surface that are opposed to each other, a second metal bonding layer to be bonded to the first metal bonding layer is formed in the third surface of the substrate, and After the wafer and the substrate are bonded, a first shielding layer is provided corresponding to the functional circuit area, and the first shielding layer is connected to the second metal bonding layer;
  • the first metal bonding layer is bonded to the second metal bonding layer, and the second metal bonding layer exposes at least a part of the middle region of the passivation layer, so that the third surface and the The surface of the passivation layer away from the wafer is bonded together;
  • a second shielding layer is formed on the second surface of the wafer and the cutting groove, and the second shielding layer is electrically connected to the first metal bonding layer.
  • a passivation layer is provided on the bonding pad of the wafer, and then a first metal bonding layer is formed on the passivation layer, and a second metal bonding layer is formed on the substrate. Bonding of the bonding layer and the second metal bonding layer, bonding and packaging the substrate and the wafer together, the substrate is provided with a first shielding layer, and the first shielding layer is arranged in contact with the second metal bonding layer; After the wafer and the substrate are bonded, the wafer is half-cut to expose the first metal bonding layer, and then a second shielding layer is formed.
  • the second shielding layer is electrically connected to the first metal bonding layer to obtain
  • the electromagnetic shielding structure is composed of the first shielding layer, the second metal bonding layer, the second shielding layer and the first metal bonding layer, and the shielding structure is approximately closed, thereby improving the electromagnetic shielding effect.
  • the passivation layer makes the solder pad only serve as a conductive structure, not as a metal bonding layer, so that it can be above the solder pad and avoid the metal bond.
  • a through silicon hole is provided to electrically connect the functional circuit area between the wafer and the substrate to the outside of the chip package structure, that is, the through silicon hole is set above the bonding pad, and there is no need to set copper pillars, occupying the functional circuit area Therefore, the use area of the functional circuit area is increased. When the chip size is reduced, the functional circuit area is prevented from shrinking, thereby ensuring the circuit performance of the chip.
  • FIG. 1 is a flowchart of a chip packaging method according to an embodiment of the present invention.
  • the chip packaging method includes:
  • S101 Provide a wafer.
  • the wafer includes a first surface and a second surface that are opposed to each other.
  • On the first surface of the wafer at least two functional circuit areas and a plurality of functional circuit areas are formed around the functional circuit area.
  • the filter chip is taken as an example for description.
  • the filter chip is designed by using the principle of surface acoustic wave or bulk acoustic wave. It must be packaged in the resonant circuit unit. An air cavity without any medium contact is formed on one side to ensure that the sound wave will not be conducted or dissipated, and that the sound wave is resonant according to the designed mode to obtain the required frequency output. Therefore, all filter chips are packaged A cavity is needed on one side of the resonant unit.
  • Figure 2 is a schematic cross-sectional structure of the wafer; the wafer includes a first surface and a second surface that are opposed to each other.
  • the first surface is the upper surface in Figure 2 and the second surface is the The bottom surface is not shown with reference numerals in this embodiment.
  • the resonant circuit 11 and the bonding pads 12 of the filter are formed on the first surface of the wafer 1.
  • the filter units 10 arranged in an array are usually arranged on the wafer to achieve batch produce.
  • Each of the filter units 10 includes a resonance circuit 11 and a bonding pad 12.
  • the functional circuit area corresponding to the filter chip is a resonant circuit.
  • the circuits in the functional circuit area may have different structures according to different designs of chip functions.
  • S102 forming a passivation layer on the solder pad, the passivation layer including a middle area and an edge area surrounding the middle area;
  • a passivation layer 2 is formed on the bonding pad 12. It should be noted that the specific position of the passivation layer is not limited in this embodiment.
  • the process of forming the passivation layer in this embodiment may be a deposition process, and the passivation layer is deposited on the surface of the bonding pad.
  • the material of the passivation layer can be one of Si, amorphous AlN, Si 3 N 4 or silicon oxide.
  • the passivation layer formed on the bonding pad between two adjacent functional circuit regions can be connected into one area to facilitate the production of the passivation layer.
  • the specific thickness of the passivation layer is not limited in this embodiment. Different thicknesses can be set according to the different chip structures formed. It should be noted that, taking the filter chip as an example, since the resonant circuit of the filter chip needs to be set in In the cavity, therefore, the thickness of the formed cavity can be controlled by the thickness of the passivation layer in this embodiment. Optionally in this embodiment, the thickness of the passivation layer ranges from 1 ⁇ m to 5 ⁇ m, including the endpoint value.
  • the first metal bonding layer covers the edge area of the passivation layer in order to subsequently provide the second metal bonding layer correspondingly, so that the second metal bonding layer can be connected to the first shielding layer inside the substrate , So that a similar closed electromagnetic shielding structure can be obtained.
  • the specific method of forming the first metal bonding layer is not limited in this embodiment.
  • the surface of the substrate is connected to the passivation layer. The surface fits.
  • the formation of the first metal bonding layer on the passivation layer 2 in this embodiment can be specifically formed by the following method:
  • a first groove 20 is formed on the passivation layer 2; in this embodiment, the position of the first groove is not limited, and it can be designed according to a preset bonding position.
  • a damascene process is used to fill the first groove 20 to form the first metal bonding layer 3, and the first metal bonding layer 3 is away from the surface of the passivation layer 2 and the surface of the passivation layer.
  • the surface of the passivation layer 2 away from the bonding pad 12 is flush. That is, as shown in FIG. 5, the upper surfaces of the first metal bonding layer 3 and the passivation layer 2 are flush.
  • the damascene process is to inlay the material of the first metal bonding layer in the first groove, so that the surface of the first metal bonding layer and the passivation layer are flush.
  • this embodiment may further include: planarizing the surfaces of the first metal bonding layer and the passivation layer, so that The surfaces of the first metal bonding layer and the passivation layer are flush.
  • the formation of the first metal bonding layer may be formed by an evaporation process.
  • the bottom of the first groove needs to be above the bonding pad, and the passivation layer remains between the first metal bonding layer and the bonding pad.
  • the thickness of the first metal bonding layer ranges from 100 nm to 1000 nm, including the endpoint value.
  • S104 Provide a substrate, the substrate includes a third surface and a fourth surface that are opposed to each other, and a second metal bonding layer to be bonded to the first metal bonding layer is formed on the third surface of the substrate, And after the wafer and the substrate are bonded, a first shielding layer is provided corresponding to the functional circuit area, and the first shielding layer is connected to the second metal bonding layer;
  • the substrate base including a third surface and a fourth surface that are opposed to each other;
  • a second groove 40 is opened on the third surface of the substrate 4;
  • a damascene process is used to fill the second groove 40 to form the second metal bonding layer 5.
  • the second metal bonding layer 5 is away from the surface of the substrate 4 and the first The three surfaces are flush. That is, as shown in FIG. 7, the upper surface of the second metal bonding layer 5 is flush with the upper surface of the substrate 4.
  • the first shielding layer 5' is provided at the position corresponding to the functional circuit area.
  • the material of the first shielding layer is not limited in this embodiment, as long as the conductive material that can achieve electromagnetic shielding is used.
  • the material of the first shielding layer may be metal, including copper, silver, nickel, or nickel-iron alloy.
  • the position of the second metal bonding layer 5 is correspondingly set according to the position of the first metal bonding layer 3.
  • the third surface of the substrate and the surface of the passivation layer may also include: planarizing the second metal bonding layer and The surface of the substrate base is such that the second metal bonding layer is flush with the surface of the substrate base.
  • the cavity of the filter chip in addition to controlling the thickness of the passivation layer to control the thickness of the cavity, it may also include: opening a third groove on the third surface, and the third The position of the groove is opposite to the position of the functional circuit area on the wafer after bonding.
  • the third groove By providing the third groove, a filter chip with a larger cavity thickness is formed.
  • the shape of the third groove is not limited in this embodiment.
  • the third groove is in a cross-sectional view perpendicular to the third surface. It may be a square groove or an arc-shaped groove, which is not limited in this embodiment.
  • S105 Bond the first metal bonding layer to the second metal bonding layer, and the second metal bonding layer exposes at least a part of the middle region of the passivation layer, so that the third surface is The surface of the passivation layer away from the wafer is bonded together;
  • the first metal bonding layer and the second metal bonding layer are bonded together by a bonding process, and at the same time, the surface of the passivation layer is closely attached to the surface of the substrate.
  • the second metal bonding layer exposes a part of the middle area of the passivation layer to facilitate subsequent production of TSV openings.
  • the materials of the first metal bonding layer and the second metal bonding layer are not limited.
  • the materials of the first metal bonding layer and the second metal bonding layer are the same, and both are metal materials.
  • the metal material is used for bonding, and the metal bonding is formed. Compared with other bonding structures formed by bonding glue, the metal bonding is more stable, so that the chip packaging structure has higher reliability.
  • the material of the first metal bonding layer includes copper, gold or copper-tin alloy.
  • the projected areas of the first metal bonding layer and the second metal bonding layer on the wafer are not limited, nor are they limited to the specific positions of the first metal bonding layer and the second metal bonding layer. As long as the wafer and substrate can be bonded together after the two are bonded, and the second metal bonding layer can be in electrical contact with the first shield, it can ensure the reliability of the chip and facilitate the subsequent formation of a nearly closed shield. structure.
  • S106 Perform a half-cut to the substrate from the second surface of the wafer, and the cutting groove exposes at least the first metal bonding layer;
  • Fig. 9 the second surface of the wafer 1 is half-cut to the substrate to obtain a cutting groove 6'.
  • a second shielding layer is formed on the second surface of the wafer and the cutting groove, and the second shielding layer is electrically connected to the first metal bonding layer.
  • the first metal bonding layer is exposed by half-cutting, and then a second shielding layer 7'is formed on the second surface of the wafer and the cutting groove, so that the second shielding layer and the first metal bonding layer Electrically connected to form part of the electromagnetic shielding structure.
  • the chip packaging method provided by the present invention forms a semi-finished chip structure.
  • TSV through holes are formed in the follow-up to transmit the internal signals of the circuit to the outside.
  • the step of forming TSV through holes may be before the half-cutting step or after the half-cutting step.
  • TSV hole making is performed before the half-cutting step, which includes:
  • the substrate is thinned to prepare for the subsequent production of openings. Therefore, the thickness of the rear substrate 4'is reduced to meet the requirements of openings.
  • the specific thickness of the thinned substrate is not limited.
  • the thickness H of the thinned substrate ranges from 30 ⁇ m to 100 ⁇ m, including the endpoint value.
  • an intermediate area between the substrate and the passivation layer is etched to form an opening, and the opening penetrates at least the substrate and the passivation layer to expose the solder pad;
  • FIG. 13 Please refer to FIG. 13 to fill the opening to form a conductive structure 7.
  • the TSV through hole is made first, and then the half-cut process is performed, which is more difficult to control to avoid wafer cracking.
  • the embodiment of the present invention may also perform the half-cut first, and then perform the TSV hole.
  • TSV hole making is performed after the half-cutting step, which includes:
  • the substrate is thinned to prepare for the subsequent production of openings. Therefore, the thickness of the rear substrate 4'is reduced to meet the requirements of openings.
  • the specific thickness of the thinned substrate is not limited.
  • the thickness H of the thinned substrate ranges from 30 ⁇ m to 100 ⁇ m, including endpoints.
  • the intermediate area between the substrate and the passivation layer is etched to form an opening, and the opening penetrates at least the substrate and the passivation layer to expose the solder pad;
  • the opening is filled to form a conductive structure 7.
  • etching is performed from the thinned surface of the substrate, and the substrate base and the passivation layer are sequentially etched to obtain openings 6, and the openings 6 expose the solder pads 12.
  • the position of the opening in this embodiment may only penetrate the substrate and the passivation layer without contacting the first metal bonding layer and the second metal bonding layer. It can also be that the sidewall of the opening is in contact with the first metal bonding layer alone, or in contact with the second metal bonding layer alone, or in contact with both the first metal bonding layer and the second metal bonding layer, this embodiment China does not limit this.
  • the surface of the substrate away from the third surface is etched sequentially through an etching process to expose the substrate, the second metal bonding layer, and the passivation layer.
  • the solder pads form openings.
  • the internal structure of the circuit needs to be led out to be grounded, in this embodiment, as shown in FIG. 17, after the thinning of the substrate 4'away from the third surface
  • the surface is etched through an etching process to sequentially etch the substrate 4', the second metal bonding layer 5, the first metal bonding layer 3 and the passivation layer 2, exposing the bonding pad 12, Form openings. That is, after the opening is subsequently filled, the metal in the opening is electrically connected to the metal of the first metal bonding layer and the second metal bonding layer, thereby achieving grounding.
  • the metal bonding layer can be used as a grounding ring at the same time, thereby further saving the space of the chip.
  • the bonding pads on the wafer are electrically connected to the outside.
  • it in order to form a chip structure that can be directly electrically connected to other components, after filling the openings to form a conductive structure, it further includes planting balls above the filled openings, and the planting balls are electrically connected to the conductive structure.
  • FIG. 18 is a schematic diagram of the chip packaging structure provided in the embodiment of the present invention.
  • the second metal bonding layer 5 is penetrated by the opening, and the conductive structure 7 is electrically connected to the second metal bonding layer 5, thereby leading out the structure of the internal circuit for grounding.
  • the opening not only penetrates the second metal bonding layer 5 but also penetrates the first metal bonding layer 3, and is used to lead internal circuits for grounding.
  • a passivation layer is provided on the bonding pad of the wafer, and then a first metal bonding layer is formed on the passivation layer, and a second metal bonding layer is formed on the substrate.
  • the bonding of the metal bonding layer and the second metal bonding layer bonds and encapsulates the substrate and the wafer together.
  • a first shielding layer is provided on the substrate, and the first shielding layer is connected to the second metal bonding layer.
  • the wafer is half-cut to expose the first metal bonding layer, and then a second shielding layer is formed, and the second shielding layer is electrically connected to the first metal bonding layer,
  • an electromagnetic shielding structure composed of the first shielding layer, the second metal bonding layer, the second shielding layer and the first metal bonding layer is obtained, and the shielding structure is approximately closed, thereby improving the electromagnetic shielding effect.
  • the present invention also provides a chip packaging structure, which is fabricated and formed by the above-mentioned chip packaging method. Please refer to FIG. 18.
  • the chip packaging structure includes:
  • the wafer 1 and the substrate 4' arranged oppositely;
  • the wafer 1 is provided with a functional circuit area and a bonding pad 12 located around the functional circuit area on the surface of the substrate 4'facing the substrate 4';
  • the passivation layer 2 located on the solder pad 12 and attached to the surface of the substrate 4';
  • the first metal bonding layer 3 located in the surface of the passivation layer 2 away from the wafer 1;
  • the second metal bonding layer 5 located in the surface of the substrate 4'facing the wafer 1, wherein a bonding is formed between the first metal bonding layer 3 and the second metal bonding layer 5 interface;
  • a first shielding layer 5' covering the substrate 4'facing the surface of the wafer 1 and electrically connected to the second metal bonding layer 5;
  • the second shielding layer 7' covering the surface of the wafer 1 excluding the surface facing the substrate 4'and the sidewall of the passivation layer 2.
  • a bump 8 may also be included above the conductive structure 7.
  • the first shielding layer and the second shielding layer are made of the same material, and both are made of metal.
  • the material of the first shielding layer is copper, silver, nickel or nickel-iron alloy.
  • the thickness of the first metal bonding layer ranges from 100 nm to 1000 nm, including the endpoint value.
  • the thickness of the passivation layer ranges from 1 ⁇ m to 5 ⁇ m, including endpoint values.
  • the material of the passivation layer includes Si, amorphous AlN, Si 3 N 4 or silicon oxide.
  • the first metal bonding layer and the second metal bonding layer are made of the same material.
  • the material of the first metal bonding layer includes copper, gold or copper-tin alloy.
  • the thickness of the second metal bonding layer ranges from 1 ⁇ m to 5 ⁇ m, including endpoints.
  • the thickness of the substrate ranges from 30 ⁇ m to 100 ⁇ m, including the endpoint value.
  • the substrate faces the surface of the wafer, and the area corresponding to the functional circuit area is also provided with a groove 9.
  • the substrate is provided with a resonance circuit
  • the grooves may be arc-shaped grooves or square-shaped grooves, which are not limited in this embodiment, as shown in FIG. 19 are arc-shaped grooves.
  • the bonding structure includes a bonding pad on the wafer, a passivation layer on the bonding pad, a first metal bonding layer and a second metal bonding layer on the passivation layer.
  • the two metal bonding layers, and the TSV openings that penetrate the substrate, the second metal bonding layer, the first metal bonding layer, and the passivation layer sequentially to expose the bonding pad.
  • chip packaging structures of various structures can also be provided, which will not be described in detail in the embodiments of the present invention.
  • the packaging method provided in the embodiment of the present invention can also package multiple filter wafer structures at the same time, thereby obtaining multiple filter packaging structures, including two-in-one, three-in-one, four-in-one, etc.
  • the filter products, as well as multiplexers such as duplexers, quadruplexers, hexaplexers, and octaplexers, directly realize the smallest product structure and the best performance.
  • the chip packaging structure provided by the embodiments of the present invention adopts the chip packaging method described in the above embodiments, can directly utilize existing processes and equipment, and has mature materials, and is suitable for all filter types (SAW and BAW) All types of packaging are also suitable for packaging of single and multiple filters, and can also be suitable for packaging of RF front-end modules (SIP modules) including filters required by various cellular terminals.
  • the cellular terminal includes 2G/3G/4G/5G mobile phones, WiFi, Pad, smart watch, IOT, automobile and other terminal devices in terminal scenarios.
  • the chip packaging structure provided in the embodiments of the present invention is packaged using the chip packaging method described in the above embodiments, by providing a passivation layer on the bonding pad of the wafer, and then forming a first metal bonding layer on the passivation layer , A second metal bonding layer is formed on the substrate, the substrate and the wafer are bonded and packaged together through the bonding of the first metal bonding layer and the second metal bonding layer, and the first shielding layer is provided on the substrate, The first shielding layer is arranged in contact with the second metal bonding layer; after the wafer and the substrate are bonded, the wafer is half-cut to expose the first metal bonding layer, and then the second shielding layer is formed, The second shielding layer is electrically connected to the first metal bonding layer, thereby obtaining an electromagnetic shielding structure composed of the first shielding layer, the second metal bonding layer, the second shielding layer and the first metal bonding layer. The structure is approximately closed, thereby improving the electromagnetic shielding effect.
  • the passivation layer makes the solder pad only serve as a conductive structure, not as a metal bonding layer, so that it can be above the solder pad and avoid the metal bond.
  • a through silicon hole is provided to electrically connect the functional circuit area between the wafer and the substrate to the outside of the chip package structure, that is, the through silicon hole is set above the bonding pad, and there is no need to set copper pillars, occupying the functional circuit area Therefore, the use area of the functional circuit area is increased. When the chip size is reduced, the functional circuit area is prevented from shrinking, thereby ensuring the circuit performance of the chip.

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Abstract

本申请提供一种芯片封装方法及芯片封装结构，通过在晶圆的焊垫上设置钝化层，然后在钝化层上形成第一金属键合层，在基板上形成第二金属键合层，通过第一金属键合层和第二金属键合层的键合，将基板和晶圆键合封装在一起，基板上设置有第一屏蔽层，所述第一屏蔽层与第二金属键合层相接设置；在晶圆和基板键合后，对晶圆进行半切割，切割到暴露第一金属键合层，再形成第二屏蔽层，第二屏蔽层与第一金属键合层电性连接，从而得到由第一屏蔽层、第二金属键合层、第二屏蔽层和第一金属键合层共同组成的电磁屏蔽结构，该屏蔽结构近似封闭，进而提高了电磁屏蔽效果。

Description

一种芯片封装方法及封装结构
本申请要求于2019年10月15日提交中国专利局、申请号为201910978107.6、发明名称为“一种芯片封装方法及封装结构”的国内申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体器件制作技术领域，尤其涉及一种具有屏蔽功能的芯片封装方法及封装结构。
背景技术
现有晶圆级芯片尺寸封装(WLCSP)应用在降低电磁干扰(EMI)的防电磁波设计上，主要是将主被动元件在上板后，以压模方式将主被动元件用塑料材料将其包覆，再加上金属盖的方式，将其单体包覆并与地相接，以实现EMI防护。这些技术会使成品厚度与体积增加，而且仅外加金属盖的防电磁干扰效果并不理想，还是存在较大干扰现象。
发明内容
有鉴于此，本发明提供一种芯片封装方法及封装结构，以解决现有技术中晶圆级芯片尺寸封装防电磁干扰效果无法满足人们需求的问题。
为实现上述目的，本发明提供如下技术方案：
一种芯片封装方法，包括：
提供晶圆，所述晶圆包括相对设置的第一表面和第二表面，所述晶圆的第一表面上至少形成有两个功能电路区和位于所述功能电路区周围的多个焊垫；
在所述焊垫上形成钝化层，所述钝化层包括中间区域和围绕中间区域的边缘区域；
在所述钝化层上形成第一金属键合层，所述第一金属键合层覆盖所述钝化层的边缘区域；
提供基板，所述基板包括相对设置的第三表面和第四表面，所述基板的第三表面内形成有与所述第一金属键合层待键合的第二金属键合层，以及在所述晶圆和所述基板键合后，与所述功能电路区对应设置的第一屏蔽层，且，所述第一屏蔽层与所述第二金属键合层相接；
将所述第一金属键合层与所述第二金属键合层键合，所述第二金属键合层至少暴露所述钝化层的部分中间区域，使得所述第三表面与所述钝化层背离所述晶圆的表面贴合在一起；
从所述晶圆的第二表面向所述基板进行半切割，切割凹槽至少暴露所述第一金属键合层；
在所述晶圆的第二表面以及所述切割凹槽内形成第二屏蔽层，所述第二屏蔽层与所述第一金属键合层电性连接。
优选地，在所述将所述第一金属键合层与所述第二金属键合层键合之后，在所述从所述晶圆的第二表面向所述基板进行半切割步骤之前，还包括：
对所述基板的第四表面进行减薄；
刻蚀所述基板和所述钝化层的中间区域，形成开孔，所述开孔至少贯穿所述基板、所述钝化层，暴露出所述焊垫；
填充所述开孔，形成导电结构。
优选地，在所述从所述晶圆的第二表面向所述基板进行半切割步骤之后，还包括：
对所述基板的第四表面进行减薄；
刻蚀所述基板和所述钝化层的中间区域，形成开孔，所述开孔至少贯穿所述基板、所述钝化层，暴露出所述焊垫；
填充所述开孔，形成导电结构。
优选地，所述刻蚀所述基板和所述钝化层的中间区域，形成开孔，具体包括：
在所述减薄后基板背离所述第三表面的表面通过刻蚀工艺，依次刻蚀所述基板、所述第二金属键合层和所述钝化层，暴露出所述焊垫，形成开孔。
优选地，在所述填充所述开孔，形成导电结构之后，还包括：
在所述导电结构表面植球。
优选地，所述在所述钝化层上形成第一金属键合层，具体包括：
在所述钝化层上开设第一凹槽；
采用镶嵌式工艺填充所述第一凹槽，形成所述第一金属键合层，所述第一金属键合层背离所述钝化层的表面与所述钝化层背离所述焊垫的表面齐平。
优选地，在形成所述第一金属键合层后，还包括：
平坦化所述第一金属键合层和所述钝化层的表面，使得所述第一金属键合层和所述钝化层的表面齐平。
优选地，所述提供基板，所述基板包括相对设置的第三表面和第四表面，所述基板的第三表面内形成有第二金属键合层，具体包括：
提供基板基体，所述基板基体包括相对设置的第三表面和第四表面；
在所述第三表面开设第二凹槽；
采用镶嵌式工艺填充所述第二凹槽，形成所述第二金属键合层，所述第二金属键合层背离所述基板的表面与所述第三表面齐平；
形成第一屏蔽层，所述第一屏蔽层与所述第二金属键合层相接，且在所述晶圆和所述基板键合后，所述第一屏蔽层与所述功能电路区相对应。
优选地，在所述形成所述第二金属键合层之后还包括：
平坦化所述第二金属键合层和所述基板基体的表面，使得所述第二金属键合层和所述基板基体的表面齐平。
优选地，在所述形成第一屏蔽层之前还包括：
在所述第三表面开设第三凹槽，所述第三凹槽的位置与键合后所述晶圆上的功能电路区的位置相对设置。
优选地，所述第一屏蔽层和所述第二屏蔽层的材质相同，均为金属材质。
优选地，所述第一金属键合层和所述第二金属键合层的材质相同，均为金属材质。
本发明还提供一种芯片封装结构，其特征在于，采用上面任意一项所述的芯片封装方法制作形成，所述芯片封装结构包括：
相对设置的晶圆和基板；
所述晶圆朝向所述基板的表面设置功能电路区和位于所述功能电路区周围的焊垫；
位于所述焊垫上，且与所述基板表面贴合的钝化层；
位于所述钝化层背离所述晶圆的表面内的第一金属键合层；
位于所述基板朝向所述晶圆的表面内的第二金属键合层，其中，所述第一金属键合层和所述第二金属键合层之间形成键合界面；
位于所述基板内的导电结构，所述导电结构至少贯穿所述基板和所述钝化层，与所述焊垫电性连接；
覆盖所述基板朝向所述晶圆的表面，且与所述第二金属键合层电性相接的第一屏蔽层；
覆盖所述晶圆除朝向所述基板的表面之外的表面、以及所述钝化层的侧壁的第二屏蔽层。
优选地，还包括位于所述导电结构上的植球。
优选地，所述第一屏蔽层和所述第二屏蔽层的材质相同，均为金属材质。
优选地，所述第一屏蔽层的材质为铜、银、镍或者镍铁合金。
优选地，所述第一金属键合层和所述第二金属键合层的材质相同，均为金属材质。
优选地，所述第一金属键合层的材质包括铜、金或铜锡合金。
优选地，所述第一金属键合层的厚度范围为100nm-1000nm，包括端点值。
优选地，所述钝化层的厚度范围为1μm-5μm，包括端点值。
优选地，所述钝化层的材质包括Si、无定形态的AlN、Si 3N 4或氧化硅。
优选地，所述第一金属键合层与所述第二金属键合层的材质相同。
优选地，所述第二金属键合层的厚度范围为1μm-5μm，包括端点值。
优选地，所述基板厚度范围为30μm-100μm，包括端点值。
优选地，所述基板朝向所述晶圆的表面，且与所述功能电路区对应的区域还设置有凹槽。
优选地，所述芯片封装结构为包含滤波器的芯片，所述滤波器对应的所述功能电路区为谐振电路。
经由上述的技术方案可知，本发明提供的芯片封装方法，通过在晶圆的焊垫上设置钝化层，然后在钝化层上形成第一金属键合层，在基板上形成第二金属键合层，通过第一金属键合层和第二金属键合层的键合，将基板和晶圆键合封装在一起，基板上设置有第一屏蔽层，所述第一屏蔽层与第二金属键合层相接设置；在晶圆和基板键合后，对晶圆进行半切割，切割到暴露第一金属键合层，再形成第二屏蔽层，第二屏蔽层与第一金属键合层电性连接，从而得到由第一屏蔽层、第二金属键合层、第二屏蔽层和第一金属键合层共同组成的电磁屏蔽结构，该屏蔽结构近似封闭，进而提高了电磁屏蔽效果。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对 实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为本发明实施例提供的一种芯片封装方法流程图；
图2-图17为本发明实施例提供的一种芯片封装方法对应工艺图；
图18为本发明实施例提供的一种芯片封装结构示意图；
图19为本发明实施例提供的另一种芯片封装结构示意图；
图20为本发明实施例提供的又一种芯片封装结构示意图。
具体实施方式
正如背景技术部分所述，现有技术中通过加金属防护盖实现电磁屏蔽。但是效果不太理想。
发明人发现，增加金属盖，造成晶圆级芯片封装尺寸较大，而且金属盖通常加载芯片封装结构的一侧，并非封闭结构，从而造成电磁屏蔽效果不太好。
基于此，本发明提供一种芯片封装方法，包括：
提供晶圆，所述晶圆包括相对设置的第一表面和第二表面，所述晶圆的第一表面上至少形成有两个功能电路区和位于所述功能电路区周围的多个焊垫；
在所述焊垫上形成钝化层，所述钝化层包括中间区域和围绕中间区域的边缘区域；
在所述钝化层上形成第一金属键合层，所述第一金属键合层覆盖所述钝化层的边缘区域；
提供基板，所述基板包括相对设置的第三表面和第四表面，所述基板的第三表面内形成有与所述第一金属键合层待键合的第二金属键合层，以及在所述晶圆和所述基板键合后，与所述功能电路区对应设置的第一屏蔽层，且，所述第一屏蔽层与所述第二金属键合层相接；
将所述第一金属键合层与所述第二金属键合层键合，所述第二金属键 合层至少暴露所述钝化层的部分中间区域，使得所述第三表面与所述钝化层背离所述晶圆的表面贴合在一起；
从所述晶圆的第二表面向所述基板进行半切割，切割凹槽至少暴露所述第一金属键合层；
在所述晶圆的第二表面以及所述切割凹槽内形成第二屏蔽层，所述第二屏蔽层与所述第一金属键合层电性连接。
本发明提供的芯片封装方法，通过在晶圆的焊垫上设置钝化层，然后在钝化层上形成第一金属键合层，在基板上形成第二金属键合层，通过第一金属键合层和第二金属键合层的键合，将基板和晶圆键合封装在一起，基板上设置有第一屏蔽层，所述第一屏蔽层与第二金属键合层相接设置；在晶圆和基板键合后，对晶圆进行半切割，切割到暴露第一金属键合层，再形成第二屏蔽层，第二屏蔽层与第一金属键合层电性连接，从而得到由第一屏蔽层、第二金属键合层、第二屏蔽层和第一金属键合层共同组成的电磁屏蔽结构，该屏蔽结构近似封闭，进而提高了电磁屏蔽效果。
另外，由于焊垫和金属键合层之间设置有钝化层，钝化层使得焊垫仅作为导电结构，而不作为金属键合层使用，从而能够在焊垫上方，且避开金属键合层的位置，设置硅通孔，将晶圆和基板之间的功能电路区电性连接至芯片封装结构外部，也即将硅通孔设置在焊垫上方，无需设置铜柱，占用功能电路区的面积，从而提高了功能电路区的使用面积，在芯片体积缩小时，避免功能电路区随之缩小，进而保证了芯片的电路性能。
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参见图1，图1为本发明实施例提供一种芯片封装方法流程图；所述芯片封装方法包括：
S101：提供晶圆，所述晶圆包括相对设置的第一表面和第二表面，所述晶圆的第一表面上至少形成有两个功能电路区和位于所述功能电路区周围的多个焊垫；
需要说明的是，本发明实施例中不限定芯片的具体类型，以滤波器芯片为例进行说明，滤波器芯片利用了声表面波或体声波原理来设计得到，封装的时候必须在谐振电路单元一侧形成一个没有任何介质接触的空气腔，以保证声波不会被传导和耗散，保证声波是按照设计的模式来进行谐振，以得到所需要的频率输出，因此所有的滤波器芯片封装的时候谐振单元一侧需要一个空腔。
请参见图2，图2为晶圆的剖面结构示意图；晶圆包括相对设置的第一表面和第二表面，其中，第一表面在图2中为上表面，第二表面在图2中为下表面，本实施例中并未以标号示出。在晶圆1的第一表面形成有滤波器的谐振电路11和焊垫12，需要说明的是，在晶圆切割之前，通常在晶圆上设置阵列排布的滤波器单元10，从而实现批量生产。滤波器单元10均包括谐振电路11和焊垫12。
本实施例中滤波器芯片对应的功能电路区为谐振电路，在其他实施例中，根据芯片功能的设计不同，功能电路区的电路可以是不同的结构。
S102：在所述焊垫上形成钝化层，所述钝化层包括中间区域和围绕中间区域的边缘区域；
如图3所示，在焊垫12上形成钝化层2，需要说明的是本实施例中不限定钝化层的具体位置。本实施例中形成钝化层的工艺可以是沉积工艺，在焊垫表面上沉积形成钝化层。钝化层的材质可以是Si、无定形态的AlN、Si 3N 4或氧化硅中的一种。为了方便钝化层的沉积，可选的，形成在相邻两个功能电路区之间的焊垫上的钝化层，可以连成一个区域，便于钝化层的制作。
本实施例中不限定所述钝化层的具体厚度，根据形成的芯片结构不同，可以设置不同的厚度，需要说明的是，以滤波器芯片为例，由于滤波器芯片的谐振电路需要设置在空腔内，因此，本实施例中可以通过钝化层的厚 度来控制形成的空腔的厚度。本实施例中可选的，钝化层的厚度范围为1μm-5μm，包括端点值。
S103：在所述钝化层上形成第一金属键合层，所述第一金属键合层覆盖所述钝化层的边缘区域；
本实施例中所述第一金属键合层覆盖钝化层的边缘区域，是为了后续对应设置第二金属键合层，使得第二金属键合层能够与基板内部的第一屏蔽层相接，从而能够得到类似封闭的电磁屏蔽结构。
需要说明的是，本实施例中不限定形成第一金属键合层的具体方式，为了保证后续第一金属键合层与第二金属键合层键合后，将基板的表面与钝化层的表面贴合。
请参见图4，本实施例中在钝化层2上形成第一金属键合层具体可以采用如下方法形成：
在所述钝化层2上开设第一凹槽20；本实施例中不限定第一凹槽的位置，根据预设的键合位置设计即可。
如图5所示，采用镶嵌式工艺填充所述第一凹槽20，形成所述第一金属键合层3，所述第一金属键合层3背离所述钝化层2的表面与所述钝化层2背离所述焊垫12的表面齐平。也即如图5中所示，第一金属键合层3和钝化层2的上表面齐平。
所述镶嵌式工艺，即为将第一金属键合层材质镶嵌在所述第一凹槽内，使得第一金属键合层与所述钝化层的表面齐平。
为了使得第一金属键合层与第二金属键合层的键合更加牢固，本实施例中还可以包括：平坦化所述第一金属键合层和所述钝化层的表面，使得所述第一金属键合层和所述钝化层的表面齐平。
本实施例中可选的，所述第一金属键合层的形成可以采用蒸镀工艺形成。
需要说明的是，为了保证钝化层的钝化作用，所述第一凹槽的底部需 要保证在焊垫的上方，且第一金属键合层和焊垫之间保留钝化层。本实施例中可选的，第一金属键合层的厚度范围为100nm-1000nm，包括端点值。
S104：提供基板，所述基板包括相对设置的第三表面和第四表面，所述基板的第三表面内形成有与所述第一金属键合层待键合的第二金属键合层，以及在所述晶圆和所述基板键合后，与所述功能电路区对应设置的第一屏蔽层，且，所述第一屏蔽层与所述第二金属键合层相接；
本实施例中提供基板包括：
提供基板基体，所述基板基体包括相对设置的第三表面和第四表面；
如图6所示，在基板4的第三表面开设第二凹槽40；
如图7所示，采用镶嵌式工艺填充所述第二凹槽40，形成所述第二金属键合层5，所述第二金属键合层5背离所述基板4的表面与所述第三表面齐平。也即如图7中所示，第二金属键合层5的上表面和基板4的上表面齐平。
请继续参见图7，在与功能电路区对应的位置设置第一屏蔽层5’，需要说明的是，本实施例中不限定第一屏蔽层的材质，只要能够实现电磁屏蔽作用的导电材料均可，可选的，所述第一屏蔽层的材质可以是金属，包括铜、银、镍或者镍铁合金。
本实施例中第二金属键合层5的位置根据第一金属键合层3的位置相应设置。
另外，为了保证第一金属键合层和第二金属键合层键合后，基板的第三表面和钝化层的表面贴合，还可以包括：平坦化所述第二金属键合层和所述基板基体的表面，使得所述第二金属键合层和所述基板基体的表面齐平。
需要说明的是，形成滤波器芯片的空腔时，除了控制钝化层的厚度可以控制空腔的厚度之外，还可以包括：在所述第三表面开设第三凹槽，所述第三凹槽的位置与键合后所述晶圆上的功能电路区的位置相对设置。
通过设置第三凹槽，形成空腔厚度较大的滤波器芯片，本实施例中不限定第三凹槽的形状，第三凹槽在垂直于第三表面的截面图中，第三凹槽可以是方形的凹槽，也可以是弧形凹槽，本实施例中对此不作限定。
S105：将所述第一金属键合层与所述第二金属键合层键合，所述第二金属键合层至少暴露所述钝化层的部分中间区域，使得所述第三表面与所述钝化层背离所述晶圆的表面贴合在一起；
如图8所示，采用键合工艺将第一金属键合层和第二金属键合层键合在一起，同时钝化层的表面和基板的表面紧密贴合。第二金属键合层暴露钝化层的部分中间区域，以便于后续制作TSV开孔。
本实施例中不限定第一金属键合层和第二金属键合层的材质，可选的，第一金属键合层和第二金属键合层的材质相同，均为金属材质。本实施例中采用金属材质进行键合，形成的是金属键合，金属键合相对于其他采用键合胶形成的键合结构，更加稳定，从而使得芯片封装结构具有较高的可靠性。本实施例中更加可选的，所述第一金属键合层的材质包括铜、金或铜锡合金。
本发明实施例中，不限定第一金属键合层和第二金属键合层在晶圆上的投影面积大小，也不限定第一金属键合层和第二金属键合层的具体位置，只要两者键合后能够使得晶圆和基板键合在一起，且第二金属键合层能够与第一屏蔽电性接触即可，保证芯片的可靠性的同时，便于后续形成近似封闭的屏蔽结构。
S106：从所述晶圆的第二表面向所述基板进行半切割，切割凹槽至少暴露所述第一金属键合层；
请参见图9，图9中对晶圆1的第二表面向所述基板进行半切割，得到切割凹槽6’。
S107：在所述晶圆的第二表面以及所述切割凹槽内形成第二屏蔽层，所述第二屏蔽层与所述第一金属键合层电性连接。
如图10所示，通过半切割暴露出第一金属键合层，然后在晶圆的第二 表面以及切割凹槽形成第二屏蔽层7’，使得第二屏蔽层与第一金属键合层电性连接，从而形成电磁屏蔽结构的一部分。
由于第一金属键合层3和第二金属键合层5键合在一起，使得第一屏蔽层5’、第二金属键合层5、第一金属键合层3和第二屏蔽层7’组成近似封闭的电磁屏蔽结构。
至此，本发明提供的芯片封装方法形成芯片半成品结构。
需要说明的是，在后续还可以包括形成TSV通孔，将电路内部信号传输出外部的结构。本实施例中形成TSV通孔的步骤可以是位于半切割步骤之前，也可以位于半切割之后。
如图11-13所示，为在半切割步骤之前进行TSV开孔制作，其包括：
请参见图11，对所述基板的第四表面进行减薄；
减薄基板以为后续制作开孔做准备，因此，减薄后基板4’的厚度以达到开孔的要求。本实施例中不限定减薄后基板的具体厚度，为方便后续开孔制作，且满足芯片的可靠性要求，可选的，减薄后基板的厚度H范围为30μm-100μm，包括端点值。
请参见图12，刻蚀所述基板和所述钝化层的中间区域，形成开孔，所述开孔至少贯穿所述基板、所述钝化层，暴露出所述焊垫；
请参见图13，填充所述开孔，形成导电结构7。
需要说明的是，先制作TSV通孔，再进行半切割工艺，对于避免晶圆破裂的控制难度较大，为此，本发明实施例还可以先进行半切割，再进行TSV开孔。
如图14-16所示，为在半切割步骤之后进行TSV开孔制作，其包括：
请参见图14，对所述基板的第四表面进行减薄；
减薄基板以为后续制作开孔做准备，因此，减薄后基板4’的厚度以达到开孔的要求。本实施例中不限定减薄后基板的具体厚度，为方便后续开孔制作，且满足芯片的可靠性要求，可选的，减薄后基板的厚度H范围为 30μm-100μm，包括端点值。
请参见图15，刻蚀所述基板和所述钝化层的中间区域，形成开孔，所述开孔至少贯穿所述基板、所述钝化层，暴露出所述焊垫；
请参见图16，填充所述开孔，形成导电结构7。
如图12和图15所示，从基板的减薄面进行刻蚀，依次刻蚀基板基体和钝化层，得到开孔6，开孔6暴露焊垫12。
需要说明的是，本实施例中开孔的位置可以仅贯穿基板和钝化层，而不接触第一金属键合层和第二金属键合层。也可以是开孔的侧壁单独与第一金属键合层接触，或单独第二金属键合层接触，又或者与第一金属键合层和第二金属键合层均接触，本实施例中对此不作限定。
需要说明的是，在所述减薄后基板背离所述第三表面的表面通过刻蚀工艺，依次刻蚀所述基板、所述第二金属键合层和所述钝化层，暴露出所述焊垫，形成开孔。
在本发明的其他实施例中，若需要将电路内部的结构引出，从而接地，本实施例中，还可以如图17所示，在所述减薄后基板4’背离所述第三表面的表面通过刻蚀工艺，依次刻蚀所述基板4’、所述第二金属键合层5、所述第一金属键合层3和所述钝化层2，暴露出所述焊垫12，形成开孔。也即后续填充开孔后，开孔内的金属与第一金属键合层和第二金属键合层的金属电性连接，从而实现接地。
又或者，制作开孔时，只贯穿基板、第二金属键合层、钝化层；又或者制作开孔时，只贯穿基板、第一金属键合层、钝化层。本实施例中对此不作限定，只要在需要设置接地时，可以利用金属键合层同时作为接地环使用，从而进一步节省芯片的空间。
在所述开孔中填充导电材料形成导电结构7后，将晶圆上的焊垫与外界电性连接。本实施例中为了形成能够直接与其他元器件电性连接的芯片结构，在填充开孔形成导电结构之后，还包括在填充后的开孔上方植球，植球与导电结构电性连接。
最后，沿背离半切割得到的凹槽的另一面进行切割，形成多个芯片封装结构。
通过切割晶圆得到多个单独的芯片封装结构，如图18所示，为本发明实施例中提供的芯片封装结构示意图。图18中，左侧电连接部分，第二金属键合层5被开孔贯穿，导电结构7与第二金属键合层5电性连接，从而将内部电路的结构引出，用于接地。在本发明的其他实施例中，还可以如图17所示，开孔不仅贯穿第二金属键合层5还贯穿第一金属键合层3，用于将内部电路引出，用于接地。
本发明实施例提供的芯片封装方法，通过在晶圆的焊垫上设置钝化层，然后在钝化层上形成第一金属键合层，在基板上形成第二金属键合层，通过第一金属键合层和第二金属键合层的键合，将基板和晶圆键合封装在一起，基板上设置有第一屏蔽层，所述第一屏蔽层与第二金属键合层相接设置；在晶圆和基板键合后，对晶圆进行半切割，切割到暴露第一金属键合层，再形成第二屏蔽层，第二屏蔽层与第一金属键合层电性连接，从而得到由第一屏蔽层、第二金属键合层、第二屏蔽层和第一金属键合层共同组成的电磁屏蔽结构，该屏蔽结构近似封闭，进而提高了电磁屏蔽效果。
基于相同的发明构思，本发明还提供一种芯片封装结构，采用上述芯片封装方法制作形成，请参见图18，所述芯片封装结构包括：
相对设置的晶圆1和基板4’；
所述晶圆1朝向所述基板4’的表面设置功能电路区和位于所述功能电路区周围的焊垫12；
位于所述焊垫12上，且与所述基板4’表面贴合的钝化层2；
位于所述钝化层2背离所述晶圆1的表面内的第一金属键合层3；
位于所述基板4’朝向所述晶圆1的表面内的第二金属键合层5，其中，所述第一金属键合层3和所述第二金属键合层5之间形成键合界面；
位于所述基板4’内的导电结构7，所述导电结构7至少贯穿所述基板4’ 和所述钝化层2，且与所述焊垫12电性连接；
覆盖所述基板4’朝向所述晶圆1的表面，且与所述第二金属键合层5电性相接的第一屏蔽层5’；
覆盖所述晶圆1除朝向所述基板4’的表面之外的表面、以及所述钝化层2的侧壁的第二屏蔽层7’。
为方便后续芯片可以直接使用，本实施例中导电结构7上方还可以包括植球8。
本发明实施例中不限定各个结构的参数和材质，可选的，所述第一屏蔽层和所述第二屏蔽层的材质相同，均为金属材质。所述第一屏蔽层的材质为铜、银、镍或者镍铁合金。所述第一金属键合层的厚度范围为100nm-1000nm，包括端点值。所述钝化层的厚度范围为1μm-5μm，包括端点值。所述钝化层的材质包括Si、无定形态的AlN、Si 3N 4或氧化硅。所述第一金属键合层与所述第二金属键合层的材质相同。所述第一金属键合层的材质包括铜、金或铜锡合金。所述第二金属键合层的厚度范围为1μm-5μm，包括端点值。所述基板厚度范围为30μm-100μm，包括端点值。
当所述芯片结构为滤波器芯片时，基板朝向所述晶圆的表面，且与所述功能电路区对应的区域还设置有凹槽9，如图19所示，基板上设置有与谐振电路相对应的凹槽，所述凹槽可以是弧形凹槽，也可以是方形凹槽，本实施例中对此不做限定，如图19所示为弧形凹槽。
另外，当需要将谐振电路中的信号连接到芯片外时，还可以在芯片中间设置TSV通孔，同样的设置结构与键合区(也即第一金属键合层和第二金属键合层以及TSV所在区域)相同，如图20中的20所示，键合结构包括位于晶圆上的焊垫，位于焊垫上的钝化层，位于钝化层上的第一金属键合层和第二金属键合层，以及依次贯穿基板、第二金属键合层、第一金属键合层、钝化层，而暴露出焊垫的TSV开孔。
需要说明的是，基于本发明构思，还可以提供多种结构的芯片封装结构，本发明实施例中对此不作一一详述。
另外，本发明实施例中提供的封装方法，还可以同时封装多个滤波器的晶圆结构，从而得到多颗滤波器封装结构，包括二合一、三合一、四合一等多合一的滤波器产品，还有双工器、四工器、六工器、八工器等多工 器产品，直接实现最小的产品结构和最佳性能。
本发明实施例提供的芯片封装结构，由于采用上面实施例中所述的芯片封装方法，能够直接利用现有的工艺和设备，且具有成熟的材料，适用于所有滤波器类型(SAW和BAW的所有类型)的封装，同时，也适用于单颗和多颗的滤波器的封装，而且，还可以适合各种蜂窝终端需要的包括滤波器的射频前端模块(SIP module)的封装。其中蜂窝终端包括2G/3G/4G/5G的手机，WiFi，Pad，智能手表，IOT，汽车等终端场景中的终端设备。
本发明实施例中提供的芯片封装结构，采用上面实施例中所述的芯片封装方法封装得到，通过在晶圆的焊垫上设置钝化层，然后在钝化层上形成第一金属键合层，在基板上形成第二金属键合层，通过第一金属键合层和第二金属键合层的键合，将基板和晶圆键合封装在一起，基板上设置有第一屏蔽层，所述第一屏蔽层与第二金属键合层相接设置；在晶圆和基板键合后，对晶圆进行半切割，切割到暴露第一金属键合层，再形成第二屏蔽层，第二屏蔽层与第一金属键合层电性连接，从而得到由第一屏蔽层、第二金属键合层、第二屏蔽层和第一金属键合层共同组成的电磁屏蔽结构，该屏蔽结构近似封闭，进而提高了电磁屏蔽效果。
另外，由于焊垫和金属键合层之间设置有钝化层，钝化层使得焊垫仅作为导电结构，而不作为金属键合层使用，从而能够在焊垫上方，且避开金属键合层的位置，设置硅通孔，将晶圆和基板之间的功能电路区电性连接至芯片封装结构外部，也即将硅通孔设置在焊垫上方，无需设置铜柱，占用功能电路区的面积，从而提高了功能电路区的使用面积，在芯片体积缩小时，避免功能电路区随之缩小，进而保证了芯片的电路性能。
需要说明的是，本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使 得包括一系列要素的物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括上述要素的物品或者设备中还存在另外的相同要素。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (25)

  1. 一种芯片封装方法，其特征在于，包括：
    提供晶圆，所述晶圆包括相对设置的第一表面和第二表面，所述晶圆的第一表面上至少形成有两个功能电路区和位于所述功能电路区周围的多个焊垫；
    在所述焊垫上形成钝化层，所述钝化层包括中间区域和围绕中间区域的边缘区域；
    在所述钝化层上形成第一金属键合层，所述第一金属键合层覆盖所述钝化层的边缘区域；
    提供基板，所述基板包括相对设置的第三表面和第四表面，所述基板的第三表面内形成有与所述第一金属键合层待键合的第二金属键合层，以及在所述晶圆和所述基板键合后，与所述功能电路区对应设置的第一屏蔽层，且，所述第一屏蔽层与所述第二金属键合层相接；
    将所述第一金属键合层与所述第二金属键合层键合，所述第二金属键合层至少暴露所述钝化层的部分中间区域，使得所述第三表面与所述钝化层背离所述晶圆的表面贴合在一起；
    从所述晶圆的第二表面向所述基板进行半切割，切割凹槽至少暴露所述第一金属键合层；
    在所述晶圆的第二表面以及所述切割凹槽内形成第二屏蔽层，所述第二屏蔽层与所述第一金属键合层电性连接。
  2. 根据权利要求1所述的芯片封装方法，其特征在于，在所述将所述第一金属键合层与所述第二金属键合层键合之后，在所述从所述晶圆的第二表面向所述基板进行半切割步骤之前，还包括：
    对所述基板的第四表面进行减薄；
    刻蚀所述基板和所述钝化层的中间区域，形成开孔，所述开孔至少贯穿所述基板、所述钝化层，暴露出所述焊垫；
    填充所述开孔，形成导电结构。
  3. 根据权利要求1所述的芯片封装方法，其特征在于，在所述从所述晶圆的第二表面向所述基板进行半切割步骤之后，还包括：
    对所述基板的第四表面进行减薄；
    刻蚀所述基板和所述钝化层的中间区域，形成开孔，所述开孔至少贯穿所述基板、所述钝化层，暴露出所述焊垫；
    填充所述开孔，形成导电结构。
  4. 根据权利要求2或3所述的芯片封装方法，其特征在于，所述刻蚀所述基板和所述钝化层的中间区域，形成开孔，具体包括：
    在所述减薄后基板背离所述第三表面的表面通过刻蚀工艺，依次刻蚀所述基板、所述第二金属键合层和所述钝化层，暴露出所述焊垫，形成开孔。
  5. 根据权利要求2或3所述的芯片封装方法，其特征在于，在所述填充所述开孔，形成导电结构之后，还包括：
    在所述导电结构表面植球。
  6. 根据权利要求1所述的芯片封装方法，其特征在于，所述在所述钝化层上形成第一金属键合层，具体包括：
    在所述钝化层上开设第一凹槽；
    采用镶嵌式工艺填充所述第一凹槽，形成所述第一金属键合层，所述第一金属键合层背离所述钝化层的表面与所述钝化层背离所述焊垫的表面齐平。
  7. 根据权利要求6所述的芯片封装方法，其特征在于，在形成所述第一金属键合层后，还包括：
    平坦化所述第一金属键合层和所述钝化层的表面，使得所述第一金属键合层和所述钝化层的表面齐平。
  8. 根据权利要求1所述的芯片封装方法，其特征在于，所述提供基板，所述基板包括相对设置的第三表面和第四表面，所述基板的第三表面内形成有第二金属键合层，具体包括：
    提供基板基体，所述基板基体包括相对设置的第三表面和第四表面；
    在所述第三表面开设第二凹槽；
    采用镶嵌式工艺填充所述第二凹槽，形成所述第二金属键合层，所述第二金属键合层背离所述基板的表面与所述第三表面齐平；
    形成第一屏蔽层，所述第一屏蔽层与所述第二金属键合层相接，且在所述晶圆和所述基板键合后，所述第一屏蔽层与所述功能电路区相对应。
  9. 根据权利要求8所述的芯片封装方法，其特征在于，在所述形成所述第二金属键合层之后还包括：
    平坦化所述第二金属键合层和所述基板基体的表面，使得所述第二金属键合层和所述基板基体的表面齐平。
  10. 根据权利要求8所述的芯片封装方法，其特征在于，在所述形成第一屏蔽层之前还包括：
    在所述第三表面开设第三凹槽，所述第三凹槽的位置与键合后所述晶圆上的功能电路区的位置相对设置。
  11. 根据权利要求1所述的芯片封装方法，其特征在于，所述第一屏蔽层和所述第二屏蔽层的材质相同，均为金属材质。
  12. 根据权利要求1所述的芯片封装方法，其特征在于，所述第一金属键合层和所述第二金属键合层的材质相同，均为金属材质。
  13. 一种芯片封装结构，其特征在于，采用权利要求1-12任意一项所述的芯片封装方法制作形成，所述芯片封装结构包括：
    相对设置的晶圆和基板；
    所述晶圆朝向所述基板的表面设置功能电路区和位于所述功能电路区 周围的焊垫；
    位于所述焊垫上，且与所述基板表面贴合的钝化层；
    位于所述钝化层背离所述晶圆的表面内的第一金属键合层；
    位于所述基板朝向所述晶圆的表面内的第二金属键合层，其中，所述第一金属键合层和所述第二金属键合层之间形成键合界面；
    位于所述基板内的导电结构，所述导电结构至少贯穿所述基板和所述钝化层，与所述焊垫电性连接；
    覆盖所述基板朝向所述晶圆的表面，且与所述第二金属键合层电性相接的第一屏蔽层；
    覆盖所述晶圆除朝向所述基板的表面之外的表面、以及所述钝化层的侧壁的第二屏蔽层。
  14. 根据权利要求13所述的芯片封装结构，其特征在于，还包括位于所述导电结构上的植球。
  15. 根据权利要求13所述的芯片封装结构，其特征在于，所述第一屏蔽层和所述第二屏蔽层的材质相同，均为金属材质。
  16. 根据权利要求15所述的芯片封装结构，其特征在于，所述第一屏蔽层的材质为铜、银、镍或者镍铁合金。
  17. 根据权利要求13所述的芯片封装结构，其特征在于，所述第一金属键合层和所述第二金属键合层的材质相同，均为金属材质。
  18. 根据权利要求17所述的芯片封装结构，其特征在于，所述第一金属键合层的材质包括铜、金或铜锡合金。
  19. 根据权利要求13所述的芯片封装结构，其特征在于，所述第一金属键合层的厚度范围为100nm-1000nm，包括端点值。
  20. 根据权利要求13所述的芯片封装结构，其特征在于，所述钝化层的厚度范围为1μm-5μm，包括端点值。
  21. 根据权利要求13所述的芯片封装结构，其特征在于，所述钝化层的材质包括Si、无定形态的AlN、Si 3N 4或氧化硅。
  22. 根据权利要求13所述的芯片封装结构，其特征在于，所述第二金属键合层的厚度范围为1μm-5μm，包括端点值。
  23. 根据权利要求13所述的芯片封装结构，其特征在于，所述基板厚度范围为30μm-100μm，包括端点值。
  24. 根据权利要求13所述的芯片封装结构，其特征在于，所述基板朝向所述晶圆的表面，且与所述功能电路区对应的区域还设置有凹槽。
  25. 根据权利要求13所述的芯片封装结构，其特征在于，所述芯片封装结构为包含滤波器的芯片，所述滤波器对应的所述功能电路区为谐振电路。
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