CN102082128B - 半导体封装和半导体管芯安装到tsv衬底相对侧的方法 - Google Patents

半导体封装和半导体管芯安装到tsv衬底相对侧的方法 Download PDF

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CN102082128B
CN102082128B CN201010537411.6A CN201010537411A CN102082128B CN 102082128 B CN102082128 B CN 102082128B CN 201010537411 A CN201010537411 A CN 201010537411A CN 102082128 B CN102082128 B CN 102082128B
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substrate
semiconductor element
semiconductor
sealant
semiconductor packages
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CN102082128A (zh
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崔大植
金钟虎
李亨民
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Stats Chippac Pte Ltd
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Abstract

半导体封装和半导体管芯安装到TSV衬底相对侧的方法。半导体封装具有被形成为通过衬底的第一导电通路。具有第一导电通路的衬底被安装到第一载体。第一半导体管芯被安装到衬底的第一表面。第一密封剂被沉积在第一半导体管芯和第一载体上。第一载体被除去。具有第一密封剂的第一管芯和衬底被安装到第二载体。第二半导体管芯被安装到与衬底的第一表面相对的该衬底的第二表面。第二密封剂被沉积到第二管芯上。第二载体被除去。凸块被形成在衬底的第二表面上。导电层可以被安装到第一管芯上。第二导电通路可以被形成为通过第一密封剂并电连接到第一导电通路。该半导体封装是可堆叠的。

Description

半导体封装和半导体管芯安装到TSV衬底相对侧的方法
技术领域
本发明总体上涉及半导体器件，并且更具体地说，本发明涉及半导体封装和形成TSV衬底以及将半导体管芯安装到TSV衬底的相对侧的方法。
背景技术
在现代电子产品中通常会发现有半导体器件。半导体器件在电部件的数量和密度上有变化。分立的半导体器件一般包括一种电部件，例如发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器、以及功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体器件通常包括数百到数百万的电部件。集成半导体器件的实例包括微控制器、微处理器、电荷耦合器件(CCD)、太阳能电池、以及数字微镜器件(DMD)。
半导体器件执行多种功能，例如高速计算、发射和接收电磁信号、控制电子器件、将日光转换成电、以及为电视显示器生成可视投影。在娱乐、通信、功率转换、网络、计算机、以及消费品领域中有半导体器件的存在。在军事应用、航空、汽车、工业控制器、以及办公设备中也有半导体器件的存在。
半导体器件利用半导体材料的电特性。半导体材料的原子结构允许通过施加电场或基极电流(base current)或者通过掺杂工艺来操纵(manipulated)它的导电性。掺杂把杂质引入半导体材料中以操纵和控制半导体器件的导电性。
半导体器件包括有源和无源电结构。有源结构(包括双极和场效应晶体管)控制电流的流动。通过改变掺杂水平并且施加电场或基极电流，晶体管促进或限制电流的流动。无源结构(包括电阻器、电容器、和电感器)产生执行多种电功能所必需的电压和电流之间的关系。无源和有源结构被电连接以形成电路，所述电路能够使半导体器件执行高速计算和其它有用的功能。
通常利用两个复杂的制造工艺来制造半导体器件，即前端制造和后端制造，每个可能包括数百个步骤。前端制造包括在半导体晶片的表面上形成多个管芯。每个管芯通常相同并且包括通过电连接有源和无源部件形成的电路。后端制造包括从已完成的晶片单体化(singulating)单个管芯并且封装管芯以提供结构支撑和环境隔离。
半导体制造的一个目标是制造更小的半导体器件。更小的器件通常消耗更少功率、具有更高的性能、并且能够被更有效地制造。另外，更小的半导体器件具有更小的占地面积(footprint)，其对于更小的终端产品而言是期望的。通过前端工艺的改善产生具有更小、更高密度的有源和无源部件的管芯可以实现更小的管芯尺寸。通过电互连和封装材料的改善，后端工艺可以产生具有更小占地面积的半导体器件封装。
许多半导体封装使用堆叠的半导体管芯以进行垂直集成。该堆叠的半导体管芯与所形成的通过密封剂的导电通路、结合引线或凸块电连接。半导体管芯之间的垂直互连消耗空间并增加了封装的整体高度，还使得制造成本更高。
发明内容
存在对以最小的空间堆叠半导体管芯用于垂直电互连的需要。因此，在一个实施例中，本发明是一种制作半导体封装的方法，该方法包括以下步骤：提供晶片级衬底，形成通过该晶片级衬底的多个通路，在所述通路中沉积导电材料以形成通过该晶片级衬底的第一导电通路，提供第一载体，将具有第一导电通路的该晶片级衬底安装到第一载体，将第一半导体管芯安装到该晶片级衬底的第一表面，在第一半导体管芯和第一载体上沉积第一密封剂，除去第一载体，提供第二载体，利用第一密封剂将第一半导体管芯和晶片级衬底安装到第二载体，将第二半导体管芯安装到晶片级衬底的与该晶片级衬底的第一表面相对的第二表面，在第二半导体管芯上沉积第二密封剂，以及除去第二载体。
在另一实施例中，本发明是一种制作半导体封装的方法，该方法包括以下步骤：提供衬底，形成通过该衬底的第一导电通路，将具有第一导电通路的该衬底安装到第一载体，将第一半导体管芯安装到该衬底的第一表面，在第一半导体管芯和第一载体上沉积第一密封剂，除去第一载体，利用第一密封剂将第一半导体管芯和衬底安装到第二载体，将第二半导体管芯安装到与衬底的第一表面相对的该衬底的第二表面，在第二半导体管芯上沉积第二密封剂，以及除去第二载体。
在另一实施例中，本发明是一种制作半导体封装的方法，该方法包括以下步骤：提供衬底，该衬底具有通过该衬底的第一导电通路，将第一半导体管芯安装到该衬底的第一表面，在第一半导体管芯上沉积第一密封剂，将第二半导体管芯安装到与衬底的第一表面相对的该衬底的第二表面，以及在第二半导体管芯上沉积第二密封剂。
在另一实施例中，本发明是一种包括衬底的半导体封装，该衬底具有通过该衬底的第一导电通路。第一半导体管芯被安装到衬底的第一表面。第一密封剂被沉积在第一半导体管芯上。第二半导体管芯被安装到与衬底的第一表面相对的该衬底的第二表面。第二密封剂被沉积到第二半导体管芯上。
附图说明
图1示出具有安装到其表面的不同类型封装的PCB；
图2a-2c示出安装到所述PCB的典型半导体封装的更多细节；
图3a-3l示出形成TSV衬底和将半导体管芯安装到该TSV衬底的相对侧的工艺；
图4示出在半导体管芯上安装的金属层；
图5示出在TSV衬底上的密封剂中形成的导电通路；
图6示出在TSV衬底上的密封剂中形成的凸块；
图7示出堆叠的半导体封装，所述半导体封装的每一个的半导体管芯被安装到TSV衬底的相对侧；
图8示出被密封用于堆叠半导体封装的凸块；
图9示出被安装到半导体封装的第二TSV衬底，其中半导体管芯被安装到第一TSV衬底的相对侧；以及
图10示出堆叠的半导体封装，所述半导体封装的每一个的半导体管芯被安装到TSV衬底。
具体实施方式
参考附图在下列描述中的一个或多个实施例中描述本发明，在附图中相似的数字表示相同或类似的元件。虽然根据用来实现本发明的目的的最佳方式描述本发明，但是本领域技术人员将理解的是，它旨在覆盖可以被包含在由被下列公开和各图所支持的所附权利要求及其等效物限定的本发明的精神和范围内的替代物、变型和等效物。
一般利用两个复杂的制造工艺制造半导体器件：前端制造和后端制造。前端制造包括在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包括有源和无源电部件，所述有源和无源电部件被电连接以形成功能电路。有源电部件，例如晶体管和二极管，具有控制电流的流动的能力。无源电部件，例如电容器、电感器、电阻器、和变压器，产生执行电路功能所必需的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、刻蚀、和平面化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过例如离子注入或热扩散的技术将杂质引入到半导体材料中。掺杂工艺改变有源器件中的半导体材料的导电性，将半导体材料转变成绝缘体、导体，或响应于电场或基极电流动态改变半导体材料导电性。晶体管包括有变化的掺杂类型和程度的区域，所述区域根据需要被设置为使晶体管能够在施加电场或基极电流时促进或限制电流的流动。
由具有不同电特性的材料的层形成有源和无源部件。所述层可以通过部分地由被沉积的材料的类型决定的多种沉积技术形成。例如，薄膜沉积可以包括化学汽相沉积(CVD)、物理汽相沉积(PVD)、电解电镀、以及无电电镀(electroless plating)工艺。每个层通常被图案化以形成有源部件、无源部件、或部件之间的电连接的各部分。
可以利用光刻图案化所述层，所述光刻包括在将被图案化的层上沉积光敏材料，例如光致抗蚀剂。利用光将图案从光掩模转移到光致抗蚀剂。利用溶剂将经受光的光致抗蚀剂图案部分除去，暴露将被图案化的下面层的各部分。光致抗蚀剂的剩余物被除去，留下被图案化的层。可替换地，利用例如无电电镀或电解电镀的技术通过直接将材料沉积到通过先前的沉积/刻蚀工艺形成的区域或空隙中来图案化一些类型的材料。
在已有图案上沉积材料的薄膜可能会放大下面的图案并且引起不均匀的平面。需要均匀的平面来制造更小和更密集包装的有源和无源部件。可以利用平面化从晶片的表面除去材料和制造均匀平面。平面化包括利用抛光垫抛光晶片的表面。在抛光期间，磨料和腐蚀性化学品被添加到晶片的表面。组合的磨料机械作用和化学品腐蚀作用除去了任何不规则的表面形貌(topography)，产生均匀的平面。
后端制造指的是将已完成的晶片切割或单体化成单个管芯，并且然后封装管芯实现结构支撑和环境隔离。为单体化管芯，沿被叫做划片街区(saw street)或划线的晶片非功能区域刻划和断开所述晶片。利用激光切割工具或锯条来单体化晶片。在单体化之后，单个管芯被安装到封装衬底，所述封装衬底包括用来与其它系统部件互连的引脚或接触焊盘。形成在半导体管芯上的接触焊盘然后被连接到封装内的接触焊盘。可以利用焊料凸块、柱形凸块(stud bump)、导电胶、或引线结合(wirebond)来制作电连接。密封剂或其它成型材料被沉积到封装上以提供物理支撑和电隔离。已完成的封装然后被插入电系统中并且其它系统部件可以利用半导体器件的功能。
图1示出具有芯片载体衬底或印刷电路板(PCB)52的电子器件50，所述芯片载体衬底或印刷电路板(PCB)52具有多个安装在它的表面上的半导体封装。电子器件50可以具有一种半导体封装、或多种半导体封装，这取决于应用。为了说明的目的，在图1中示出不同类型的半导体封装。
电子器件50可以是利用半导体封装来执行一个或多个电功能的独立系统。可替换地，电子器件50可以是更大系统的子部件。例如，电子器件50可以是图形卡、网络接口卡、或能被插入计算机中的其它信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路(ASIC)、逻辑电路、模拟电路、RF电路、分立器件、或其它半导体管芯或电部件。
在图1中，PCB 52提供普通的衬底，用于安装在PCB上的半导体封装的结构支撑和电互连。利用蒸发、电解电镀、无电电镀、丝网印刷、或其它合适的金属沉积工艺将导电信号迹线(trace)54形成在PCB 52的表面上或各层内。信号迹线54提供半导体封装、安装的部件、以及其它外部系统部件中的每一个之间的电通信。迹线54也将电源和地连接提供给半导体封装中的每一个。
在一些实施例中，半导体器件可以具有两个封装级。第一级封装是用来将半导体管芯以机械和电的方式附着到中间载体的技术。第二级封装包括将所述中间载体以机械和电的方式附着到PCB。在其它实施例中，半导体器件可以仅具有第一级封装，其中管芯被以机械和电的方式直接安装到PCB。
为了说明的目的，几种第一级封装(包括引线结合封装56和倒装芯片58)被示出在PCB 52上。另外，几种第二级封装(包括球栅阵列(BGA)60、凸块芯片载体(BCC)62、双列直插式封装(DIP)64、栅格阵列(land grid array，LGA)66、多芯片模块(MCM)68、方形扁平无引脚封装(quad flat non-leaded package，QFN)70、以及方形扁平封装72)被示出安装在PCB 52上。根据系统要求，利用第一和第二级封装形式的任何组合配置的半导体封装的任何组合、以及其它电子部件，可以被连接到PCB 52。在一些实施例中，电子器件50包括单个附着的半导体封装，虽然其它实施例要求多个互连的封装。通过在单个衬底上组合一个或多个半导体封装，制造商可以将预先制作的部件并入电子器件和系统中。因为半导体封装包括复杂功能，所以可以利用更便宜的部件和流水线制造工艺来制造电子器件。所得到的器件较少可能失效并且制造起来花费较少，对用户而言导致更低的成本。
图2a-2c示出示范性半导体封装。图2a示出安装在PCB 52上的DIP 64的更多细节。半导体管芯74包括包含模拟或数字电路的有源区，所述模拟或数字电路被实现为形成在管芯内并且根据管芯的电设计被电互连的有源器件、无源器件、导电层、和介电层。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及形成在半导体管芯74的有源区内的其它电路元件。接触焊盘76是导电材料(例如铝(AL)、铜(Cu)、锡(Sn)、镍(N i)、金(Au)、或银(Ag))的一个或多个层，并且电连接到形成在半导体管芯74内的电路元件。在DIP 64的组装期间，利用金硅共晶层或粘附材料(例如热的环氧或环氧树脂)将半导体管芯74安装到中间载体78。封装体包括绝缘封装材料，例如聚合物或陶瓷。导体引线80和引线结合82在半导体管芯74和PCB 52之间提供电互连。密封剂84被沉积在封装上用于通过防止湿气与粒子进入所述封装并污染管芯74或引线结合82来进行环境保护。
图2b示出安装在PCB 52上的BCC 62的更多细节。半导体管芯88利用底层填料(underfill)或环氧树脂粘附材料92被安装到载体90上。引线结合94在接触焊盘96和98之间提供第一级包装(packing)互连。模塑料(molding compound)或密封剂100被沉积在半导体管芯88和引线结合94上以为所述器件提供物理支撑和电隔离。接触焊盘102利用电解电镀或无电电镀这样合适的金属沉积工艺形成在PCB52的表面上以防止氧化。接触焊盘102电连接到PCB 52中的一个或多个导电信号迹线54。凸块104被形成在BCC 62的接触焊盘98与PCB 52的接触焊盘102之间。
在图2c中，利用倒装芯片形式的第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区108包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计形成的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及在有源区108内的其它电路元件。半导体管芯58通过凸块110以机械和电的方式连接到载体106。
使用凸块112利用BGA形式的第二级封装将BGA 60以机械和电的方式连接到PCB 52。半导体管芯58通过凸块110、信号线114、以及凸块112电连接到PCB 52中的导电信号迹线54。模塑料或密封剂116被沉积在半导体管芯58和载体106上以为所述器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电轨迹的短导电路径以便减小信号传播距离、降低电容、并且改善总的电路性能。在另一个实施例中，半导体管芯58可以在没有中间载体106的情况下利用倒装芯片形式的第一级封装被以机械和电的方式直接连接到PCB 52。
相对于图1和2a-2c，图3a-31示出形成TSV衬底和将半导体管芯安装到TSV衬底的相对侧的工艺。在图3a中，半导体晶片120包括用于结构支撑的基底衬底材料122，例如硅、锗、砷化镓、磷化铟、或碳化硅。利用激光钻孔或深反应离子刻蚀(DRIE)形成通过衬底122的多个通路123。
在图3b中，利用电解电镀或无电电镀(electroless plating)将导电材料沉积在通路123中，以形成导电直通硅通路(TSV)124。导电TSV 124可以是Al，Cu，Sn，Ni，Au，Ag或其它适当的导电材料的一个或多个层。
在图3c中，利用PVD、CVD、印刷、旋涂、喷涂、烧结、或热氧化在TSV 124和衬底122的表面128上形成绝缘或钝化层126。绝缘层126可以是二氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、五氧化二钽(Ta2O5)、氧化铝(Al2O3)、或具有类似绝缘和结构特性的其它材料的一个或多个层。通过蚀刻工艺去除绝缘层126的一部分以暴露TSV 124。
利用图案化和金属沉积工艺(例如PVD、CVD、溅射、电解电镀和无电电镀)在绝缘层126的被除去的部分中的TSV 124和衬底122的表面128上形成导电层130。导电层130可以是Al，Cu，Sn，Ni，Au，Ag或其它适当的导电材料的一个或多个层。导电层130电连接到TSV124。导电层130的其它部分可以根据半导体器件的设计和功能是电共有的(electricallyc ommon)或被电隔离。
利用PVD、CVD、印刷、旋涂、喷涂、烧结、或热氧化在与衬底122的表面128相对的衬底122的表面134和TSV 124上形成绝缘或钝化层132。绝缘层132可以是SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似绝缘和结构特性的其它材料的一个或多个层。通过蚀刻工艺去除绝缘层132的一部分以暴露TSV 124。
利用图案化和金属沉积工艺(例如PVD、CVD、溅射、电解电镀和无电电镀)在绝缘层132的被除去的部分中的衬底122的表面134上形成导电层136。导电层136可以是Al，Cu，Sn，N i，Au，Ag或其它适当的导电材料的一个或多个层。导电层136电连接到TSV 124。导电层136的其它部分可以根据半导体器件的设计和功能是电共有的(electrically common)或被电隔离。
衬底或载体140包括临时或牺牲基底材料，例如硅、聚合物、聚合物复合物、金属、陶瓷、玻璃、玻璃环氧树脂、氧化铍、或用于结构支撑的其它合适的低成本、刚性材料。晶片级TSV衬底或中介层(interposer)138被安装到载体140上，如图3c和3d所示。
在图3e中，利用锯条或激光切割工具142切割形成间隙141，间隙141穿过半导体晶片120的衬底122向下直到载体140。锯条142不切断或削弱载体140，即，载体140保持其跨越衬底122的剩余部分的支撑特性。
在图3f中，半导体管芯或部件144被安装到衬底122。每个半导体管芯144具有形成在面向衬底122的表面128的有源表面148上的接触焊盘146。有源表面148包括模拟或数字电路，所述模拟或数字电路被实现为形成在管芯内并且根据管芯的电设计和功能电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面148内实现模拟电路或数字电路的其它电路元件，例如数字信号处理器(DSP)、ASIC、存储器、或其它信号处理电路。半导体管芯144也可以包括I PD，例如电感器、电容器、和电阻器，用于RF信号处理。多个凸块150形成在导电层130或接触焊盘146上并且被回流以将接触焊盘146电连接到导电层130。在一个实施例中，半导体管芯144被实施为倒装芯片形式的器件。
在图3g中，利用浆料印刷、挤压模塑、传递模塑、液体密封剂模塑、真空层压、旋涂、或其它合适的施加器将密封剂或模塑料156沉积在半导体管芯144、衬底122和载体140上。密封剂156可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂156不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。
在图3h中，衬底或载体158包括临时或牺牲基底材料，例如硅、聚合物、聚合物复合物、金属、陶瓷、玻璃、玻璃环氧树脂、氧化铍、或用于结构支撑的其它合适的低成本、刚性材料。图3a-3g中描述的结构被倒转并利用密封剂156安装到载体158。通过化学腐蚀、机械剥离、CMP、机械研磨、热烘、激光扫描、或湿法脱模来除去临时载体140。
在图3i中，将半导体管芯或部件160安装到TSV衬底138。每个半导体管芯160具有形成在面向TSV表面138的有源表面164上的接触焊盘162。有源表面164包括模拟或数字电路，所述模拟或数字电路被实现为形成在管芯内并且根据管芯的电设计和功能电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面164内实现模拟电路或数字电路的其它电路元件，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯160也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。多个凸块166形成在导电层136或接触焊盘162上并且被回流以将接触焊盘162电连接到导电层136。在一个实施例中，半导体管芯160被实施为倒装芯片形式的器件。
在图3j中，利用浆料印刷、挤压模塑、传递模塑、液体密封剂模塑、真空层压、旋涂、或其它合适的施加器将密封剂或模塑料168沉积在半导体管芯160上。密封剂168可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂168不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。
在图3k中，利用蒸发、电解电镀、无电电镀、球滴、或丝网印刷工艺将导电凸块材料沉积到导电层136上。所述凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、及其组合，可选的具有焊剂溶液。例如，所述凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将所述凸块材料结合到导电层136。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块170。在一些应用中，凸块170二次回流以改善到导电层136的电接触。凸块也可以被挤压结合到导电层136。凸块170表示一种可以形成在导电层136上的互连结构。所述互连结构也可以使用柱形凸块、微凸块、导电柱或其它电互连。
在图31中，通过化学腐蚀、机械剥离、CMP、机械研磨、热烘、激光扫描、或湿法脱模来除去临时载体158。利用锯条或激光切割工具172通过密封剂156将该结构单体化成单独的晶片级堆叠半导体封装174。
半导体管芯144和160被安装到晶片级TSV衬底或中介层138的相对侧并且与TSV 124电连接。通过将半导体管芯144和160堆叠在TSV衬底138的两侧来减小半导体封装174的厚度。热膨胀系数(CTE)可以被匹配，因为TSV衬底是用与半导体管芯144和160相类似的材料(例如硅)制成的。
图4示出类似于图3a-31中描述的结构的半导体封装178的实施例，其中金属层180安装到半导体管芯144，并且金属层182安装到半导体管芯160。在一个实施例中，金属层180和182用作热沉以耗散来自半导体管芯144和160的热能。金属层180和182可以是A1、Cu、或具有高热导率的其它材料，以为半导体管芯144和160提供热耗散。在热沉和半导体管芯之间的可选热界面(interface)材料，例如氧化铝、氧化锌、氮化硼、或粉状银帮助散布和耗散由半导体管芯144和160产生的热。
在另一实施例中，金属层180和182是电磁干扰(EMI)和射频干扰(RFI)屏蔽层。在这种情况下，屏蔽层180和182可以是Cu、Al、铁氧体或羰基铁(carbonyl iron)、不锈钢、镍银、低碳钢、硅铁钢、箔、环氧树脂、导电树脂和其它能够阻挡或吸收EMI、RFI和其它器件间干扰的金属和复合物。屏蔽层180和182还可以是非金属材料(例如碳黑)或铝片(aluminum flake)，以减小EMI和RFI的影响。屏蔽层180和182接地以转移EMI和RFI信号。
图5示出类似于图3a-31中描述的结构的半导体封装183的实施例，其中半导体管芯144较窄或TSV衬底138较宽以便为导电通路184腾出空间。利用激光钻孔或蚀刻工艺(例如DRIE)形成通过密封剂156的多个通路。使用电解电镀或无电电镀，利用Al、Cu、Sn、Ni、Au、Ag、钛(Ti)、W、多晶硅、或其它合适的导电材料来填充所述通路以形成导电通路184。
图6示出类似于图3a-31中描述的结构的半导体封装186的实施例，其中半导体管芯144较窄或TSV衬底138较宽以便为凸块188腾出空间。在沉积密封剂156之前，凸块188形成在导电层130上，类似于图3k。凸块188电连接到导电层130。
图7示出具有通过凸块170和188被电连接的两个堆叠半导体封装186的堆叠封装(package-on-package，PoP)。
图8示出类似于图6中描述的结构的半导体封装190的实施例，其中密封剂192形成在凸块170上。半导体封装190适于堆叠多个类似的半导体封装。
图9示出类似于图6中描述的结构的半导体封装196的实施例，其中TSV衬底198(类似于TSV衬底138)安装到半导体管芯144。TSV衬底198的TSV 200电连接到凸块188。
图10示出半导体封装202的PoP实施例，其中半导体封装186安装到半导体封装204。半导体封装204包括使用与图3a-3g中描述的类似工艺步骤制作的TSV衬底206和半导体管芯208。凸块210形成在TSV衬底206上，类似于图3k。密封剂212沉积在半导体管芯208和凸块210上。半导体封装204通过凸块170电连接到半导体封装186。
虽然已经详细说明本发明的一个或多个实施例，但是本领域技术人员将理解的是，在不脱离由下列权利要求所阐述的本发明的范围的情况下可以对那些实施例进行变型和修改。

Claims (14)

1.一种制作半导体封装的方法，包括：
提供晶片级衬底；
形成通过所述晶片级衬底的多个通路；
在所述通路中沉积导电材料以形成通过所述晶片级衬底的第一导电通路；
提供第一载体；
将具有第一导电通路的所述晶片级衬底安装到第一载体；
将第一半导体管芯安装到所述晶片级衬底的第一表面；
在第一半导体管芯和第一载体上沉积第一密封剂；
除去第一载体；
提供第二载体；
利用第一密封剂将第一半导体管芯和晶片级衬底安装到第二载体；
将第二半导体管芯安装到晶片级衬底的与所述晶片级衬底的第一表面相对的第二表面；
在第二半导体管芯上沉积第二密封剂；以及
除去第二载体。
2.根据权利要求1的方法，还包括在所述晶片级衬底的第二表面上形成多个凸块。
3.根据权利要求1的方法，还包括形成通过所述第一密封剂并电连接到所述第一导电通路的多个第二导电通路。
4.根据权利要求1的方法，还包括在沉积第一密封剂之前在所述第一导电通路上形成多个凸块。
5.根据权利要求1的方法，还包括堆叠多个半导体封装，所述多个半导体封装每个均包括安装到所述晶片级衬底的第一表面的第一半导体管芯。
6.一种制作半导体封装的方法，包括：
提供衬底；
形成通过所述衬底的第一导电通路；
将具有第一导电通路的所述衬底安装到第一载体；
将第一半导体管芯安装到所述衬底的第一表面；
在第一半导体管芯和第一载体上沉积第一密封剂；
除去第一载体；
利用第一密封剂将第一半导体管芯和衬底安装到第二载体；
将第二半导体管芯安装到与衬底的第一表面相对的衬底的第二表面；
在第二半导体管芯上沉积第二密封剂；以及
除去第二载体。
7.根据权利要求6的方法，还包括在所述衬底的第二表面上形成凸块。
8.根据权利要求6的方法，还包括形成通过所述第一密封剂并电连接到所述第一导电通路的第二导电通路。
9.根据权利要求6的方法，还包括在沉积第一密封剂之前在所述第一导电通路上形成凸块。
10.根据权利要求6的方法，还包括堆叠多个半导体封装，所述多个半导体封装每个均包括安装到所述衬底的第一和第二表面的第一和第二半导体管芯。
11.一种半导体封装，包括：
衬底，所述衬底具有通过所述衬底的第一导电通路；
安装到所述衬底的第一表面的第一半导体管芯；
在所述衬底的所述第一表面上形成的第一凸块；
沉积在所述第一半导体管芯、所述第一凸块和所述衬底的侧面上的第一密封剂；
安装到与所述衬底的第一表面相对的所述衬底的第二表面的第二半导体管芯；
在所述第二半导体管芯的外部形成在所述衬底的第二表面上的第二凸块；
沉积到第二半导体管芯上的第二密封剂；以及
多个堆叠的半导体封装，所述多个堆叠的半导体封装的每个均包括安装到所述衬底的第一和第二表面的第一和第二半导体管芯，其中所述堆叠的半导体封装通过所述第一凸块被电连接。
12.根据权利要求11的半导体封装，还包括形成在所述第二凸块上和所述衬底的第二表面上的第二密封剂。
13.根据权利要求11的半导体封装，还包括安装到第一半导体管芯上的导电层。
14.根据权利要求11的半导体封装，还包括被形成为通过所述第一密封剂并电连接到所述第一导电通路的第二导电通路。
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