TWI733690B - 半導體加工方法 - Google Patents
半導體加工方法 Download PDFInfo
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- TWI733690B TWI733690B TW105125720A TW105125720A TWI733690B TW I733690 B TWI733690 B TW I733690B TW 105125720 A TW105125720 A TW 105125720A TW 105125720 A TW105125720 A TW 105125720A TW I733690 B TWI733690 B TW I733690B
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Abstract
提供了一種半導體加工方法。該方法包括提供第一載體。在第一載體上提供第一黏合劑,在第一黏合劑上放置多個半導體晶片。提供第二載體。所述第二載體具有多個晶片接收區域。將第一載體和第二載體結合在一起以將半導體晶片附接至第二載體上各自的晶片接收區域。然後從所述半導體晶片分離所述第一載體。
Description
本發明涉及半導體封裝,更具體地,涉及半導體加工方法。
可製造性是半導體封裝中重要的考慮因素,因為其直接影響封裝成本。因此,為了降低包裝成本,期望具有一種便於半導體封裝處理的基質。
因而,在第一方面,本發明提供了一種半導體加工方法。所述半導體加工方法包括:提供第一載體;在所述第一載體上第一黏合劑;在所述第一黏合劑上放置多個半導體晶片;提供第二載體,其中所述第二載體具有多個晶片接收區域;將所述第一載體和第二載體結合在一起以將所述半導體晶片附接至所述第二載體上各自的所述晶片接收區域;以及從所述半導體晶片分離所述第一載體。
結合附圖,本發明的其他方面和優點將從通過示例說明本發明原理的以下的詳細描述中顯而易見。
10:第一載體、傳遞載體
12:第一全域標記
14:第一單元標記
16:晶片放置位置
18:第一黏合劑
20:半導體晶片
22:活性表面
24:虛表面
26:晶片標記
28:第二或支撐載體、第二載體、支撐載體
30:第二全域標記、初級全域標記
32:晶片接收區域、晶片接收區域或單元區域
34:晶片墊片
36:第二單元標記
38:層
40:第二黏合劑、黏結層
42:次級全域標記
44:介電層
46:第一開口、標記開口
48:端子墊片
50:第二開口
52:通孔
54:第一導電跡線
56:元件墊片
58:結構特徵
60:無源元件
62:黏結層
64:間隔件
66、68、78、80:半導體封裝
70:第二介電層
72:第二通孔
74:第二導電跡線
76:第三介電層
當結合附圖閱讀時,將更好地理解本發明優選實施例的以下詳細描述。本發明通過示例進行說明,並不受附圖限制,在附圖中,相同
的附圖標記指示相同的元件。將會理解,附圖並非按比例繪出,並且為了易於理解本發明而進行了簡化。
圖1是根據本發明實施例的第一載體的示意性俯視圖;圖2是其上設置有第一黏合劑的圖1的第一載體的示意性側視圖;圖3是根據本發明另一實施例的其上設置有第一黏合劑的圖1的第一載體的示意性側視圖;圖4是示出圖2和圖3的第一黏合劑上的多個半導體晶片的放置的示意圖;圖5是根據本發明實施例的第二載體的示意性俯視圖;圖6是根據本發明另一實施例的第二載體的示意性俯視圖;圖7是根據本發明又一實施例的第二載體的示意性俯視圖;圖8是根據本發明再一實施例的第二載體的示意性俯視圖;圖9是示出根據本發明實施例的設置在第一載體上的半導體晶片的每個上的第二黏合劑的示意性側視圖;圖10是根據本發明另一實施例的設置在第二載體上的晶片接收區域的每個上的第二黏合劑的示意性側視圖;圖11是示出根據本發明實施例的將第一載體的多個第一全域標記與第二載體的多個第二全域標記相應對齊的示意圖;圖12是示出第二載體的尺寸被確定為容納多於一個第一載體的實施例的示意圖;圖13是示出根據本發明實施例的第一載體和第二載體結合在一起以將半導體晶片附接至第二載體上的各個晶片接收區域的示意圖;圖14是示出根據本發明實施例的施加剪切力以從半導體晶片分離第一載體的示意圖;圖15是示出根據本發明實施例的從半導體晶片分離第一載體的示意圖;圖16是示出將半導體晶片附加至圖5所示的第二載體的示意圖;
圖17是示出根據本發明實施例的形成於圖16所示的第二載體上的介電層的示意性側視圖;圖18是示出根據本發明另一實施例的形成於圖16所示的第二載體上的介電層的示意性俯視圖;圖19是示出根據本發明另一實施例的半導體加工步驟的示意圖;圖20是示出根據本發明又一實施例的半導體加工步驟的示意圖;圖21和22是根據本發明其他實施例的第二載體的示意性俯視圖;和圖23至26是根據本發明實施例形成的半導體封裝的放大剖面圖。
以下結合附圖給出的詳細描述意為本發明目前優選實施例的描述,並不意在表示可以實踐本發明的唯一形式。應理解,可以通過意在包括在本發明的範圍內的不同實施例來實現相同或等同的功能。在所有附圖中,相同的附圖標記自始至終用於指示相同的元件。
圖1至22示出根據本發明實施例的半導體加工方法。在本說明書中,術語“全域標記”用於描述載體或初級的位置指示,術語“單元標記”用於描述單元級的位置指示,術語“晶片標記”用於描述半導體晶片上的位置指示,術語“次級全域標記”用於描述多載體或次級的位置指示。
現在參照圖1,提供第一或傳遞載體10。在本實施例中,第一載體10具有多個第一全域標記12。在所示實施例中,第一載體10也具有多個第一單元標記14,第一單元標記14定義多個晶片放置位置16。
第一載體10可以提供為條或板的形式,並且可以由金屬構成,例如,鋼或銅,金屬合金,玻璃或聚合物,例如FR4。在第一載體10由金屬材料製成的實施例中,第一全域標記12與第一單元標記14可以通過化學蝕刻、鐳射蝕刻或使用傳統的光刻技術或圖案形成工藝的電鍍形成於第一載體10上或形成於第一載體10中。在蝕刻的情況下,第一
全域標記12和第一單元標記14可以被刻入第一載體10的表面。在電鍍的情況下,金屬第一載體10可以被用作導電平面,設置的第一全域標記12和第一單元標記14形成在第一載體10的表面上並突出於第一載體10的表面。在第一載體10由玻璃或聚合物製成的實施例中,第一全域標記12與第一單元標記14可以通過鐳射或油墨雕刻被刻入第一載體10。有利地,當第一載體10由玻璃製成時,因為玻璃具有低的熱膨脹係數,因此當第一載體10在隨後的工藝步驟中被加熱時,形成於第一載體10中的第一全域標記12與第一單元標記14不會明顯移動,從而可以提高加工精度。此外,由於第一全域標記12與第一單元標記14直接在第一載體10上生成,因此不涉及可能引入偏移或其它誤差的額外工藝步驟。這也有助於提高加工精度。
在所示實施例中,每個第一全域標記12具有不同的形狀。有利地,在半導體加工方法中,這有助於定位第一載體10和相對於第一載體10定位其它元件或部件。
儘管在所示實施例中示出在第一載體10的表面上設置兩個(2)全域標記12並且示出提供兩個(2)單元標記14以定義每個晶片放置位置16,但對於本領域普通技術人員應當理解的是,本發明並不受限於提供的第一全域標記12或第一單元標記14的數量。在可選實施例中,第一載體10可以具有更多數量的第一全域標記12和/或第一單元標記14。
在本實施例中,可以基於第一全域標記12的位置確定第一單元標記14的位置。每個第一全域標記12可以設置在相對於另一個第一全域標記12固定的或選定的位置,每個第一單元標記14可以設置在相對於第一全域標記12和同一晶片放置位置16中的其他第一單元標記14固定的或選定的位置。第一全域標記12可以用於計算和確定第一單元標記14的位置,第一單元標記14可以用於計算和確定每個晶片放置位置16的中心,每個晶片放置位置16對應於將要安裝的半導體晶片的單元位置。在這樣的實施例中,晶片放置位置16的中心處於相對於第一全域
標記12固定的或選定的位置。
現在參照圖2,如圖所示,在第一或傳遞載體10上設置第一黏合劑18。第一黏合劑18可以通過層壓、或通過絲網印刷或通過塗覆設置在第一或傳遞載體10上。
在本實施例中,第一黏合劑18包括可釋放黏合材料,可釋放黏合材料具有釋放機制,例如,在暴露於熱、紫外線輻射、紅外線輻射或化學溶液時導致可釋放黏性材料失去實質的黏合強度。在一個實施例中,第一黏合劑18可以是黏合強度在暴露於熱時顯著減少的熱釋放薄膜。
在所示實施例中,第一全域標記12與第一單元標記14被刻入第一載體10,因此不能延伸超過第一載體10的表面。在這樣的實施例中,第一黏合劑18可以是透明的或半透明的,使得第一全域標記12與第一單元標記14是通過第一黏合劑18可見的。
現在參照圖3,示出了其上設置有第一黏合劑18的第一載體10的可選實施例。在所示實施例中,第一全域標記12與第一單元標記14形成於第一載體10的表面上並從第一載體10的表面突出。在這樣的實施例中,第一黏合劑18封裝第一全域標記12與第一單元標記14,使得只有第一全域標記12和第一單元標記14的上表面被暴露。在該實施例中,第一黏合劑18可以是不透明的。
現在參照圖4,多個半導體晶片20被放置在如圖2或3所示的第一黏合劑18上。
半導體晶片20的每一個可以是處理器,例如數位訊號處理器(DSP),專用功能電路,例如記憶體位址發生器,或執行任何其它類型的功能。此外,半導體晶片20不限於特別的技術例如CMOS,或不限於從任何特定晶片技術得到。此外,本領域技術人員可以理解的是,本發明可以適應各種晶片尺寸。半導體晶片20的每一個具有活性表面(active surface)22和與活性表面相對的虛表面(dummy surface)24。
用於電連接到晶片電路的端子墊片(未示出)設置在半導體晶片20的活性表面22上。
在本實施例中,多個晶片標記26設置在半導體晶片20的每一個上,晶片標記26設置在半導體晶片20的活性表面22上。晶片標記26的每一個可以設置在相對於其它晶片標記26和/或端子墊片固定的或指定的位置,並且可以用於計算和確定半導體晶片20的每一個的中心。在一個實施例中,半導體晶片20上的區別性特徵可用作或充當晶片標記26。
在所示的本實施例中,在將各自的半導體晶片20放置在第一黏合劑18之前,將半導體晶片20的每一個上的晶片標記26與相應的第一單元標記14對齊。以這種方式,當各自的半導體晶片20被放置在第一或傳遞載體10上時,半導體晶片20的每一個的中心與每個相應的單元或晶片放置位置16的中心對齊,半導體晶片20的每一個與相應的單元或晶片放置位置16對齊。因此,半導體晶片20的每一個的中心和位置也在相對於第一或全域標記固定的或指定的位置。這種對齊可以由視覺系統執行,所述視覺系統包括攝像單元和計算並調整半導體晶片20的位置的控制器單元。
當被放置在第一或傳遞載體10上時,半導體晶片20的活性表面22面對第一或傳遞載體10並黏附到第一黏合劑18。第一黏合劑18有助於在隨後的工藝步驟期間防止半導體晶片20的任何不必要的位移,也有助於確保半導體晶片20的每一個總是處於相對於第一全域標記12固定的或指定的位置。
在第一黏合劑18是糊劑形式、半固體形式或半熔態(B-stage)形式的實施中,第一黏合劑18可以進一步通過熱或輻射被固化以增加其材料的彈性模量和至半導體晶片20的黏附。
現在參照圖5,提供第二或支撐載體28,第二載體28具有多個晶片接收區域32。在本實施例中,第二載體28還具有多個第二全域標記30。
在本實施例中,晶片接收區域32包括設置在第二載體28上的多個晶片墊片34,晶片墊片34的每一個對應於半導體晶片20中的一個將要被安裝或附接至的晶片接收區域或單元區域32。
第二載體28可以被提供為條或板的形式。在一個實施例中,第二載體28由導電和化學可蝕刻材料,例如,銅或鋼,或其的層形成。在另一實施例中,第二載體28可以是聚合樹脂絕緣片,層壓有導電和化學可蝕刻材料例如銅的層。
在所示實施例中,第二全域標記30的每一個具有與對應的第一全域標記12相同的形狀。有利地,在隨後的加工步驟中有助於第二載體28相對於第一載體10的定位。
儘管在所示實施例中示出兩個(2)全域標記30設置在第二載體28的表面上,但是對於本領域普通技術人員來說應當理解的是,本發明並不受限於提供的第二全域標記30的數量。例如,在可選的實施例中,第二載體28可以具有更多數量的第二全域標記30。
在本實施例中,第二全域標記30的每一個設置在相對於其它第二全域標記30固定的或選定的位置,晶片墊片34的每一個設置在相對於第二全域標記30和其它晶片墊片34固定的或選定的位置。第二全域標記30可以用於計算和確定晶片接收區域32的位置,因此也確定晶片墊片34的位置。在優選實施例中,晶片墊片34的每一個的中心對應於相應的晶片接收區域32的中心。
晶片墊片34可使用標準光刻技術和圖案形成工藝通過電鍍而形成,由此形成的晶片墊片34從第二載體28的表面突出。在優選實施例中,第二全域標記30可以通過電鍍與晶片墊片34一起形成,並且也從第二載體28的表面突出。在可選的實施例中,可以在形成晶片墊片34之前首先通過化學蝕刻或使用鐳射或油墨的雕刻形成第二全域標記30。
現在參照圖6,示出第二載體28的可選實施例。在所示實施例中,
多個第二單元標記36形成在鄰近各自的晶片墊片34的第二載體28的表面上。
在本實施例中,第二單元標記36設置在晶片接收區域32中,成對的第二單元標記36定義相應的晶片接收區域32。儘管在所示的實施例中示出設置兩個(2)單元標記36以定義晶片接收區域32的每一個,但是對於本領域普通技術人員來說應當理解的是,本發明並不受限於提供的第二單元標記36的數量。例如,在可選的實施例中,可以提供較多數量的第二單元標記36以定義晶片接收區域32的每一個。
在本實施例中,可以基於第二全域標記30的位置確定第二單元標記36的位置。第二單元標記36的每一個可以設置在相對於第二全域標記30、也相對於晶片墊片34以及同一晶片接收區域32中的其它第二單元標記36固定的或選定的位置。第二全域標記30可以用來計算和確定位置第二單元標記36的位置,第二單元標記36可以用於計算和確定晶片接收區域32和晶片墊片34的中心,使得晶片接收區域32和晶片墊片34的中心也處於相對於第二全域標記30固定的或選定的位置。
現在參照圖7,示出了又一實施例的第二載體28。在該實施例中,第二單元標記36形成在晶片墊片34的本身上。
現在參照圖8,示出了再一實施例的第二載體28。在該實施例中,沒有形成單獨的晶片墊片34,第二載體28包括通過包覆或電鍍設置在第二載體28的表面上的金屬例如銅或鎳的層38。在這樣的實施例中,第二全域標記30可以通過電鍍形成於第二載體28上,並因此從表面突出。第二全域標記30也可以通過化學蝕刻或使用鐳射或油墨的雕刻形成於第二載體28上。
現在參照圖9,如圖所示,第二黏合劑40設置在第一載體10上的半導體晶片20的每一個上。更具體地,在所示實施例中,黏結層(bonding layer)40設置在第一載體10上的半導體晶片20的虛表面24上。這可以通過網版絲印(stencil screen printing)、或針頭或噴射點膠設置。第二黏
合劑40可以是環氧基晶片附接黏合劑、丙烯酸基晶片附接黏合劑或熱介面材料,例如,銀漿。在可選的實施例中,第二黏合劑40可以在單片化之前預先形成於半導體晶片20上,例如,以管芯附接薄膜的形式。有利地,當在第一載體10上的半導體晶片20上設置第二黏合劑40時,第二載體28可以預先加熱,更快地上升到選定的溫度。
現在參照圖10,示出可選的實施例,其中相反地,黏合或黏結層40設置於第二載體28的晶片接收區域32的每一個上。
現在參照圖11,如本發明實施例所示,第一載體10的第一全域標記12與第二載體28中相應的第二全域標記30對齊。以這種方式,傳遞載體10與支撐載體28對齊,傳遞載體10上的半導體晶片20與支撐載體28上相應的晶片墊片大體對齊。當傳遞載體10和支撐載體28以這種方式定位時,半導體晶片20和相應的晶片墊片34面對彼此,半導體晶片20的每一個的中心與相應的晶片墊片34的每一個的中心大體對齊。
現在參照圖12,示出了第二載體28的尺寸被確定為容納多於一個(1)第一載體10的實施例。本實施例不同於前述實施例,使用多個第一或傳遞載體10在第二支撐載體28上放置半導體晶片20。在這個實施例中,每個傳遞載體10的尺寸小於支撐載體28的尺寸,每個傳遞載體10將一組半導體晶片20放置在支撐載體28上。有利地,這增加在支撐載體28上放置晶片的精度。進一步有利地,將第二載體28的尺寸確定為容納多於一個(1)第一載體10的使用也提高半導體加工的效率,幫助減少加工時間。在所示實施例中,除了用於將支撐載體28與各個傳遞載體10的每個對齊的初級全域標記30之外,第二載體28具有多個次級全域標記,多個次級全域標記42用於隨後的加工步驟中的整個第二或支撐載體28及放置於其上的全部半導體晶片20的加工。
現在參照圖13,如圖所示,第一載體10和第二載體28被結合在一起以將半導體晶片20附接至第二載體28上各自的晶片接收區域32。這可以是將傳遞載體10放置在支撐載體28上使得半導體晶片20的虛表面
24接觸黏結層40且半導體晶片20的中心與相應的晶片墊片34的中心大體對齊。通過黏結層40將第一載體10和第二載體28的元件機械地鎖定在適當的位置。
當傳遞載體10被放置在支撐載體28上使得半導體晶片20的虛表面24接觸黏結層40時,第二黏合劑40的一部分被部分地替換為傳遞載體10的塊。但是,因為半導體晶片20的活性表面22黏附至第一黏合劑18,通過第一黏合劑18避免被替換的第二黏合劑40流進或進入半導體晶片20的活性表面22。當加工厚度在25微米(μm)和大約50μm之間的薄晶片裸片時,這是特別有利的。
在本實施例中,在將第一載體10和第二載體28結合在一起之後,第二黏合劑40被加熱至第二黏合劑40的固化溫度。這固化了黏結層40,並增大了黏結層40的模量和黏合強度以將半導體晶片20鎖定在相對於第一全域標記12和第二全域標記30固定的或選定的位置。在一個實施例中,第一載體10和第二載體28的元件被加熱到升高的第一溫度,第一溫度約為150攝氏度(℃)且對應於採用的黏結層40的固化溫度。
在從半導體晶片20分離第一載體10之前,可以在加熱第一黏合劑18至可釋放黏合材料的釋放溫度之前冷卻第一載體10和第二載體28的元件。該加熱操作導致第一黏合劑18大體失去黏合強度,這有助於隨後從半導體晶片20分離第一載體10。可釋放黏合材料的釋放溫度高於第二黏合劑40的固化溫度。在一個實施例中,第一載體10和第二載體28的元件被加熱到升高的第二溫度,第二溫度約為200℃且對應於使用的可釋放黏合材料的釋放溫度。
換句話說,在黏結層40固化並增加至半導體晶片20的黏合強度之後,第一黏合劑18喪失至半導體晶片20的黏合強度。
兩步加熱過程可以在一個(1)機器中執行或通過使用兩個(2)機器執行。在後者的實施例中,第一載體10和第二載體28的元件可以
在被冷卻之前在第一機器中被加熱,然後輸送到第二機器以進行第二加熱操作。
在固化第二黏合劑40之前,黏結層40可以是糊狀或流體狀態。在這樣的實施例中,傳遞載體10上的第一黏合劑18有助於防止當通過第一黏合劑18將半導體晶片20放置在適當的位置時,半導體晶片20由於表面張力或黏結層40的浮力作用發生從中心位置的非自願移位。因此,半導體晶片20的相對位置保持基本相同,即使在半導體晶片20被傳遞到支撐載體28上之後。
當傳遞載體10和支撐載體28由不同的材料製成時,存在熱膨脹係數(CTE)的差異。隨著溫度的升高,傳遞載體10和支撐載體28以不同速率膨脹。當第一黏合劑18比未固化的黏結層40具有明顯更強的黏合強度時,在膨脹期間半導體晶片20趨向於跟隨傳遞載體10,因此優選地,傳遞載體10的熱膨脹係數(CTE)小於支撐載體28的熱膨脹係數。相應地,本實施例中的第一載體10可以具有與第二載體28相比相同或較小的熱膨脹係數(CTE)。例如,在一個示例性實施例中,傳遞載體10可以由CTE約為每攝氏度百萬分之三(3ppm/℃)的玻璃製成,支撐載體28可以由CTE約為11ppm/℃的鋼製成。在優選實施例中,第一載體10和第二載體28由相同的材料製成,使得加熱時膨脹率是相同的。
現在參照圖14和15,示出了從半導體晶片20分離第一載體10。如圖14和15所示,從半導體晶片20分離第一載體10的步驟包括:在從半導體晶片20拉開第一載體10之前,施加剪切力至第一載體10,更具體地,分離行為包括剪切(傳遞載體10和支撐載體28之間的角位移和橫向位移),然後拉(傳遞載體10和支撐載體28之間的垂直位移),以最小化半導體晶片20的損害和不必要的移動。半導體晶片20通過黏結層40牢固地保持在晶片墊片34上的合適位置。
在本實施例中,傳遞載體10從支撐載體28分離,而第一載體10和
第二載體28的元件保持在第二升高溫度下。
現在參照圖16,當傳遞載體10從支撐載體28分離時,第一黏合劑18從半導體晶片20的活性表面22分離。因此,半導體晶片20的活性表面22被暴露並背對支撐載體28。因此,半導體晶片20的端子墊片和晶片標記26也被暴露。
然後可以在半導體晶片20的活性表面22上執行清潔操作,以從第一黏合劑18除去殘餘物。這可以是等離子體或化學清洗。
在一個實施例中,掃描操作可以在這個時候執行以獲得半導體晶片20的每一個上的端子墊片的位置資料,用於隨後的加工步驟。這可以通過使用光學視覺系統實現。更具體地,光學視覺系統的檢測器或攝像機可以識別待被捕獲的的多個特徵(例如,突出的形狀、顏色對比度或兩者的組合),對應的特徵的位置資料可以被記錄從而在隨後的加工步驟中使用。
在上述方式中,半導體晶片20可以被同時從傳遞載體10傳遞到支撐載體28,半導體晶片20的每一個被準確地放置並且與對應的晶片墊片34大體對齊,半導體晶片20的每一個的中心與相應的晶片墊片34的中心大體對齊。半導體晶片20因此被定位在相對於支撐載體28上的第二全域標記30固定的或選定的位置,可以通過第二全域標記30計算並確定半導體晶片20的每一個的位置。相應地,由於可以通過第二全域標記30計算並確定半導體晶片20的每一個的位置,並且每個半導體晶片20上的端子墊片的位置處於相對於相應的晶片中心固定的或選定的位置,因此也可以從第二全域標記30計算和確定每個半導體晶片20上的端子墊片的位置。
現在參照圖17,如圖所示,在第二載體28上形成介電層44,介電層44封裝半導體晶片20。在所示實施例中,介電層44僅封裝半導體晶片20和晶片墊片34,而不覆蓋第二全域標記30。
介電層44可以通過模塑、層壓或印刷工藝形成在第二載體28上。
在一個實施例中,使用膜片或糊劑形式的環氧化合物形成介電層44。介電層44的厚度可以通過研磨或拋光變薄,而不暴露半導體晶片20。
在一個實施例中,可以在此時執行掃描操作以獲得半導體晶片20的每一個上的端子墊片的位置資料,用於隨後的加工步驟。這可以是使得封裝半導體晶片20的介電層44暴露至電磁輻射(例如,X-射線、紅外射線或紫外射線),允許視覺系統的檢測器或攝像機捕獲和記錄半導體晶片20的每一個上的端子墊片的位置資料,用於隨後的加工步驟。
現在參照圖18,示出了在第二載體28上形成介電層44的另一實施例。在該實施例中,第二全域標記30最初被介電層44覆蓋和封裝。因此,多個第一開口46形成於介電層44中,以暴露各個第二全域標記30。
第二載體28上的第二全域標記30可以通過例如鐳射鑽孔而暴露。標記開口46的尺寸可以大於第二全域標記30的尺寸以確保第二全域標記30在標記開口46中完全暴露。
在本實施例中,首先基於第二全域標記30的位置確定半導體晶片20的每一個上的多個端子墊片48的位置,然後在介電層44中形成多個第二開口50以暴露各自的端子墊片48。有利地,所述從傳遞載體10傳遞半導體晶片20至支撐載體28的半導體加工方法允許從支撐載體28上的第二全域標記30準確計算並確定端子墊片48的位置。形成第二開口50的精度是關鍵的,因為第二開口50和相應的端子墊片48之間的任何不對齊可以損壞半導體晶片20的靈敏電路。因此,基於第二全域標記30的位置計算並確定半導體晶片20上的端子墊片48的精確位置的能力提供顯著的優點。
第二開口50可以通過例如鐳射鑽孔或點火形成。鐳射點火可以使用鐳射直接成像(LDI)系統與視覺和控制器系統,以允許生成精確的圖案。更具體地,視覺能力有助於定位第二全域標記30,控制器系統有助於計算半導體晶片20和相應的端子墊片48的相對位置。鐳射系
統然後移動到端子墊片48上方的精確位置以生成第二開口50。在一個實施例中,從較早的掃描操作獲得的端子墊片48的位置資料可以用於定位端子墊片48以形成第二開口50。
在所示實施例中,在介電層44的第二開口50中形成多個通孔52,在介電層44的表面上形成多個導電跡線54。通孔52將半導體晶片20的活性表面22上的端子墊片48連接到導電跡線54。
通孔52和導電跡線54可以通過半加成電鍍工藝形成。更具體地,可以通過無電沉積工藝在介電層44的表面和通孔52的側壁上沉積金屬種子層,隨後在介電層44上設置光致抗蝕劑層。然後可以利用IDL或掩模曝光對光致抗蝕劑層形成圖案。然後,可以在第二開口50中形成通孔52,利用導電材料例如銅在種子層上形成導電跡線54。最後,去除種子層的任何暴露部分。
在圖案化光致抗蝕劑層的步驟中,第二全域標記30再次用作參考特徵以計算和確定圖案相對於半導體晶片20的相對位置。在使用LDI的實施例中,視覺和控制器系統定位第二全域標記30並通過參考第二全域標記30計算半導體晶片20的位置。在使用掩膜曝光的實施例中,掩膜上的對應標記與支撐載體28上的第二全域標記30對齊。掩膜上的圖案形成在光致抗蝕劑層上,並對應於半導體晶片20的適當位置。
支撐載體28的全域標記30還用在隨後的形成半導體封裝的步驟中,以準確地計算和確定半導體晶片20和其對應的端子墊片48的位置。由於使用全域標記30的一般方法與上述方法類似,無需進一步的描述以完整理解本發明。
在密封步驟之後,可以通過化學蝕刻或機械分離去除第二載體28,可以通過鐳射或機械切削或切割穿過介電層44分離半導體晶片20,以獲得多個半導體封裝單元。
現在參照圖19,示出了第一載體10和第二載體28的裝配的另一實施例。不同於前述實施例,本實施例中,多個元件墊片56設置在第二
載體28上。元件墊片56中的每一個可以設置在相對於第二全域標記30、也相對於晶片墊片34和其它元件墊片56固定的或指定的位置。第二全域標記30可以用來計算和確定元件墊片56的位置。元件墊片56可以與晶片墊片34一起形成在第二載體28上。
多個結構特徵58、多個無源元件60或其組合可以形成於第二載體28上的各自的元件墊片56上或附接到第二載體28上的各自的元件墊片56。在可選的實施例中,元件墊片56可省略,結構特徵58和/或無源元件60可以直接形成於第二載體28或晶片墊片34上或附接到第二載體28或晶片墊片34。結構特徵58可以是用於垂直連接的互連或柱列,用於射頻(RF)遮罩的壁結構或用於增強生成的半導體封裝的結構完整性的圖案化結構。結構特徵58可以通過電鍍、刻蝕第二載體或附接外部部件至第二載體28而預先形成。可以結合電鍍或蝕刻使用光刻以在第二載體28上形成結構特徵58的各種圖案或構造。可選地,外部部件可通過常規的表面安裝工藝被附接到第二載體28。
無源元件60可以是電容器、電阻器、二極體、電感器或集成無源設備(IPD)。在將無源元件60放置到元件墊片56上之前,可以將例如環氧樹脂或焊料的黏結層62分配到元件墊片56上。可選地,無源元件60可以具有預先形成在無源元件60的多個電極上的黏結層,用於附接至元件墊片56。在用無源元件60填充支撐載體28之後可以使得支撐載體28經歷熱處理,以確保完全的黏結。
為了避免妨礙第一載體10和第二載體28的裝配,結構特徵58和無源元件60的上表面低於半導體晶片20的活性表面22。如果晶片墊片34和元件墊片56具有相同的厚度,半導體晶片20的厚度必須基本上等於或大於結構特徵58和無源元件60的厚度。可以通過研磨或拋光半導體晶片20指定或控制半導體晶片20的厚度。
因此,在所示實施例中,結構特徵58和無源元件60的高度小於半導體晶片20的厚度。因此,在將半導體晶片20從傳遞載體10傳遞到支
撐載體28的過程中,結構特徵58和無源元件60不會接觸第一黏合劑18,也不影響半導體晶片20與晶片墊片34的接觸。
現在參照圖20,示出了第一載體10和第二載體28的裝配的另一實施例。在該實施例中,半導體晶片20的厚度小於無源元件60的厚度。
因此,在半導體晶片20的每一個和對應的晶片墊片34之間設置間隔件64,以增加半導體晶片20的活性表面22的高度。在可選的實施例中,可以通過將晶片墊片34電鍍至更厚的厚度而提高半導體晶片20的活性表面22的高度。
第二載體28上的無源元件60和結構特徵58的示例性佈局示於圖21和22,如下所述。
現在參照圖21,在所示實施例中,結構特徵58圍繞晶片墊片34設置在第二載體28上。
現在參照圖22,在本實施例中,無源元件60被設置在第二載體28上的各自的元件墊片56上或附接至第二載體28上的元件墊片56。無源元件60可以採用常規的表面安裝工藝通過元件放置被設置在元件墊片56上或附接至元件墊片56。
半導體加工方法形成的示例性半導體封裝示於圖23至26,如下所述。
現在參照圖23,示出了半導體封裝66。半導體封裝66包括:通過第二黏合劑40附接到晶片墊片34的半導體晶片20。半導體晶片20由第一介電層44封裝。穿過第一介電層44形成的多個第一通孔52將半導體晶片20連接到多個第一導電跡線54。
現在參照圖24,示出了半導體封裝68。半導體封裝68不同於前述實施例,第一導電跡線54由第二介電層70封裝,穿過第二介電層70形成的多個第二通孔72將第一導電跡線54連接到多個第二導電跡線74。第二導電跡線74由第三介電層76封裝。以這種方式,可以適用常規的層構建工藝順序地添加多層的導電跡線,以提供更高的佈線密度和複
雜性。第二介電層70和第三介電層76可以是,例如,環氧模塑膠或膜、織造玻璃纖維層或焊料掩模。
現在參照圖25,示出了半導體封裝78。與前述實施例不同,半導體封裝78包括多個結構特徵58。結構特徵58也被第一介電層44封裝,並第一通孔52電連接至第一導電跡線54。第一導電跡線54由第二介電層70封裝。在本實施例中,結構特徵58是提供從半導體封裝78的一個表面到半導體封裝78的相對表面的電連接路徑的互連柱。有利地,這允許另一半導體封裝堆疊在半導體封裝78上,以形成堆疊半導體封裝。
現在參照圖26,示出了半導體封裝80。半導體封裝80不同於前述實施例,半導體封裝80包括設置在多個元件墊片56個或附接到多個元件墊片56的多個無源元件60。無源元件60也被第一介電層44封裝,並通過第一通孔5電連接至第一導電跡線54,通過第一導電跡線54電連接至半導體晶片20。第一導電跡線54被第二介電層70封裝。從前述討論顯然可知,本發明提供了一種半導體加工方法,該方法允許同時加工多個半導體晶片。有利地,這增加加工效率,並降低加工時間和成本。另外,通過在半導體加工過程中提供全域標記作為位置指示,也改進了加工精度和產品的可靠性。
呈現本發明的優選實施例的描述是為了說明和描述,而並不意在排他或將本發明限制為所公開的形式。本領域技術人員將會理解,可以在不偏離廣義的發明概念的情況下對上述實施例做出改變。因而可以理解,本發明不限於所公開的特定實施例,而是覆蓋由所附申請專利範圍限定的本發明的範圍內的修改。
此外,除非上下文明確需要,在整個說明書和申請專利範圍中,詞“包括”、“包含”等應被理解為與排他或窮舉含義相對的包含;也就是說,其含義為“包括但不限於”。
10:第一載體、傳遞載體
12:第一全域標記
18:第一黏合劑
20:半導體晶片
28:第二或支撐載體、第二載體、支撐載體
30:第二全域標記、初級全域標記
32:晶片接收區域、晶片接收區域或單元區域
34:晶片墊片
40:第二黏合劑、黏結層
Claims (21)
- 一種半導體加工方法,包括:提供第一載體;在所述第一載體上提供第一黏合劑;在所述第一黏合劑上放置多個半導體晶片;提供第二載體,其中所述第二載體具有多個晶片接收區域,其中所述晶片接收區域包括設置在所述第二載體上的多個晶片墊片;在與各個所述晶片墊片相鄰的所述第二載體的表面和所述晶片墊片自身中的一個上形成多個第二單元標記;將所述第一載體和第二載體結合在一起以將所述半導體晶片附接至所述第二載體上各自的所述晶片接收區域;以及從所述半導體晶片分離所述第一載體,其中所述第一載體具有多個第一全域標記,所述第二載體具有多個第二全域標記,其中在將所述第一載體和第二載體結合在一起之前將所述第一全域標記與相應的第二全域標記對齊。
- 如請求項1所述的方法,其中所述第一全域標記的每一個具有不同的形狀,所述第二全域標記的每一個具有與相應的所述第一全域標記相同的形狀。
- 如請求項1所述的方法,進一步包括:為所述第一載體提供多個第一單元標記,所述第一單元標記定義多個晶片放置位置。
- 如請求項3所述的方法,其中為所述第一載體提供多個第一單元標記的步驟包括:基於所述第一全域標記的位置確定所述第一單元標記的位置。
- 如請求項3所述的方法,進一步包括:在所述第一黏合劑上放置各個半導體晶片之前,將所述半導體晶片的每一個上 的多個晶片標記與相應的所述第一單元標記對齊。
- 如請求項5所述的方法,其中所述晶片標記設置在所述半導體晶片的活性表面上。
- 如請求項1所述的方法,其中形成所述第二單元標記的步驟包括:基於所述第二全域標記的位置確定所述第二單元標記的位置。
- 如請求項1所述的方法,進一步包括:在所述第二載體上提供多個元件墊片。
- 如請求項8所述的方法,進一步包括:將多個結構特徵、多個無源元件或其組合附接至所述第二載體上的各個所述元件墊片。
- 如請求項1所述的方法,進一步包括:在所述半導體晶片的每一個和所述晶片接收區域的每一個中的一個上設置第二黏合劑。
- 如請求項10所述的方法,進一步包括:在將所述第一載體和所述第二載體結合在一起之後,加熱所述第二黏合劑至所述第二黏合劑的固化溫度。
- 如請求項1所述的方法,其中所述第一黏合劑包括可釋放黏合材料。
- 如請求項12所述的方法,進一步包括:在從所述半導體晶片分離所述第一載體之前,加熱所述第一黏合劑至所述可釋放黏合材料的釋放溫度。
- 如請求項1所述的方法,其中從所述半導體晶片分離所述第一載體的步驟包括:在從所述半導體晶片拉開所述第一載體之前,施加剪切力至所述第一載體。
- 如請求項1所述的方法,進一步包括:為所述第二載體提供多個次級全域標記。
- 如請求項1所述的方法,其中所述第二載體的尺寸被確定為容納多於一個所述第一載體。
- 如請求項1所述的方法,其中所述第一載體具有與所述第二載體相比相同或較小的熱膨脹係數。
- 如請求項1所述的方法,進一步包括:在所述第二載體上形成介電層,所述介電層封裝所述半導體晶片。
- 如請求項18所述的方法,進一步包括:基於所述第二全域標記的位置,確定多個端子墊片在所述半導體晶片的每個上的位置;和在所述介電層中形成多個開口,以暴露各自的端子墊片。
- 如請求項18所述的方法,進一步包括:在所述介電層中形成多個開口,以暴露各自的所述第二全域標記。
- 如請求項1所述的方法,進一步包括:執行掃描操作以獲得所述半導體晶片的每一個上的多個端子墊片的位置資料。
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6278193B1 (en) * | 1998-12-07 | 2001-08-21 | International Business Machines Corporation | Optical sensing method to place flip chips |
US20020140063A1 (en) * | 2001-03-30 | 2002-10-03 | Osamu Yamazaki | Semiconductor chip carrying adhesive tape/sheet, semiconductor chip carrier, semiconductor chip mounting method and semiconductor chip packaging body |
US6617702B2 (en) * | 2001-01-25 | 2003-09-09 | Ibm Corporation | Semiconductor device utilizing alignment marks for globally aligning the front and back sides of a semiconductor substrate |
US20060183269A1 (en) * | 2003-07-28 | 2006-08-17 | Edward Fuergut | Method for producing a semiconductor component with a plastic housing and carrier plate for performing the method |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3923023A1 (de) | 1989-07-12 | 1991-01-24 | Siemens Ag | Uv-haertbarer klebstoff fuer ein halbleiterchipmontageverfahren |
US7054492B2 (en) * | 2002-09-24 | 2006-05-30 | Lee Shih-Jong J | Fast regular shaped pattern searching |
KR101127855B1 (ko) * | 2005-06-02 | 2012-03-21 | 엘지디스플레이 주식회사 | 액정표시소자 |
US8241964B2 (en) * | 2010-05-13 | 2012-08-14 | Stats Chippac, Ltd. | Semiconductor device and method of embedding bumps formed on semiconductor die into penetrable adhesive layer to reduce die shifting during encapsulation |
CN102456636B (zh) * | 2010-10-19 | 2015-10-14 | 矽品精密工业股份有限公司 | 嵌入式芯片的封装件的制造方法 |
JP5927756B2 (ja) * | 2010-12-17 | 2016-06-01 | ソニー株式会社 | 半導体装置及び半導体装置の製造方法 |
US8557631B2 (en) * | 2011-12-01 | 2013-10-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interposer wafer bonding method and apparatus |
TWI446501B (zh) | 2012-01-20 | 2014-07-21 | 矽品精密工業股份有限公司 | 承載板、半導體封裝件及其製法 |
US9640487B2 (en) * | 2012-03-28 | 2017-05-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer alignment mark scheme |
TWI473228B (zh) | 2013-04-24 | 2015-02-11 | 矽品精密工業股份有限公司 | 半導體封裝件之製法 |
KR101672640B1 (ko) * | 2015-06-23 | 2016-11-03 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6278193B1 (en) * | 1998-12-07 | 2001-08-21 | International Business Machines Corporation | Optical sensing method to place flip chips |
US6617702B2 (en) * | 2001-01-25 | 2003-09-09 | Ibm Corporation | Semiconductor device utilizing alignment marks for globally aligning the front and back sides of a semiconductor substrate |
US20020140063A1 (en) * | 2001-03-30 | 2002-10-03 | Osamu Yamazaki | Semiconductor chip carrying adhesive tape/sheet, semiconductor chip carrier, semiconductor chip mounting method and semiconductor chip packaging body |
US20060183269A1 (en) * | 2003-07-28 | 2006-08-17 | Edward Fuergut | Method for producing a semiconductor component with a plastic housing and carrier plate for performing the method |
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