CN106469692A - 半导体加工方法 - Google Patents

半导体加工方法 Download PDF

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Publication number
CN106469692A
CN106469692A CN201610662553.2A CN201610662553A CN106469692A CN 106469692 A CN106469692 A CN 106469692A CN 201610662553 A CN201610662553 A CN 201610662553A CN 106469692 A CN106469692 A CN 106469692A
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vector
support
chip
semiconductor chip
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CN106469692B (zh
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周亦歆
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Pep Innovation Pte Ltd
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Pep Innovation Pte Ltd
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Abstract

提供了一种半导体加工方法。该方法包括提供第一载体(10)。在第一载体(10)上提供第一粘合剂(18)，在第一粘合剂(18)上放置多个半导体芯片(20)。提供第二载体(28)。所述第二载体(28)具有多个芯片接收区域(32)。将第一载体(10)和第二载体(28)结合在一起以将半导体芯片(20)附接至第二载体(28)上各自的芯片接收区域(32)。然后从所述半导体芯片(20)分离所述第一载体(10)。

Description

半导体加工方法
技术领域
本发明涉及半导体封装，更具体地，涉及半导体加工方法。
背景技术
可制造性是半导体封装中重要的考虑因素，因为其直接影响封装成本。因此，为了降低包装成本，期望具有一种便于半导体封装处理的基质。
发明内容
因而，在第一方面，本发明提供了一种半导体加工方法。所述半导体加工方法包括：提供第一载体；在所述第一载体上第一粘合剂；在所述第一粘合剂上放置多个半导体芯片；提供第二载体，其中所述第二载体具有多个芯片接收区域；将所述第一载体和第二载体结合在一起以将所述半导体芯片附接至所述第二载体上各自的所述芯片接收区域；以及从所述半导体芯片分离所述第一载体。
结合附图，本发明的其他方面和优点将从通过示例说明本发明原理的以下的详细描述中显而易见。
附图说明
当结合附图阅读时，将更好地理解本发明优选实施例的以下详细描述。本发明通过示例进行说明，并不受附图限制，在附图中，相同的附图标记指示相同的元件。将会理解，附图并非按比例绘出，并且为了易于理解本发明而进行了简化。
图1是根据本发明实施例的第一载体的示意性俯视图；
图2是其上设置有第一粘合剂的图1的第一载体的示意性侧视图；
图3是根据本发明另一实施例的其上设置有第一粘合剂的图1的第一载体的示意性侧视图；
图4是示出图2和图3的第一粘合剂上的多个半导体芯片的放置的示意图；
图5是根据本发明实施例的第二载体的示意性俯视图；
图6是根据本发明另一实施例的第二载体的示意性俯视图；
图7是根据本发明又一实施例的第二载体的示意性俯视图；
图8是根据本发明再一实施例的第二载体的示意性俯视图；
图9是示出根据本发明实施例的设置在第一载体上的半导体芯片的每个上的第二粘合剂的示意性侧视图；
图10是根据本发明另一实施例的设置在第二载体上的芯片接收区域的每个上的第二粘合剂的示意性侧视图；
图11是示出根据本发明实施例的将第一载体的多个第一全局标记与第二载体的多个第二全局标记相应对齐的示意图；
图12是示出第二载体的尺寸被确定为容纳多于一个第一载体的实施例的示意图；
图13是示出根据本发明实施例的第一载体和第二载体结合在一起以将半导体芯片附接至第二载体上的各个芯片接收区域的示意图；
图14是示出根据本发明实施例的施加剪切力以从半导体芯片分离第一载体的示意图；
图15是示出根据本发明实施例的从半导体芯片分离第一载体的示意图；
图16是示出将半导体芯片附加至图5所示的第二载体的示意图；
图17是示出根据本发明实施例的形成于图16所示的第二载体上的介电层的示意性侧视图；
图18是示出根据本发明另一实施例的形成于图16所示的第二载体上的介电层的示意性俯视图；
图19是示出根据本发明另一实施例的半导体加工步骤的示意图；
图20是示出根据本发明又一实施例的半导体加工步骤的示意图；
图21和22是根据本发明其他实施例的第二载体的示意性俯视图；和
图23至26是根据本发明实施例形成的半导体封装的放大剖面图。
具体实施方式
以下结合附图给出的详细描述意为本发明目前优选实施例的描述，并不意在表示可以实践本发明的唯一形式。应理解，可以通过意在包括在本发明的范围内的不同实施例来实现相同或等同的功能。在所有附图中，相同的附图标记自始至终用于指示相同的元件。
图1至22示出根据本发明实施例的半导体加工方法。在本说明书中，术语“全局标记”用于描述载体或初级的位置指示，术语“单元标记”用于描述单元级的位置指示，术语“芯片标记”用于描述半导体芯片上的位置指示，术语“次级全局标记”用于描述多载体或次级的位置指示。
现在参照图1，提供第一或传递载体10。在本实施例中，第一载体10具有多个第一全局标记12。在所示实施例中，第一载体10也具有多个第一单元标记14，第一单元标记14定义多个芯片放置位置16。
第一载体10可以提供为条或板的形式，并且可以由金属构成，例如，钢或铜，金属合金，玻璃或聚合物，例如FR4。在第一载体10由金属材料制成的实施例中，第一全局标记12与第一单元标记14可以通过化学蚀刻、激光蚀刻或使用传统的光刻技术或图案形成工艺的电镀形成于第一载体10上或形成于第一载体10中。在蚀刻的情况下，第一全局标记12和第一单元标记14可以被刻入第一载体10的表面。在电镀的情况下，金属第一载体10可以被用作导电平面，设置的第一全局标记12和第一单元标记14形成在第一载体10的表面上并突出于第一载体10的表面。在第一载体10由玻璃或聚合物制成的实施例中，第一全局标记12与第一单元标记14可以通过激光或油墨雕刻被刻入第一载体10。有利地，当第一载体10由玻璃制成时，因为玻璃具有低的热膨胀系数，因此当第一载体10在随后的工艺步骤中被加热时，形成于第一载体10中的第一全局标记12与第一单元标记14不会明显移动，从而可以提高加工精度。此外，由于第一全局标记12与第一单元标记14直接在第一载体10上生成，因此不涉及可能引入偏移或其它误差的额外工艺步骤。这也有助于提高加工精度。
在所示实施例中，每个第一全局标记12具有不同的形状。有利地，在半导体加工方法中，这有助于定位第一载体10和相对于第一载体10定位其它元件或部件。
尽管在所示实施例中示出在第一载体10的表面上设置两个(2)全局标记12并且示出提供两个(2)单元标记14以定义每个芯片放置位置16，但对于本领域普通技术人员应当理解的是，本发明并不受限于提供的第一全局标记12或第一单元标记14的数量。在可选实施例中，第一载体10可以具有更多数量的第一全局标记12和/或第一单元标记14。
在本实施例中，可以基于第一全局标记12的位置确定第一单元标记14的位置。每个第一全局标记12可以设置在相对于另一个第一全局标记12固定的或选定的位置，每个第一单元标记14可以设置在相对于第一全局标记12和同一芯片放置位置16中的其他第一单元标记14固定的或选定的位置。第一全局标记12可以用于计算和确定第一单元标记14的位置，第一单元标记14可以用于计算和确定每个芯片放置位置16的中心，每个芯片放置位置16对应于将要安装的半导体芯片的单元位置。在这样的实施例中，芯片放置位置16的中心处于相对于第一全局标记12固定的或选定的位置。
现在参照图2，如图所示，在第一或传递载体10上设置第一粘合剂18。第一粘合剂18可以通过层压、或通过丝网印刷或通过涂覆设置在第一或传递载体10上。
在本实施例中，第一粘合剂18包括可释放粘合材料，可释放粘合材料具有释放机制，例如，在暴露于热、紫外线辐射、红外线辐射或化学溶液时导致可释放粘性材料失去实质的粘合强度。在一个实施例中，第一粘合剂18可以是粘合强度在暴露于热时显著减少的热释放薄膜。
在所示实施例中，第一全局标记12与第一单元标记14被刻入第一载体10，因此不能延伸超过第一载体10的表面。在这样的实施例中，第一粘合剂18可以是透明的或半透明的，使得第一全局标记12与第一单元标记14是通过第一粘合剂18可见的。
现在参照图3，示出了其上设置有第一粘合剂18的第一载体10的可选实施例。在所示实施例中，第一全局标记12与第一单元标记14形成于第一载体10的表面上并从第一载体10的表面突出。在这样的实施例中，第一粘合剂18封装第一全局标记12与第一单元标记14，使得只有第一全局标记12和第一单元标记14的上表面被暴露。在该实施例中，第一粘合剂18可以是不透明的。
现在参照图4，多个半导体芯片20被放置在如图2或3所示的第一粘合剂18上。
半导体芯片20的每一个可以是处理器，例如数字信号处理器(DSP)，专用功能电路，例如存储器地址发生器，或执行任何其它类型的功能。此外，半导体芯片20不限于特别的技术例如CMOS，或不限于从任何特定晶片技术得到。此外，本领域技术人员可以理解的是，本发明可以适应各种芯片尺寸。半导体芯片20的每一个具有活性表面(activesurface)22和与活性表面相对的虚表面(dummy surface)24。用于电连接到芯片电路的端子垫片(未示出)设置在半导体芯片20的活性表面22上。
在本实施例中，多个芯片标记26设置在半导体芯片20的每一个上，芯片标记26设置在半导体芯片20的活性表面22上。芯片标记26的每一个可以设置在相对于其它芯片标记26和/或端子垫片固定的或指定的位置，并且可以用于计算和确定半导体芯片20的每一个的中心。在一个实施例中，半导体芯片20上的区别性特征可用作或充当芯片标记26。
在所示的本实施例中，在将各自的半导体芯片20放置在第一粘合剂18之前，将半导体芯片20的每一个上的芯片标记26与相应的第一单元标记14对齐。以这种方式，当各自的半导体芯片20被放置在第一或传递载体10上时，半导体芯片20的每一个的中心与每个相应的单元或芯片放置位置16的中心对齐，半导体芯片20的每一个与相应的单元或芯片放置位置16对齐。因此，半导体芯片20的每一个的中心和位置也在相对于第一或全局标记固定的或指定的位置。这种对齐可以由视觉系统执行，所述视觉系统包括摄像单元和计算并调整半导体芯片20的位置的控制器单元。
当被放置在第一或传递载体10上时，半导体芯片20的活性表面22面对第一或传递载体10并粘附到第一粘合剂18。第一粘合剂18有助于在随后的工艺步骤期间防止半导体芯片20的任何不必要的位移，也有助于确保半导体芯片20的每一个总是处于相对于第一全局标记12固定的或指定的位置。
在第一粘合剂18是糊剂形式、半固体形式或半熔态(B-stage)形式的实施中，第一粘合剂18可以进一步通过热或辐射被固化以增加其材料的弹性模量和至半导体芯片20的粘附。
现在参照图5，提供第二或支撑载体28，第二载体28具有多个芯片接收区域32。在本实施例中，第二载体28还具有多个第二全局标记30。在本实施例中，芯片接收区域32包括设置在第二载体28上的多个芯片垫片34，芯片垫片34的每一个对应于半导体芯片20中的一个将要被安装或附接至的芯片接收区域或单元区域32。
第二载体28可以被提供为条或板的形式。在一个实施例中，第二载体28由导电和化学可蚀刻材料，例如，铜或钢，或其的层形成。在另一实施例中，第二载体28可以是聚合树脂绝缘片，层压有导电和化学可蚀刻材料例如铜的层。
在所示实施例中，第二全局标记30的每一个具有与对应的第一全局标记12相同的形状。有利地，在随后的加工步骤中有助于第二载体28相对于第一载体10的定位。
尽管在所示实施例中示出两个(2)全局标记30设置在第二载体28的表面上，但是对于本领域普通技术人员来说应当理解的是，本发明并不受限于提供的第二全局标记30的数量。例如，在可选的实施例中，第二载体28可以具有更多数量的第二全局标记30。
在本实施例中，第二全局标记30的每一个设置在相对于其它第二全局标记30固定的或选定的位置，芯片垫片34的每一个设置在相对于第二全局标记30和其它芯片垫片34固定的或选定的位置。第二全局标记30可以用于计算和确定芯片接收区域32的位置，因此也确定芯片垫片34的位置。在优选实施例中，芯片垫片34的每一个的中心对应于相应的芯片接收区域32的中心。
芯片垫片34可使用标准光刻技术和图案形成工艺通过电镀而形成，由此形成的芯片垫片34从第二载体28的表面突出。在优选实施例中，第二全局标记30可以通过电镀与芯片垫片34一起形成，并且也从第二载体28的表面突出。在可选的实施例中，可以在形成芯片垫片34之前首先通过化学蚀刻或使用激光或油墨的雕刻形成第二全局标记30。
现在参照图6，示出第二载体28的可选实施例。在所示实施例中，多个第二单元标记36形成在邻近各自的芯片垫片34的第二载体28的表面上。
在本实施例中，第二单元标记36设置在芯片接收区域32中，成对的第二单元标记36定义相应的芯片接收区域326。尽管在所示的实施例中示出设置两个(2)单元标记36以定义芯片接收区域32的每一个，但是对于本领域普通技术人员来说应当理解的是，本发明并不受限于提供的第二单元标记36的数量。例如，在可选的实施例中，可以提供较多数量的第二单元标记36以定义芯片接收区域32的每一个。
在本实施例中，可以基于第二全局标记30的位置确定第二单元标记36的位置。第二单元标记36的每一个可以设置在相对于第二全局标记30、也相对于芯片垫片34以及同一芯片接收区域32中的其它第二单元标记36固定的或选定的位置。第二全局标记30可以用来计算和确定位置第二单元标记36的位置，第二单元标记36可以用于计算和确定芯片接收区域32和芯片垫片34的中心，使得芯片接收区域32和芯片垫片34的中心也处于相对于第二全局标记30固定的或选定的位置。
现在参照图7，示出了又一实施例的第二载体28。在该实施例中，第二单元标记36形成在芯片垫片34的本身上。
现在参照图8，示出了再一实施例的第二载体28。在该实施例中，没有形成单独的芯片垫片34，第二载体28包括通过包覆或电镀设置在第二载体28的表面上的金属例如铜或镍的层38。在这样的实施例中，第二全局标记30可以通过电镀形成于第二载体28上，并因此从表面突出。第二全局标记30也可以通过化学蚀刻或使用激光或油墨的雕刻形成于第二载体28上。
现在参照图9，如图所示，第二粘合剂40设置在第一载体10上的半导体芯片20的每一个上。更具体地，在所示实施例中，粘结层(bonding layer)40设置在第一载体10上的半导体芯片20的虚表面24上。这可以通过网版丝印(stencil screen printing)、或针头或喷射点胶设置。第二粘合剂40可以是环氧基芯片附接粘合剂、丙烯酸基芯片附接粘合剂或热界面材料，例如，银浆。在可选的实施例中，第二粘合剂40可以在单片化之前预先形成于半导体芯片20上，例如，以管芯附接薄膜的形式。有利地，当在第一载体10上的半导体芯片20上设置第二粘合剂40时，第二载体28可以预先加热，更快地上升到选定的温度。
现在参照图10，示出可选的实施例，其中相反地，粘合或粘结层40设置于第二载体28的芯片接收区域32的每一个上。
现在参照图11，如本发明实施例所示，第一载体10的第一全局标记12与第二载体28中相应的第二全局标记30对齐。以这种方式，传递载体10与支撑载体28对齐，传递载体10上的半导体芯片20与支撑载体28上相应的芯片垫片大体对齐。当传递载体20和支撑载体28以这种方式定位时，半导体芯片20和相应的芯片垫片34面对彼此，半导体芯片20的每一个的中心与相应的芯片垫片34的每一个的中心大体对齐。
现在参照图12，示出了第二载体28的尺寸被确定为容纳多于一个(1)第一载体10的实施例。本实施例不同于前述实施例，使用多个第一或传递载体10在第二支撑载体28上放置半导体芯片20。在这个实施例中，每个传递载体10的尺寸小于支撑载体28的尺寸，每个传递载体10将一组半导体芯片20放置在支撑载体28上。有利地，这增加在支撑载体28上放置芯片的精度。进一步有利地，将第二载体28的尺寸确定为容纳多于一个(1)第一载体10的使用也提高半导体加工的效率，帮助减少加工时间。在所示实施例中，除了用于将支撑载体28与各个传递载体10的每个对齐的初级全局标记30之外，第二载体28具有多个次级全局标记，多个次级全局标记用于随后的加工步骤中的整个第二或支撑载体28及放置于其上的全部半导体芯片20的加工。
现在参照图13，如图所示，第一载体10和第二载体28被结合在一起以将半导体芯片20附接至第二载体28上各自的芯片接收区域32。这可以是将传递载体32放置在支撑载体28上使得半导体芯片20的虚表面24接触粘结层40且半导体芯片20的中心与相应的芯片垫片34的中心大体对齐。通过粘结层40将第一载体10和第二载体28的组件机械地锁定在适当的位置。
当传递载体10被放置在支撑载体28上使得半导体芯片20的虚表面24接触粘结层40时，第二粘合剂40的一部分被部分地替换为传递载体10的块。但是，因为半导体芯片20的活性表面22粘附至第一粘合剂18，通过第一粘合剂18避免被替换的第二粘合剂40流进或进入半导体芯片20的活性表面22。当加工厚度在25微米(μm)和大约50μm之间的薄芯片裸片时，这是特别有利的。
在本实施例中，在将第一载体10和第二载体28结合在一起之后，第二粘合剂40被加热至第二粘合剂40的固化温度。这固化了粘结层40，并增大了粘结层40的模量和粘合强度以将半导体芯片20锁定在相对于第一全局标记12和第二全局标记30固定的或选定的位置。在一个实施例中，第一载体10和第二载体28的组件被加热到升高的第一温度，第一温度约为150摄氏度(℃)且对应于采用的粘结层40的固化温度。
在从半导体芯片20分离第一载体10之前，可以在加热第一粘合剂18至可释放粘合材料的释放温度之前冷却第一载体10和第二载体28的组件。该加热操作导致第一粘合剂18大体失去粘合强度，这有助于随后从半导体芯片20分离第一载体10。可释放粘合材料的释放温度高于第二粘合剂40的固化温度。在一个实施例中，第一载体10和第二载体28的组件被加热到升高的第二温度，第二温度约为200℃且对应于使用的可释放粘合材料的释放温度。
换句话说，在粘结层40固化并增加至半导体芯片20的粘合强度之后，第一粘合剂18丧失至半导体芯片20的粘合强度。
两步加热过程可以在一个(1)机器中执行或通过使用两个(2)机器执行。在后者的实施例中，第一载体10和第二载体28的组件可以在被冷却之前在第一机器中被加热，然后输送到第二机器以进行第二加热操作。
在固化第二粘合剂40之前，粘结层40可以是糊状或流体状态。在这样的实施例中，传递载体10上的第一粘合剂18有助于防止当通过第一粘合剂18将半导体芯片20放置在适当的位置时，半导体芯片20由于表面张力或粘结层40的浮力作用发生从中心位置的非自愿移位。因此，半导体芯片20的相对位置保持基本相同，即使在半导体芯片20被传递到支撑载体28上之后。
当传递载体10和支撑载体28由不同的材料制成时，存在热膨胀系数(CTE)的差异。随着温度的升高，传递载体10和支撑载体28以不同速率膨胀。当第一粘合剂18比未固化的粘结层40具有明显更强的粘合强度时，在膨胀期间半导体芯片20趋向于跟随传递载体10，因此优选地，传递载体10的热膨胀系数(CTE)小于支撑载体28的热膨胀系数。相应地，本实施例中的第一载体10可以具有与第二载体28相比相同或较小的热膨胀系数(CTE)。例如，在一个示例性实施例中，传递载体10可以由CTE约为每摄氏度百万分之三(3ppm/℃)的玻璃制成，支撑载体28可以由CTE约为11ppm/℃的钢制成。在优选实施例中，第一载体10和第二载体28由相同的材料制成，使得加热时膨胀率是相同的。
现在参照图14和15，示出了从半导体芯片20分离第一载体10。如图14和15所示，从半导体芯片20分离第一载体10的步骤包括：在从半导体芯片20拉开第一载体10之前，施加剪切力至第一载体10，更具体地，分离行为包括剪切(传递载体10和支撑载体28之间的角位移和横向位移)，然后拉(传递载体10和支撑载体28之间的垂直位移)，以最小化半导体芯片20的损害和不必要的移动。半导体芯片20通过粘结层40牢固地保持在芯片垫片34上的合适位置。
在本实施例中，传递载体10从支撑载体28分离，而第一载体10和第二载体28的组件保持在第二升高温度下。
现在参照图16，当传递载体10从支撑载体28分离时，第一粘合剂18从半导体芯片20的活性表面22分离。因此，半导体芯片20的活性表面22被暴露并背对支撑载体28。因此，半导体芯片20的端子垫片和芯片标记26也被暴露。
然后可以在半导体芯片20的活性表面22上执行清洁操作，以从第一粘合剂18除去残余物。这可以是等离子体或化学清洗。
在一个实施例中，扫描操作可以在这个时候执行以获得半导体芯片20的每一个上的端子垫片的位置数据，用于随后的加工步骤。这可以通过使用光学视觉系统实现。更具体地，光学视觉系统的检测器或摄像机可以识别待被捕获的的多个特征(例如，突出的形状、颜色对比度或两者的组合)，对应的特征的位置数据可以被记录从而在随后的加工步骤中使用。
在上述方式中，半导体芯片20可以被同时从传递载体10传递到支撑载体28，半导体芯片20的每一个被准确地放置并且与对应的芯片垫片34大体对齐，半导体芯片20的每一个的中心与相应的芯片垫片34的中心大体对齐。半导体芯片20因此被定位在相对于支撑载体28上的第二全局标记30固定的或选定的位置，可以通过第二全局标记30计算并确定半导体芯片20的每一个的位置。相应地，由于可以通过第二全局标记30计算并确定半导体芯片20的每一个的位置，并且每个半导体芯片20上的端子垫片的位置处于相对于相应的芯片中心固定的或选定的位置，因此也可以从第二全局标记30计算和确定每个半导体芯片20上的端子垫片的位置。
现在参照图17，如图所示，在第二载体28上形成介电层44，介电层44封装半导体芯片20。在所示实施例中，介电层44仅封装半导体芯片20和芯片垫片34，而不覆盖第二全局标记30。
介电层44可以通过模塑、层压或印刷工艺形成在第二载体28上。在一个实施例中，使用膜片或糊剂形式的环氧化合物形成介电层44。介电层44的厚度可以通过研磨或抛光变薄，而不暴露半导体芯片20。
在一个实施例中，可以在此时执行扫描操作以获得半导体芯片20的每一个上的端子垫片的位置数据，用于随后的加工步骤。这可以是使得封装半导体芯片20的介电层44暴露至电磁辐射(例如，X-射线、红外射线或紫外射线)，允许视觉系统的检测器或摄像机捕获和记录半导体芯片20的每一个上的端子垫片的位置数据，用于随后的加工步骤。
现在参照图18，示出了在第二载体28上形成介电层44的另一实施例。在该实施例中，第二全局标记30最初被介电层44覆盖和封装。因此，多个第一开口46形成于介电层44中，以暴露各个第二全局标记30。
第二载体28上的第二全局标记30可以通过例如激光钻孔而暴露。标记开口46的尺寸可以大于第二全局标记30的尺寸以确保第二全局标记30在标记开口46中完全暴露。
在本实施例中，首先基于第二全局标记30的位置确定半导体芯片20的每一个上的多个端子垫片48的位置，然后在介电层44中形成多个第二开口50以暴露各自的端子垫片48。有利地，所述从传递载体10传递半导体芯片20至支撑载体28的半导体加工方法允许从支撑载体28上的第二全局标记30准确计算并确定端子垫片48的位置。形成第二开口50的精度是关键的，因为第二开口50和相应的端子垫片48之间的任何不对齐可以损坏半导体芯片20的灵敏电路。因此，基于第二全局标记30的位置计算并确定半导体芯片20上的端子垫片48的精确位置的能力提供显著的优点。
第二开口50可以通过例如激光钻孔或点火形成。激光点火可以使用激光直接成像(LDI)系统与视觉和控制器系统，以允许生成精确的图案。更具体地，视觉能力有助于定位第二全局标记30，控制器系统有助于计算半导体芯片20和相应的端子垫片48的相对位置。激光系统然后移动到端子垫片48上方的精确位置以生成第二开口50。在一个实施例中，从较早的扫描操作获得的端子垫片48的位置数据可以用于定位端子垫片48以形成第二开口50。
在所示实施例中，在介电层44的第二开口50中形成多个通孔52，在介电层44的表面上形成多个导电迹线54。通孔52将半导体芯片20的活性表面22上的端子垫片48连接到导电迹线54。
通孔52和导电迹线54可以通过半加成电镀工艺形成。更具体地，可以通过无电沉积工艺在介电层44的表面和通孔52的侧壁上沉积金属种子层，随后在介电层44上设置光致抗蚀剂层。然后可以利用IDL或掩模曝光对光致抗蚀剂层形成图案。然后，可以在第二开口50中形成通孔52，利用导电材料例如铜在种子层上形成导电迹线54。最后，去除种子层的任何暴露部分。
在图案化光致抗蚀剂层的步骤中，第二全局标记30再次用作参考特征以计算和确定图案相对于半导体芯片20的相对位置。在使用LDI的实施例中，视觉和控制器系统定位第二全局标记30并通过参考第二全局标记30计算半导体芯片20的位置。在使用掩膜曝光的实施例中，掩膜上的对应标记与支撑载体28上的第二全局标记30对齐。掩膜上的图案形成在光致抗蚀剂层上，并对应于半导体芯片20的适当位置。
支撑载体28的全局标记30还用在随后的形成半导体封装的步骤中，以准确地计算和确定半导体芯片20和其对应的端子垫片48的位置。由于使用全局标记30的一般方法与上述方法类似，无需进一步的描述以完整理解本发明。
在密封步骤之后，可以通过化学蚀刻或机械分离去除第二载体28，可以通过激光或机械切削或切割穿过介电层44分离半导体芯片20，以获得多个半导体封装单元。
现在参照图19，示出了第一载体10和第二载体28的装配的另一实施例。不同于前述实施例，本实施例中，多个元件垫片56设置在第二载体28上。元件垫片56中的每一个可以设置在相对于第二全局标记30、也相对于芯片垫片34和其它元件垫片56固定的或指定的位置。第二全局标记30可以用来计算和确定元件垫片56的位置。元件垫片56可以与芯片垫片34一起形成在第二载体28上。
多个结构特征58、多个无源元件60或其组合可以形成于第二载体28上的各自的元件垫片56上或附接到第二载体28上的各自的元件垫片56。在可选的实施例中，元件垫片56可省略，结构特征58和/或无源元件60可以直接形成于第二载体28或芯片垫片34上或附接到第二载体28或芯片垫片34。结构特征58可以是用于垂直连接的互连或柱列，用于射频(RF)屏蔽的壁结构或用于增强生成的半导体封装的结构完整性的图案化结构。结构特征58可以通过电镀、刻蚀第二载体或附接外部部件至第二载体28而预先形成。可以结合电镀或蚀刻使用光刻以在第二载体28上形成结构特征58的各种图案或构造。可选地，外部部件可通过常规的表面安装工艺被附接到第二载体28。
无源元件60可以是电容器、电阻器、二极管、电感器或集成无源设备(IPD)。在将无源元件60放置到元件垫片56上之前，可以将例如环氧树脂或焊料的粘结层62分配到元件垫片56上。可选地，无源元件60可以具有预先形成在无源元件60的多个电极上的粘结层，用于附接至元件垫片56。在用无源元件60填充支撑载体28之后可以使得支撑载体28经历热处理，以确保完全的粘结。
为了避免妨碍第一载体10和第二载体28的装配，结构特征58和无源元件60的上表面低于半导体芯片20的活性表面22。如果芯片垫片34和元件垫片56具有相同的厚度，半导体芯片20的厚度必须基本上等于或大于结构特征58和无源元件60的厚度。可以通过研磨或抛光半导体芯片20指定或控制半导体芯片20的厚度。
因此，在所示实施例中，结构特征58和无源元件60的高度小于半导体芯片20的厚度。因此，在将半导体芯片20从传递载体10传递到支撑载体28的过程中，结构特征58和无源元件60不会接触第一粘合剂18，也不影响半导体芯片20与芯片垫片34的接触。
现在参照图20，示出了第一载体10和第二载体28的装配的另一实施例。在该实施例中，半导体芯片20的厚度小于无源元件60的厚度。因此，在半导体芯片20的每一个和对应的芯片垫片34之间设置间隔件64，以增加半导体芯片20的活性表面22的高度。在可选的实施例中，可以通过将芯片垫片34电镀至更厚的厚度而提高半导体芯片20的活性表面22的高度。
第二载体28上的无源元件60和结构特征58的示例性布局示于图21和22，如下所述。
现在参照图21，在所示实施例中，结构特征58围绕芯片垫片34设置在第二载体28上。
现在参照图22，在本实施例中，无源元件60被设置在第二载体28上的各自的元件垫片56上或附接至第二载体28上的元件垫片56。无源元件60可以采用常规的表面安装工艺通过元件放置被设置在元件垫片56上或附接至元件垫片56。
半导体加工方法形成的示例性半导体封装示于图23至26，如下所述。
现在参照图23，示出了半导体封装66。半导体封装66包括：通过第二粘合剂40附接到芯片垫片34的半导体芯片20。半导体芯片20由第一介电层44封装。穿过第一介电层44形成的多个第一通孔52将半导体芯片20连接到多个第一导电迹线54。
现在参照图24，示出了半导体封装68。半导体封装68不同于前述实施例，第一导电迹线54由第二介电层70封装，穿过第二介电层70形成的多个第二通孔72将第一导电迹线54连接到多个第二导电迹线74。第二导电迹线74由第三介电层76封装。以这种方式，可以适用常规的层构建工艺顺序地添加多层的导电迹线，以提供更高的布线密度和复杂性。第二介电层70和第三介电层76可以是，例如，环氧模塑料或膜、织造玻璃纤维层或焊料掩模。
现在参照图25，示出了半导体封装78。与前述实施例不同，半导体封装78包括多个结构特征58。结构特征58也被第一介电层44封装，并第一通孔52电连接至第一导电迹线54。第一导电迹线54由第二介电层70封装。在本实施例中，结构特征58是提供从半导体封装78的一个表面到半导体封装78的相对表面的电连接路径的互连柱。有利地，这允许另一半导体封装堆叠在半导体封装件78上，以形成堆叠半导体封装。
现在参照图26，示出了半导体封装80。半导体封装80不同于前述实施例，半导体封装件80包括设置在多个元件垫片56个或附接到多个元件垫片56的多个无源元件60。无源元件60也被第一介电层44封装，并通过第一通孔5电连接至第一导电迹线54，通过第一导电迹线54电连接至半导体芯片20。第一导电迹线54被第二介电层70封装。从前述讨论显然可知，本发明提供了一种半导体加工方法，该方法允许同时加工多个半导体芯片。有利地，这增加加工效率，并降低加工时间和成本。另外，通过在半导体加工过程中提供全局标记作为位置指示，也改进了加工精度和产品的可靠性。
呈现本发明的优选实施例的描述是为了说明和描述，而并不意在排他或将本发明限制为所公开的形式。本领域技术人员将会理解，可以在不偏离广义的发明概念的情况下对上述实施例做出改变。因而可以理解，本发明不限于所公开的特定实施例，而是覆盖由所附权利要求限定的本发明的范围内的修改。
此外，除非上下文明确需要，在整个说明书和权利要求书中，词“包括”、“包含”等应被理解为与排他或穷举含义相对的包含；也就是说，其含义为“包括但不限于”。

Claims (24)

1.一种半导体加工方法，包括：
提供第一载体；
在所述第一载体上提供第一粘合剂；
在所述第一粘合剂上放置多个半导体芯片；
提供第二载体，其中所述第二载体具有多个芯片接收区域；
将所述第一载体和第二载体结合在一起以将所述半导体芯片附接至所述第二载体上各自的所述芯片接收区域；以及
从所述半导体芯片分离所述第一载体。
2.根据权利要求1所述的方法，其中所述第一载体具有多个第一全局标记，所述第二载体具有多个第二全局标记，其中在将所述第一载体和第二载体结合在一起之前将所述第一全局标记与相应的第二全局标记对齐。
3.根据权利要求2所述的方法，其中所述第一全局标记的每一个具有不同的形状，所述第二全局标记的每一个具有与相应的所述第一全局标记相同的形状。
4.根据权利要求2所述的方法，进一步包括：为所述第一载体提供多个第一单元标记，所述第一单元标记定义多个芯片放置位置。
5.根据权利要求4所述的方法，其中为所述第一载体提供多个第一单元标记的步骤包括：基于所述第一全局标记的位置确定所述第一单元标记的位置。
6.根据权利要求4所述的方法，进一步包括：在所述第一粘合剂上放置各个半导体芯片之前，将所述半导体芯片的每一个上的多个芯片标记与相应的所述第一单元标记对齐。
7.根据权利要求6所述的方法，其中所述芯片标记设置在所述半导体芯片的活性表面上。
8.根据权利要求2所述的方法，其中所述芯片接收区域包括设置在所述第二载体上的多个芯片垫片。
9.根据权利要求8所述的方法，进一步包括：在与各个所述芯片垫片相邻的所述第二载体的表面和所述芯片垫片自身中的一个上形成多个第二单元标记。
10.根据权利要求9所述的方法，其中形成所述第二单元标记的步骤包括：基于所述第二全局标记的位置确定所述第二单元标记的位置。
11.根据权利要求1所述的方法，进一步包括：在所述第二载体上提供多个元件垫片。
12.根据权利要求11所述的方法，进一步包括：将多个结构特征、多个无源元件或其组合附接至所述第二载体上的各个所述元件垫片。
13.根据权利要求1所述的方法，进一步包括：在所述半导体芯片的每一个和所述芯片接收区域的每一个中的一个上设置第二粘合剂。
14.根据权利要求13所述的方法，进一步包括：在将所述第一载体和所述第二载体结合在一起之后，加热所述第二粘合剂至所述第二粘合剂的固化温度。
15.根据权利要求1所述的方法，其中所述第一粘合剂包括可释放粘合材料。
16.根据权利要求15所述的方法，进一步包括：在从所述半导体芯片分离所述第一载体之前，加热所述第一粘合剂至所述可释放粘合材料的释放温度。
17.根据权利要求1所述的方法，其中从所述半导体芯片分离所述第一载体的步骤包括：在从所述半导体芯片拉开所述第一载体之前，施加剪切力至所述第一载体。
18.根据权利要求2所述的方法，进一步包括：为所述第二载体提供多个次级全局标记。
19.根据权利要求1所述的方法，其中所述第二载体的尺寸被确定为容纳多于一个所述第一载体。
20.根据权利要求1所述的方法，其中所述第一载体具有与所述第二载体相比相同或较小的热膨胀系数。
21.根据权利要求2所述的方法，进一步包括：在所述第二载体上形成介电层，所述介电层封装所述半导体芯片。
22.根据权利要求21所述的方法，进一步包括：
基于所述第二全局标记的位置，确定多个端子垫片在所述半导体芯片的每个上的位置；和
在所述介电层中形成多个开口，以暴露各自的端子垫片。
23.根据权利要求21所述的方法，进一步包括：在所述介电层中形成多个开口，以暴露各自的所述第二全局标记。
24.根据权利要求1所述的方法，进一步包括：执行扫描操作以获得所述半导体芯片的每一个上的多个端子垫片的位置数据。
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