CN101179068A - 多堆叠封装及其制造方法 - Google Patents

多堆叠封装及其制造方法 Download PDF

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Publication number
CN101179068A
CN101179068A CNA2007101671925A CN200710167192A CN101179068A CN 101179068 A CN101179068 A CN 101179068A CN A2007101671925 A CNA2007101671925 A CN A2007101671925A CN 200710167192 A CN200710167192 A CN 200710167192A CN 101179068 A CN101179068 A CN 101179068A
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China
Prior art keywords
encapsulation
semiconductor chip
substrate
opening
multiple pileup
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CNA2007101671925A
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English (en)
Inventor
边鹤均
赵泰济
沈钟辅
韩相旭
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN101179068A publication Critical patent/CN101179068A/zh
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Abstract

本发明的实施例提供了一种具有上和下封装的MSP，在上封装的基板中具有凹陷开口。上封装还可包括多个堆叠的半导体芯片。下封装可以包括基板和至少一个半导体芯片。在装配期间，部分下封装放置在上封装的基板中的凹陷开口中。有利的结果是具有缩小的总高度的两个封装MSP装配。此外，还可以缩小在上封装基板和下封装基板之间的焊料球或其它接头的尺寸和间距。

Description

多堆叠封装及其制造方法
技术领域
本发明涉及一种半导体芯片封装及其制造方法，更特别地，涉及具有多个堆叠的半导体芯片的多堆叠封装(multi stack package，MSP)及其制造方法。
背景技术
随着半导体工业的发展，电子器件变得更小、更轻和多功能。多堆叠封装(MSP)已发展为将多个半导体器件(或芯片)结合到一个单元封装中。如在这里所用，MSP或封装涉及电子装配。与单个半导体芯片封装相比，MSP具有改进的尺寸、重量和安装面积。
图1为说明传统多堆叠封装(MSP)的结构的横截面图。
参考图1，传统MSP 10具有一种堆叠结构，其中下封装12包括在基板20上由密封剂28覆盖的半导体芯片22，和上封装14包括在基板30上由密封剂38覆盖且具有垂直堆叠和对准的半导体芯片32和34的堆叠模块。焊盘26和36分别形成在基板20和基板30上，用于将基板电连接至外部电路。下封装12经由作为焊盘26和焊盘36之间的接头的焊料球40电连接至上封装14。如在这里所用，接头是导电元件，其提供MSP的两个相对元件之间的电连接。
在图1中说明的MSP 10的结构中，通过下封装12的高度h1和上封装14的高度h2部分地确定MSP 10的整个高度h。为了获得MSP 10的小的整个高度h，必须缩减下封装12的高度h1和上封装14的高度h2。通过缩减封装12中半导体芯片22的高度和封装14中半导体芯片32和34的高度，通过缩减从半导体芯片22的上表面到密封剂28的上表面的高度和从半导体芯片34的上表面到密封剂38的上表面的高度，或通过缩减基板20和30的厚度可实现上述目的。然而，由于技术限制，这些方法很难应用到封装工艺中。
此外，由于半导体芯片22和密封剂28的高度h3而必须在下封装12和上封装14之间设置间隙，所以不可能将下封装12和上封装14之间的焊料球40的尺寸缩减为需要的尺寸。因此，限制了焊料球的间距，和于是限制了在基板的有限空间内形成的输入/输出线密度。
发明内容
本发明的实施例提供了一种具有上和下封装的MSP，在上封装的基板中具有凹陷开口。上封装还可包括多个堆叠的半导体芯片。下封装可包括基板和至少一个半导体芯片。在装配期间，部分下封装放置在上封装的基板中的凹陷开口中。有利的结果是具有缩小总高度的两个封装MSP装配。此外，还可以缩小在上封装基板和下封装基板之间的焊料球或其它接头的尺寸和间距。
依照本发明的一方面，提供了一种多堆叠封装，包括第一封装和第二封装，第一封装包括第一基板和第一半导体芯片，第一半导体芯片由第一粘合层安装到第一基板，第一基板具有第一开口，第一开口关于第一半导体芯片在垂直方向上基本对准；和第二封装耦合第一封装，第二封装包括第二基板和第二半导体芯片，第二半导体芯片由第二粘合层安装到第二基板，第二半导体芯片关于第一开口在垂直方向上基本对准，至少一部分第二封装延伸到由第一开口限定的空间中使得多堆叠封装的高度小于与第一封装和第二封装有关的高度之和。
依照本发明的另一方面，提供了一种多堆叠封装的制造方法。该方法包括：在第一基板上安装第一半导体芯片，安装第一半导体芯片包括施加第一粘合层到第一基板；在第二基板上安装第二半导体芯片；密封第二半导体芯片以形成密封的第二半导体芯片；去除一部分第一基板以产生第一开口，第一开口关于第一半导体芯片在垂直方向上基本对准；和将至少一部分密封的第二半导体芯片插入到第一开口中。
依照本发明的另一方面，提供了一种多堆叠封装的制造方法。该方法包括：去除一部分第一基板以产生第一开口；在第一基板上安装第一半导体芯片，第一半导体芯片关于第一开口在垂直方向上基本对准，安装第一半导体芯片包括施加第一粘合层到第一基板；在第二基板上安装第二半导体芯片；密封第二半导体芯片以形成密封的第二半导体芯片；和将至少一部分密封的第二半导体芯片插入到第一开口中。
附图说明
本发明的上述和其它特征和优点将通过参考附图详细描述其示范性实施例变得更显而易见，附图中：
图1为说明传统多堆叠封装(MSP)的结构的横截面图；
图2为依照本发明一实施例的多堆叠封装的横截面图；
图3为依照本发明另一实施例的多堆叠封装的横截面图；
图4为依照本发明又一实施例的多堆叠封装的横截面图；
图5为依照本发明又一实施例的多堆叠封装的横截面图；
图6为说明依照本发明一实施例的多堆叠封装制造方法的流程图；
图7为说明依照本发明另一实施例的多堆叠封装制造方法的流程图；和
图8至10为说明依照图7中所述本发明实施例的多堆叠封装制造方法的一些顺次工艺的横截面图。
具体实施方式
现将参考其中显示本发明优选实施例的附图更加全面地描述本发明。然而，本发明可以以许多不同的形式实现且不应解释为限于这里阐述的实施例。而是，提供这些实施例使得本公开充分和完整，且向那些本领域的技术人员全面地传达本发明的范围。通篇相似的附图标记指示相似的元件。
图2为依照本发明一实施例的多堆叠封装100的横截面图。
参考图2，依照本发明一实施例的多堆叠封装100包括垂直堆叠的封装102和封装104。
上封装102包括具有相对表面120a和120b的基板120。半导体芯片132安装在基板120的表面120a上，且半导体芯片134安装在半导体芯片132的表面上。基板120可以是常规的印刷电路板(PCB)、软性PCB、硅基板、陶瓷基板或其它基板技术。
基板120包括在关于半导体芯片132和134的基板的对立侧上的开口120h。开口120h小于半导体芯片132的足印。开口120h垂直对准半导体芯片132。在图2说明的多堆叠封装100中，开口120h的形式为穿透基板120的通孔。然而，本发明不限于此。例如，开口120h可以具有小于基板120的整个厚度的深度，不穿透基板120。在图2说明的多堆叠封装100的封装102中，粘合层122经由开口120h暴露出来并且面对由密封剂168密封的半导体芯片162。
基板120还包括开口120h周围的导电图案区域120p。半导体芯片132通过粘合层122固定在基板120的表面120a上，和半导体芯片134通过粘合层124固定在半导体芯片132的上表面上。半导体芯片132和134通过焊线126与基板120的表面120a上暴露的导电焊盘128耦合，并电连接到基板120。半导体芯片132和134以及焊线126都由例如环氧模塑化合物(EMC)的密封剂138密封住。
在图2所述的依照本发明一实施例的多堆叠封装100中，封装102显示为包括具有两个顺序堆叠的半导体芯片132和134的半导体芯片堆叠模块。然而，本发明并不限于此，且第一封装102可包括具有三个或更多顺序堆叠的半导体芯片的半导体芯片堆叠模块。
下封装104包括具有相对表面140a和140b的基板140，且半导体芯片162安装在基板140的表面140a上。封装104还包括密封剂168。根据设计选择，基板140可以是典型的PCB、软性PCB、硅基板、陶瓷基板或其它基板技术。
基板140包括在半导体芯片162下面和周围的导电图案区域140p。半导体芯片162通过粘合层152贴装到基板140的表面140a。半导体芯片162通过焊线156与基板140的表面140a上暴露的导电焊盘148耦合，且电连接基板140。半导体芯片162和焊线156由例如EMC的密封剂168密封住。可通过例如顶浇口模塑工艺(top gate mold process)的部分模塑工艺形成密封剂168以仅密封基板140上的半导体芯片162和焊线156。因此，暴露出半导体芯片162和焊线156周围的一部分表面140a，而没有被密封剂168覆盖住。此外，在所述的实施例中，用于将第二基板140电连接到外电路板的多个接头180接合到第二基板140的表面140b上的暴露焊盘148。
至少一部分封装104插入到形成在第一基板120中的开口120h中。在基板140上密封半导体芯片162的密封剂168的宽度W2可以等于或小于形成在第一基板120中的开口120h的宽度W1。
上封装102和下封装104通过接头170彼此电连接，接头170在基板120的表面120b上的焊盘128与基板140的表面140a上的焊盘148之间连接。在图2所述的多堆叠封装100中，接头170显示为例如焊料球的金属凸点。
在可选的实施例中，依照设计选择，接头170和/或接头180可为弹性导体、线焊或另一电导体。
依照本发明的实施例，多堆叠封装100的总厚度T1可减少插入开口120h中的第二封装104部分的厚度，不用减小封装102和/或封装104的厚度。这就不需要在制造封装102和104时用于支撑较薄基板的分离载体框架，因此降低制造成本。这还省去了处理较薄基板的复杂工艺，由此简化了制造工艺。此外，可以在形成封装102和封装104时降低基板翘曲和次级共平面度(co-planarity inferiority)的可能性。另外，基板120和基板140之间的距离D1是小的。这使得基板120和140之间能使用小接头170，且由此减小接头170的间距，使得形成在基板有限面积内的互连图案的密度增大。另外当组装封装102与封装104时，形成在封装102中的开口120h作为接合向导以防止对准错误。
图3为依照本发明另一实施例的多堆叠封装200的横截面图。
除了下文的内容，图3所述的多堆叠封装200与图2所述的依照本发明实施例的多堆叠封装100基本相似。图3中，与图2相同的参考数字指示等价元件，且因此将不再重复对那些元件的详细描述。
对于依照本发明另一实施例的多堆叠封装200，封装202中，半导体芯片132通过粘合层222固定在基板120的表面120a上。粘合层222包括开口222h，其基本上对准基板120中的开口220h。半导体芯片132的一部分表面通过开口220h和开口222h暴露于半导体芯片162的密封剂168。
至少一部分封装204插入到开口220h和/或开口222h之中。这使得在基板120和基板140之间产生小的距离D2。
在图3所述的依照本发明实施例的多堆叠封装200中，基板120和基板140之间的距离D2可以小于图2所述的距离D1。结果，多堆叠封装200的总厚度T2可小于多堆叠封装100的总厚度T1。此外，基板120和基板140之间的接头270可以小于图2的接头170，且由此可以缩小的间距分隔，增大了形成在有限面积内的互连图案的密度。
在可选的实施例中，依照设计选择，接头270可以是焊料凸点、弹性导体、线焊或另一种电导体。
除了上文所述的特征，封装202和204分别具有与图2的封装102和104相同的结构。
图4为依照本发明又一实施例的多堆叠封装300的横截面图。
除了下文的内容，图4所述的多堆叠封装300与依照图2所述的实施例的多堆叠封装100在结构上基本相似。图4中，与图2相同的参考数字指示等价元件，且因此将不再重复对那些元件的详细描述。
依照本发明的此实施例，多堆叠封装300包括形成在封装102的开口120h中且嵌入封装102和封装104之间的封装间(inter-package)间隙填充物390。
封装间间隙填充物390沿着开口120h的至少一部分侧壁和封装102的下表面延伸。在图4所述的依照本发明实施例的多堆叠封装300中，封装间间隙填充物390连接粘合层122的下表面。
封装间间隙填充物390可以是例如环氧树脂膏或粘合材料膜。可选地，封装间间隙填充物390可以是或包括非粘合材料，例如热化合物(thermalcompound)。热化合物可以包括例如半导体、金属、金属氧化物和/或有机材料。特别地，热化合物可以包括例如硅(Si)、金(Au)、银(Ag)、铜(Cu)、氧化锌(ZnO2)和/或氧化银(AgO2)。可选地，封装间间隙填充物390可以是或包括例如具有导电填充物的环氧树脂，导电填充物可以例如是Ag、镍(Ni)、涂Au的Ni和铅(Pb)。可选地，封装间间隙填充物390可以是或包括非导电材料，例如包括二氧化硅(SiO2)、涂胶SiO2和/或橡胶的填充物。
在依照本发明此实施例的多堆叠封装300中，封装间间隙填充物390能够保护通过开口120h暴露的一部分封装102。此外，封装间间隙填充物390可增强封装102和104之间的接合，由此提高多堆叠封装300的可靠性。当封装间间隙填充物390由热化合物形成时，来自多堆叠封装300的热量通过封装间间隙填充物390辐射到外面，这提高了多堆叠封装300的热辐射特性，且进而提高了多堆叠封装300的可靠性。
图5为依照本发明又一实施例的多堆叠封装400的横截面图。
除了下文的内容，图5所述的多堆叠封装400与依照图3所述的实施例的多堆叠封装200在结构上基本相似。图5中，与图3相同的参考数字指示等价元件，且因此将不再重复对那些元件的详细描述。
依照本发明此实施例，多堆叠封装400包括形成在第一封装202的开口220h中且嵌入封装202和封装204之间的封装间间隙填充物490。由于封装间间隙填充物490与图4的封装间间隙填充物390相同，所以将省略对它的详细描述。然而，在图5所述的依照本发明实施例的多堆叠封装400中，封装间间隙填充物490沿着开口220h和222h的至少一部分侧壁以及通过开口220h和222h暴露的第一封装202的下表面延伸。在图5所述的依照本发明实施例的多堆叠封装400中，封装间间隙填充物490与半导体芯片132的下表面接触。
图6为说明依照本发明实施例的多堆叠封装的制造方法的流程图。
在工艺610中，第一半导体芯片装配在第一基板120的表面120a上以形成第一封装102或202。第一半导体芯片可以是具有如图2至5所述的两个堆叠的半导体芯片132和134的半导体芯片堆叠模块，或具有三个或更多顺序堆叠的半导体芯片。工艺610还包括在第二基板140的表面140a上装配第二半导体芯片162以形成第二封装104或204。
工艺610可以进一步包括引线键合和/或密封步骤。例如，形成第一封装102或202可以包括把焊线126和密封剂138添加到第一封装102或202中。同样地，形成第二封装104或204可以包括添加焊线156和密封剂168。
在工艺620中，从第二表面120b去除第一封装102或202的第一基板120的区域以在第一半导体芯片下形成沟槽。沟槽可以是图2和4的示例中的第一开口120h。在这种情况下，只能去除第一基板120的区域以形成第一开口120h作为穿透第一基板120的沟槽。
可选地，在工艺620中可以去除一部分第一基板120和然后还可以去除通过第一开口120h暴露的一部分第一粘合层222。在这种情况下，在工艺620中形成的沟槽是图3和5的示例中第一开口220h和第二开口222h的结合。
在工艺620的又一实施例中，还可以去除通过第一开口220h和第二开口222h暴露的半导体芯片132的下表面。例如，为了从半导体芯片132的下表面去除预定厚度，可以去除半导体芯片132的背面上的一部分体硅基板。
在工艺630中，在沟槽中形成封装间间隙填充物390或490。粘合材料膜可以粘附沟槽的内壁以达到形成封装间间隙填充物390或490的目的。可选地，在工艺630中非粘合材料可以干涂(dry-coated)在沟槽的内壁上。
在工艺640中，至少一部分第二封装104或204(例如，至少一部分密封剂168)插入沟槽中。在实行工艺640中，至少一部分密封剂168可以接触封装间间隙填充物390或490。
在工艺650中，第一基板120电连接第二基板140。特别地，例如与第一基板120的第二表面120b上焊盘128连接的金属凸点的接头170或270可以连接第二基板140的第三表面140a上焊盘148。接头170或270可以是例如包括铅(Pb)的焊料球。将第一封装102或202的接头170或270键合到第二封装104或204的焊盘的工艺可以在炉中约240℃的温度下实行。
可以改变图6所述的方法。例如，在一个可选实施例中，工艺630可以被完全省略以分别形成图2或3的MSP 100或200。此外，在又一可选实施例中，工艺630可在工艺640之后实行；在这种情况下，将封装间间隙填充物390或490注入到沟槽中和至少一部分密封剂168周围。
图7为说明依照本发明另一实施例的多堆叠封装制造方法的流程图。
工艺710中，在第一基板120的区域中形成第一开口120h或220h。
工艺720中，第一半导体芯片安装在第一基板120的第一表面120a上。在这种情况下，定位第一半导体芯片以覆盖至少一部分第一开口120h或220h。将省略对第一半导体芯片的详细描述，因为它与相关于图6工艺610的半导体芯片相同。第一粘合层122和第二粘合层124可以用于将第一半导体芯片贴装到第一基板120。工艺720还可包括添加焊线126和密封剂138。
参考图8和9描述利用安装台的工艺720的实施例。
图8为具有第一开口220h的第一基板120的横截面图，第一基板120位于安装台800上以达到在第一基板120上安装第一半导体芯片的目的。在所述实施例中，安装台800在其上表面上具有凸起802。凸起802可以具有等于或小于第一基板120中形成的第一开口220h的宽度W1的宽度W3。凸起802可以具有等于或小于第一基板120的高度H1的高度H2。如图8所示，在安装台800的凸起802插入第一开口220h中的状态下，第一半导体芯片可以安装在第一基板120上。
图9为安装在第一基板120上的半导体芯片132和134的横截面图，在安装台800的凸起802插入第一开口220h中的状态下，采用第一粘合层222和第二粘合层124将半导体芯片132和134安装在第一基板120上以形成第一封装202。
如图8和9所述，在具有第一开口220h的第一基板120安装到具有凸起802的安装台800上的状态下，半导体芯片132和134安装在第一基板120上，由此防止在制造第一封装202时第一基板120的翘曲，和有利于操作基板120。此外，为了形成第一封装202，较薄基板可以用作第一基板120。
回参考图7，在工艺730中，通过第一基板120的第一开口220h暴露的部分第一粘合层222被去除以形成穿透第一粘合层222的第二开口222h。由此，如图10所示，半导体芯片132的下表面通过第一开口220h和第二开口222h暴露。工艺730可选地包括从半导体芯片132的暴露的下表面去除预定的厚度。
工艺730还可包括将接头270添加到第一基板120的焊盘128。例如，形成第二开口222h之后，接头270可以与第一基板120的第二表面120b中的焊盘128耦合。可选地，在形成第二开口222h之前，接头270可以与第一基板120的第二表面120b中的焊盘128耦合。
在工艺740中，第二半导体芯片安装在第二基板140的第三表面140a上以形成第二封装104或204。第二半导体芯片可以是图2至5中所述的半导体芯片162。工艺740还可包括添加焊线156和密封剂168。
在工艺750中，封装间间隙填充物390或490形成在第一封装202的第一开口220h和第二开口222h中。由于形成封装间间隙填充物390或490的工艺与图6的工艺630相同，所以将省略对它的描述。依照设计选择，工艺750可以省略。
在工艺760中，至少一部分第二封装104或204(例如，至少一部分密封半导体芯片162的密封剂168)插入到第一开口220h和第二开口222h中。至少一部分密封剂168可以接触封装间间隙填充物390或490。
在工艺770中，如图6的工艺650中，第一基板120电连接第二基板140。
可以改变图7中所述的方法。例如，在一个可选实施例中，在步骤760之后实行步骤750；在这种情况下，步骤750包括注入间隙填充物390或490到沟槽中和至少一部分密封剂168周围。
在图7所述的另一可选实施例中，步骤720包括选择性的使用第一粘合层222使得第一开口220h不暴露粘合物。在这种情况下，不需要步骤730，因为通过选择性的使用第一粘合层222形成第二开口222h。
在依照本发明的多堆叠封装中，一部分第二下封装插入形成在第一上封装下的沟槽或开口中。在不必减小彼此接合的第一封装和第二封装的厚度情况下可减小依照本发明的多堆叠封装的总厚度。这就不需要在制造第一和第二封装时用于支撑较薄基板的分离载体框架，因此降低制造成本，和简化制造工艺。此外，当第一封装对准且接合第二封装时，形成在第一封装中的沟槽或开口作为接合向导以防止封装之间的对准错误。随着第一基板和第二基板之间的距离变小，电连接基板所需的接头的尺寸可以减小，可使用更小的接头间距和增大形成在基板的有限面积内的互连图案的密度。因此，本发明可用于高度集成的高性能集成电路。
虽然参考其示范性实施例具体显示和描述了本发明，然而本领域的一般技术人员可以理解在不脱离由权利要求所界定的本发明的精神和范围的情况下，可以做出形式和细节上的不同变化。例如，当单个特征被描述为可选的情况，发明应理解为包括被要求保护的特征的组合，而没有特别显示或说明这种组合。
本申请要求于2006年11月9日向韩国专利局提交的韩国专利申请第10-2006-0110538号的权益，在这里并入其公开的全文作参考。

Claims (20)

1.一种多堆叠封装，包括：
第一封装，包括第一基板和第一半导体芯片，所述第一半导体芯片利用第一粘合层安装到所述第一基板，该第一基板具有第一开口，该第一开口关于所述第一半导体芯片在垂直方向上基本对准；和
第二封装，与第一封装耦合，该第二封装包括第二基板和第二半导体芯片，该第二半导体芯片利用第二粘合层安装到所述第二基板，所述第二半导体芯片关于所述第一开口在所述垂直方向上基板对准，至少一部分所述第二封装延伸到由所述第一开口限定的空间中使得所述多堆叠封装的高度小于与所述第一封装和所述第二封装有关的高度之和。
2.权利要求1所述的多堆叠封装，其中所述第二半导体芯片由密封剂密封住，和其中至少一部分密封剂延伸到由所述第一开口限定的所述空间中。
3.权利要求1所述的多堆叠封装，其中封装间间隙填充物存在于至少一部分由所述第一开口限定的所述空间中。
4.权利要求3所述的多堆叠封装，其中所述封装间间隙填充物是粘合材料。
5.权利要求3所述的多堆叠封装，其中所述封装间间隙填充物是非粘合材料。
6.权利要求3所述的多堆叠封装，其中所述封装间间隙填充物是热化合物。
7.权利要求3所述的多堆叠封装，其中所述封装间间隙填充物是导电材料。
8.权利要求1所述的多堆叠封装，其中所述第一粘合层包括第二开口，该第二开口关于所述第一开口在所述垂直方向上基本对准。
9.权利要求8所述的多堆叠封装，其中封装间间隙填充物存在于至少一部分由所述第一开口限定的所述空间中，和其中所述封装间间隙填充物还存在于至少一部分由所述第二开口限定的空间中。
10.权利要求1所述的多堆叠封装，其中所述第一封装包括第三半导体芯片，该第三半导体芯片关于所述第一半导体芯片在所述垂直方向上基本对准，该第三半导体芯片通过第三粘合层安装到所述第一半导体芯片。
11.一种多堆叠封装的制造方法，所述方法包括：
在第一基板上安装第一半导体芯片，安装第一半导体芯片包括施加第一粘合层到所述第一基板；
在第二基板上安装第二半导体芯片；
密封所述第二半导体芯片以形成密封的第二半导体芯片；
去除一部分所述第一基板以产生第一开口，该第一开口关于所述第一半导体芯片在垂直方向上基本对准；和
将至少一部分所述密封的第二半导体芯片插入到所述第一开口中。
12.权利要求11的方法，还包括在所述第一半导体芯片上安装第三半导体芯片，该第三半导体芯片关于所述第一半导体芯片在所述垂直方向上基本对准。
13.权利要求11的方法，还包括在去除一部分第一基板之后以及插入至少一部分所述密封的第二半导体芯片之前施加封装间间隙填充物到至少一部分所述第一开口中。
14.权利要求11的方法，还包括在去除一部分第一基板之后以及插入至少一部分所述密封的第二半导体芯片之前去除由所述第一开口暴露的一部分所述第一粘合层。
15.权利要求11的方法，还包括在插入至少一部分所述密封的第二半导体芯片之后将封装间间隙填充物注入到至少一部分所述第一开口中。
16.一种多堆叠封装的制造方法，所述方法包括：
去除一部分第一基板以产生第一开口；
在所述第一基板上安装第一半导体芯片，该第一半导体芯片关于所述第一开口在垂直方向上基本对准，安装第一半导体芯片包括施加第一粘合层到所述第一基板；
在第二基板上安装第二半导体芯片；
密封所述第二半导体芯片以形成密封的第二半导体芯片；和
将至少一部分所述密封的第二半导体芯片插入到所述第一开口中。
17.权利要求16的方法，还包括在所述第一半导体芯片上安装第三半导体芯片，该第三半导体芯片关于所述第一半导体芯片在所述垂直方向上基本对准。
18.权利要求16的方法，还包括在插入至少一部分所述密封的第二半导体芯片之前施加封装间间隙填充物到至少一部分所述第一开口中。
19.权利要求16的方法，还包括在插入至少一部分所述密封的第二半导体芯片之后施加封装间间隙填充物到至少一部分所述第一开口中。
20.权利要求16的方法，其中施加第一粘合层是有选择性的，使得该第一粘合层不延伸到所述第一开口中。
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CN102254835A (zh) * 2010-05-17 2011-11-23 新科金朋有限公司 半导体器件及其制造方法
CN103779289A (zh) * 2012-10-18 2014-05-07 富葵精密组件(深圳)有限公司 连接基板及层叠封装结构
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CN104769712B (zh) * 2013-01-28 2018-07-13 晟碟信息科技（上海）有限公司 包括嵌入式控制器裸芯的半导体器件和其制造方法
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