CN104769712A - 包括嵌入式控制器裸芯的半导体器件和其制造方法 - Google Patents

包括嵌入式控制器裸芯的半导体器件和其制造方法 Download PDF

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Publication number
CN104769712A
CN104769712A CN201380052380.7A CN201380052380A CN104769712A CN 104769712 A CN104769712 A CN 104769712A CN 201380052380 A CN201380052380 A CN 201380052380A CN 104769712 A CN104769712 A CN 104769712A
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bare chip
substrate
semiconductor bare
cavity
semiconductor device
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CN201380052380.7A
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CN104769712B (zh
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S.库马尔
邱进添
钱开友
俞志明
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SanDisk Information Technology Shanghai Co Ltd
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SanDisk Information Technology Shanghai Co Ltd
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Abstract

一种半导体器件，包括基板(102)，其具有其中形成以用于接收半导体裸芯的腔体(112)。在各例子中，半导体裸芯是控制器裸芯(114)。可以用电迹线(120)来将控制器裸芯(114)连接到基板(102)，该电迹线(120)可以通过例如印刷来形成。在控制器裸芯(114)电连接到基板(102)之后，可以在腔体(112)和控制器裸芯(114)上方将一个或多个存储器裸芯(150)附着到基板(102)。

Description

包括嵌入式控制器裸芯的半导体器件和其制造方法
背景技术
便携式消费电子产品的强劲增长需要促进了对高容量存储装置的需求。诸如闪存存储卡的非易失性半导体存储器装置正变得越来越广泛用于满足对数字信息存储和交换的日益增长的需要。它们的便携性、多用些和稳定的设计、以及其高可靠性和大容量已经使得这种存储器器件理想地用于各种电子设备，包括例如，数码相机、数字音乐播放器、视频游戏机、PDA和蜂窝电话。
虽然已知了多种封装体配置，但是通常闪存存储卡可以制造为系统级封装体(SiP)或多芯片模块(MCM)，其中，在小足印基板上安装和互连多个裸芯。该基板通常可以包括刚性的介电基底，其具有在一面或两面上蚀刻的导电层。在裸芯和(一个或多个)导电层之间形成电连接，且(一个或多个)导电层提供用于将裸芯连接到主机设备的电引线结构。一旦完成了在裸芯和基板之间的电连接，则通常该装配件被包封在提供保护性包装的模塑化合物内。
图1和图2中示出了传统半导体封装体20的剖面侧视图和俯视图(在图2中没有示出模塑化合物)。典型的封装体包括附着到基板26的多个半导体裸芯，诸如闪存裸芯22和控制器裸芯24。在裸芯制造工艺期间，可以在半导体裸芯22、24上形成多个裸芯键合垫28。类似地，可以在基板26上形成多个接触垫30。裸芯22可以被附着在基板26上，然后裸芯24可以被安装在裸芯22上。然后，可以通过在相应的裸芯键合垫28和接触垫30对之间附着引线键合体32来将所有裸芯电耦合到基板。一旦完成了所有电连接，则可以在模塑化合物34中包封这些裸芯和引线键合体，以密封该封装体并保护这些裸芯和引线键合体。
为了最高效地使用封装体足印，已知上下堆叠半导体裸芯，无论是完全彼此重叠还是带有偏移地重叠，如图1和2所示。在偏移配置中，一个裸芯被堆叠在另一裸芯的顶上使得下方裸芯的键合垫被暴露。偏移配置提供方便地接近在堆叠中的每个半导体裸芯上的键合垫的优点。虽然在图1中的堆叠中示出了两个半导体裸芯，但是已知在堆叠中提供更多存储器裸芯，诸如例如四个或八个半导体裸芯。
为了增加半导体封装体中的存储器容量、同时维持或减少该封装体的总体尺寸，存储器裸芯的尺寸相比于封装体的总体尺寸已经变大。如此，存储器裸芯的足印通常几乎与基板的足印一样大。
控制器裸芯24通常小于半导体裸芯22。因此，控制器裸芯24被传统地置于半导体裸芯堆叠的顶上。该配置具有某些缺点。例如，难以形成从控制器裸芯上的裸芯键合垫向下到基板的大量引线键合体。已知在控制器裸芯下方提供插入体或重分配层，使得形成从控制器裸芯到插入体的引线键合体，且然后从插入体向下到基板的引线键合体。另外，从控制器裸芯到基板的引线键合体的相对长的长度减慢了半导体器件的操作。已知将控制器裸芯直接安装到基板的顶上，但是这则呈现了难以将更大存储器裸芯安装到控制器裸芯的顶上。
附图说明
图1是传统半导体封装体的剖面侧视图。
图2是传统基板和引线键合的半导体裸芯的俯视图。
图3是根据本发明的实施例的半导体器件的整体制造工艺的流程图。
图4是在制造工艺中在一个步骤的根据本技术的半导体器件的透视图。
图5是在制造工艺中在另一个步骤的根据本技术的半导体器件的透视图。
图6是在制造工艺中在另一个步骤的根据本技术的半导体器件的透视图。
图7是示出根据本公开的实施例的步骤209的另外的细节的流程图。
图8是在制造工艺中在另一个步骤的根据本技术的半导体器件的透视图。
图9是在制造工艺中在另一个步骤的根据本技术的半导体器件的透视图。
图10是根据本技术的一个可选实施例的半导体器件的透视图。
图11是在制造工艺中在另一个步骤的根据该可选实施例的半导体器件的透视图。
图12是在制造工艺中在另一个步骤的根据图9的实施例的半导体器件的透视图。
图13和14是根据图11所示的可选实施例的半导体器件的透视图。
图15和16是根据图11所示的另一可选实施例的半导体器件的透视图。
图17是在制造工艺中在另一个步骤的根据图12-16的任一实施例的半导体器件的透视图。
图18是在制造工艺中在另一个步骤的根据图17的半导体器件的透视图。
图19是在制造工艺中在另一个步骤的根据图18的半导体器件的透视图。
具体实施方式
以下将参考图3到19来描述本技术，本技术在实施例中涉及包括基板的表面内安装的控制器裸芯的半导体器件。要理解，本发明可以按许多不同的形式来实施，且不应该被限制为在此阐述的实施例。而是，提供这些实施例以便本公开将充分和完整，且充分地向本领域技术人员传达该发明。确实，本发明旨在覆盖这些实施例的替换、修改和等同物，这些都被包括在由所附权利要求所限定的本发明的范围和精神中。另外，在本发明的以下详细描述中，阐述大量具体细节以便提供对本发明的全面了解。但是，本领域技术人员将清楚，可以不用这种具体细节来实践本发明。
在此可能使用的术语“顶部”和“底部”、“上方”和“下方”和“垂直”和“水平”仅用于举例和图示目的，且不旨在限制本发明的描述，所引用的项目可以在位置和方向上交换。而且，如在此使用的，对于给定的应用，术语“基本上”、“近似”和/或“大约”意味着所指定的尺度或参数可以在可接受的制造容许量内变换。在一个实施例中，该可接受制造容许量为±0.25％。
将参考图3的流程图和图4到19的透视图和侧视图来说明本发明的实施例。虽然图4到19每个示出了单个器件100、或其一部分，但是要理解，该器件100可以与基板面板上的多个其他封装体100一起被批处理，以实现规模经济。基板面板上的封装体100的行和列的数量可以改变。
基板面板以多个基板102开始(再次，在图4到19中示出一个这样的基板)。基板102可以是各种不同的芯片承载介质，其包括印刷电路板(PCB)、引线框架或带自动键合(TAB)带。在基板102是PCB的情况下，基板可以由具有顶部导电层105和底部导电层107的核心103形成，如图4所示。核心103可以由诸如例如聚酰亚胺薄片、包括FR4和FR5的环氧树脂、双马来酰亚胺-三嗪(BT)等的各种介电材料形成。虽然不是本发明所必要的，但是该核心可以具有在40微米(μm)到200μm之间的厚度，虽然在替换实施例中该核心的厚度可以在该范围之外变化。在可选实施例中，该核心103可以是陶瓷或有机的。
围绕核心的导电层105、107可以由铜或铜合金、镀铜或镀铜合金、合金42(42Fe/58Ni)、镀铜钢或已知用于在基板面板上使用的其他金属和材料形成。导电层可以具有大约12μm到18μm的厚度，尽管在可选实施例中这些层的厚度可以在该范围之外变化。
图3是形成根据本发明的实施例的半导体器件的制造工艺的流程图。在步骤200中，基板102被钻孔以在基板102上定义贯通通孔104。所示的通孔104(在图中仅编号了一些通孔)仅是示例，且基板可以包括比图中示出的多得多的通孔104，且它们可以处于与图中示出的位置不同的位置。接下来在步骤202中，通过选择性地移除顶部和底部导电层的一个或两者的部分来形成导电图案。可以例如通过已知光刻蚀刻工艺来进行导电层的移除。
留下的导电层的部分在基板102的上表面和/或下表面上形成导电图案，如图5所示。导电图案可以包括电迹线106和接触垫108。迹线106和接触垫108(在图中仅编号了一些)仅是示例，且基板102可以包括比图中示出的更多迹线和/或接触垫，且它们可以处于与图中示出的位置不同的位置。
再次参考图3，然后，可以在步骤204中，在自动光学检查(AOI)中检查基板102。一旦被检查了，在步骤206中且如图6所示，可以向基板施加焊接掩膜110。如已知的，接触垫和触指可以通过焊接掩膜中的开口而被暴露。在施加了焊接掩膜之后，在步骤208中，在已知电镀或薄膜沉积工艺中，导电图案上的接触垫、触指、和任何其他焊接区域可以被镀上Ni/Au、合金42等。
根据本技术的实施例，在步骤209中，可以在向下形成到基板102的表面内的腔体中安装控制器裸芯。现在参考图7的流程图来说明步骤209的进一步的细节。在步骤240中，可以在基板102的表面中形成腔体112，例如如图8所示。在图8所示的例子中，形成向下通过上焊接掩膜层110的腔体112，使得介电层103的上表面暴露在腔体112的底部处。因此，腔体112可以具有焊接掩膜层110和上导电层105组合后的深度(如上所述，层105的部分还可以被移除以形成导电图案)。注意，上导电层105的深度可以是12μm到18μm，且任何焊接掩膜层110可以具有25μm±10μm的厚度，尽管要理解，在其他实施例中，该上导电层和/或焊接掩膜层可以具有比这更大或更小的厚度。
在以下描述的其他实施例中，可替换地形成通过上焊接掩膜层并向下到介电层103中的腔体112。而且，可设想基板由插在导电铜层之间的若干介电层103形成，所有层均夹在上表面和下表面上的焊接掩膜层之间。在这种实施例中，腔体112可以被形成为通过上焊接掩膜层，然后向下通过一个或多个导电和/或介电层。在在此描述的实施例中，腔体112被形成在基板102的上表面上(基板102接收存储器裸芯的表面，如之后描述的)。但是，在可选实施例中，腔体112可以被形成在基板102的下表面中，且控制器裸芯可以被安装在该下表面上的腔体112中。
在各实施例中，腔体112具有与要在其中落座的控制器裸芯相同的足印或比其中落座的控制器裸芯略大的足印。腔体112的深度可以与控制器裸芯的厚度相同，或大于控制器裸芯的厚度。可以通过各种方法、包括例如蚀刻、激光的使用、或这些方法的组合来形成该腔体112。
在步骤242中，控制器裸芯114可以被安装在腔体112内，如图9所示。控制裸芯114可以例如是ASIC，尽管可设想其他半导体裸芯、诸如DRAM。如上所述，腔体112可以仅比焊接掩膜层110深。例如，如图10和11所示，腔体112被形成为通过该焊接掩膜层110，且部分地进入介电层103。这种实施例可能对更厚的裸芯114有用，诸如图11所示，使得裸芯114的上表面位于焊接掩膜层110的上表面处，或低于焊接掩膜层110的上表面。虽然在本技术的各实施例中腔体112内的裸芯114的上表面位于焊接掩膜层110的上表面处或低于焊接掩膜层110的上表面，但是要理解，在其他实施例中，腔体112内的裸芯114的上表面可以高于焊接掩膜110的上表面。
在步骤246中，对于在腔体112中的控制器裸芯114的边缘周围可能存在空间的情形，那些空间可以被填充介电材料116。该介电材料可以是例如B阶段粘合剂，其例子包括来自在日本具有总部的Nitto-Denko公司的EM-710H-P，以及来自Henkel AG&Co.KGaA的6202C环氧树脂。在这些例子中，介电材料116电绝缘控制器裸芯114，且还将裸芯114固定到基板102。在其他实施例中，可以使用分离的裸芯粘附粘合剂来将控制器裸芯114安装在腔体112中，然后控制器裸芯114的边缘周围的任何空间可以被填充介电材料116。在该后者的例子中，介电材料116不一定是粘合剂。在其他实施例中，介电材料116可以在裸芯114之前被放置在腔体112中，使得介电材料116环绕裸芯114的底部表面和侧面。
控制器裸芯114包括裸芯键合垫118，该裸芯键合垫118之一在图9中被示例地标出。在步骤250中，可以对裸芯键合垫118进行视觉和/或自动检查，以确定介电材料116或其他污染物中的任何一个是否已经被沉积在裸芯键合垫118上，这可能干扰控制器裸芯114到基板102的电连接，如以下说明的。如果发现这种污染物，则在步骤252中可以移除该污染物。作为一个例子，可以使用激光来烧掉或汽化裸芯键合垫118上的任何污染物。
在移除了污染物之后，或在回填了介电材料116之后，如果没有发现污染物，则可以在控制器裸芯114上的裸芯键合垫118和基板102上的接触垫108之间形成导电迹线120。在图12中标出了一个导电迹线120。
这些导电迹线120可以通过各种方法来形成。在一个实施例中，这些迹线可以被印刷在基板和控制器裸芯上的接触垫108和裸芯键合垫118之间的空间上，以将相应的垫108电连接到垫118上。例如，如图12所示，可以提供一个或多个印刷头122作为喷雾剂(或其他)印刷工艺的一部分，以在垫108和118之间印刷电导电迹线120。这种印刷工艺是已知的，例如来自营业地在比利时的Liege的Sirris。迹线120可以例如是电导体，其包括铜、银、金、钯、其组合和/或其他电导体。迹线120可以可选地是导电聚合物PEDOT:PSS(聚(3,4-乙烯二氧噻吩)-聚苯乙烯磺酸)或CNT(碳纳米管)材料。
印刷头122可以通过各种技术来沉积电迹线120，所述技术包括例如连续和/或按需喷射(DOD)印刷。可以使用印刷头122等各种其他技术来沉积迹线120，所述技术包括例如镀、丝网印刷和薄膜沉积来由印刷头122等。根据上述技术印刷的电迹线120可以被印刷得具有精细的间距，诸如例如10μm行宽，以及迹线120之间的20μm间隔。在其他实施例中，可设想其他行宽和间隔。
在其他实施例中，通过各种其他技术来形成电迹线120。例如，如图13和14所示，迹线120可以被预印刷在柔性膜124上。该膜124可以例如是来自在R.O.C的台湾的高雄具有营业地的WUS印刷电路有限公司的印刷电路带。这种膜可以包括在该膜124上印刷、沉积或另外形成的导电迹线120。该膜可以包括ETFE(亚乙基四氟乙烯)背胶层(backing layer)、粘合层、和在背胶层和粘合层之间的脱模剂。可以在粘合层中或在粘合层上提供电迹线的图案。
脱模剂可以是在室温下是固体的，且具有附着性以与背胶层粘合。膜124可以置于基板和控制器裸芯上(从图13所示的位置翻转)，使得电迹线120被适当放置以便在相应的接触垫和键合垫108、118之间延伸。膜124可以在压力下被加热，此时，脱模剂融化，将粘合层和导电迹线120从背胶层分离。粘合层可以被固化以将电迹线附着在基板102和控制器裸芯114上的合适位置，如图14所示。在申请人共同未决的国际专利申请No.PCT/CN2011/084137中公开了该膜124的成分和应用的其他细节，该申请整体被引用并于此。
图15和16中示出了在垫108和118之间通过“无线环”引线键合体形成电迹线120的另一方法。在该实施例中，可以使用引线键合劈刀(未示出)来将球键合体130(其中两个球键合体在图15中被标出)沉积在控制器裸芯114的裸芯键合垫118上。然后，该劈刀可以通过在接触垫108上沉积球132(图16)并将该引线键合从该球132延伸到该球键合体130来形成反向引线键合体。该引线键合体可以被称为“无线环”，因为该引线可以在该球132和该球键合体130之间被拉紧。要理解，在其他实施例中该球键合体130和球132的各自的位置可以交换。还要理解，在其他实施例中，可以使用其他低高度引线键合方法来将接触垫108与裸芯键合垫118电耦合。
现在返回参考图3的流程图，在步骤209中将控制器裸芯114安装在腔体112中之后，可以在自动检查工艺(步骤210)中和在最终视觉检查(步骤212)中检查和测试基板102，以查验电操作以及污染物、划痕和变色。要理解，自动检查和/或视觉检查也可以作为步骤209中将控制器裸芯114安装在腔体112中的一部分来进行。
接下来，在步骤214中，可以将无源组件134附着到基板，例如附着在焊接掩膜110层中的开口136中。一个或多个无源组件134可以包括例如一个或多个电容器、电阻器和/或电感器，尽管还可设想其他组件。示出的无源组件134仅是示例，且在其他实施例中，数量、类型和位置可以改变。
接下来，在步骤220中，如图17-19所示，可以将一个或多个存储器裸芯150安装到基板102。存储器裸芯150可以例如是NAND闪存裸芯，但在其他实施例中在步骤220中可以将其他类型的裸芯150安装到基板。图17-19示出安装2个裸芯150的实施例，但在其他实施例中可以有更多或更少的存储器裸芯130。根据本技术的各方面，存储器裸芯150可以在存储器裸芯114上方，平躺抵靠焊接掩膜层110的上表面。
在各实施例中，在每个裸芯150被置于基板102上之后在步骤224中使用引线键合体152将每个裸芯150引线键合到基板102，如图18的侧视图中所示。在其他实施例中，所有裸芯可以置于基板上，且然后，所有裸芯可以被引线键合到基板。
在安装裸芯堆叠和引线键合之后，在步骤226中且如图19所示，裸芯堆叠、引线键合体和基板的至少一部分可以被包封在模塑化合物160中。模塑化合物160可以包括例如固态环氧树脂、酚醛树脂、熔融石英、结晶石英、碳黑和/或金属羟化物。这种模塑化合物可从例如在日本都有总部的Sumitomo公司和Nitto-Denko公司得到。可设想来自其他制造商的其他模塑化合物。可以根据各种已知工艺来施加模塑化合物，所述工艺包括通过转移模塑或注射模塑技术。在其他实施例中，可以通过FFT(薄自由流动(Flow Free Thin))压缩模塑来进行包封工艺。这种FFT压缩模塑工艺是已知的，且在例如日本、东京的Towa公司的Matsutani,H.的2009年的Microelectronics and PackagingConference杂志的题为“Compression Molding Solutions For Various High EndPackage And Cost Savings For Standard Package Applications”的公开物中描述，该公开物整体被引用并于此。
在各实施例中，可以将成品半导体器件110用作球栅阵列(BGA)封装体，其被永久地焊接到主机设备的印刷电路板。对于这种实施例，在图19所示的步骤中，焊料球162可以被焊接到基板102的下表面。在其他实施例中，成品半导体器件100可以是焊盘栅阵列(LGA)封装体,其包括在主机设备内可移除地耦合成品器件100的触指的。在这种实施例中，可以跳过步骤226，且下表面可以包括触指，而不是接收焊料球的接触垫。
在步骤230中可以从面板上单片化各个封装体，以形成图18所示的成品半导体器件100。通过各种切割方法的任一种来单片化每个半导体器件100，所述切割方法包括锯割、水流切割、激光切割、水引导激光切割、干介质切割和金刚石涂覆线切割。虽然直线切割将通常限定矩形或正方形的半导体器件100，但是要理解，在本发明的其他实施例中，半导体器件100可以具有与矩形和正方形不同的形状。
一旦切割为封装体100，可以在步骤232中测试这些封装体，以确定这些封装体是否适当地运作。如在现有技术中已知，这种测试可以包括电测试、写入(burn in)和其他测试。可选地，在步骤234中，在例如半导体器件是LGA封装体的情况下，成品半导体器件可以被包裹在盖帽(未示出)内。
成品半导体封装体100可以例如是存储卡，诸如例如MMC卡、SD卡、多用途卡、微SD卡、存储棒、紧凑SD卡、ID卡、PCMCIA卡、SSD卡、芯片卡、智能卡、USB卡、MCP类嵌入式卡存储器等。
总之，在一个例子中，本技术涉及一种半导体器件，包括：基板，包括介电层和在所述介电层上的导电层，所述导电层包括导电图案，所述导电图案包括电迹线和接触垫；在所述导电层上方形成的焊接掩膜层；在所述基板中形成的腔体，其向下到所述腔体的底部处的所述介电层；在所述腔体中安装的第一半导体裸芯，其在所述介电层上电隔离，所述第一半导体裸芯包括裸芯键合垫；在所述基板的接触垫和所述第一半导体裸芯的裸芯键合垫之间形成的电迹线，以将所述第一半导体裸芯电连接到所述基板；以及在所述基板上安装的第二半导体裸芯，至少覆盖所述腔体中的包括所述第一半导体裸芯的一部分。
在另一个例子中，本技术涉及一种半导体器件，包括：包括接触垫的基板；在所述基板中形成的腔体；在所述腔体中安装的第一半导体裸芯，所述第一半导体裸芯包括裸芯键合垫；在所述基板的接触垫和所述第一半导体裸芯的裸芯键合垫之间形成的印刷电迹线，以将所述第一半导体裸芯电连接到所述基板；以及在所述基板上安装的第二半导体裸芯，至少覆盖所述腔体中的包括所述第一半导体裸芯的一部分。
在另一个例子中，本技术涉及一种半导体器件，包括：包括接触垫的基板；在所述基板中形成的腔体；在所述腔体中安装的第一半导体裸芯，所述第一半导体裸芯包括裸芯键合垫；电迹线和来自柔性膜的粘合剂，所述电迹线被施加在所述基板的接触垫和所述第一半导体裸芯的裸芯键合垫之间，以将所述第一半导体裸芯电连接到所述基板；以及在所述基板上安装的第二半导体裸芯，至少覆盖所述腔体中的包括所述第一半导体裸芯的一部分。
在另一个例子中，本技术涉及一种制造半导体器件的方法，包括：(a)形成基板，所述基板包括介电层和在所述介电层上的导电层，所述导电层包括导电图案，所述导电图案包括电迹线和接触垫；(b)在所述导电层上方形成焊接掩膜层；(c)在所述基板中形成腔体，其向下到所述腔体的底部处的所述介电层；(d)在所述腔体中安装第一半导体裸芯，其在所述介电层上电隔离，所述第一半导体裸芯包括裸芯键合垫；(e)在所述基板的接触垫和所述第一半导体裸芯的裸芯键合垫之间印刷电迹线，以将所述第一半导体裸芯电连接到所述基板；以及(f)在所述基板上安装第二半导体裸芯，至少覆盖所述腔体中的包括所述第一半导体裸芯的一部分。
已经为了图示和描述的目的呈现了本发明的前述描述。不旨在穷举或限制本发明到公开的精确形式。在上述教导下，许多修改和变化是可能的。选择上述实施例以便最佳地说明本发明的原理及其实际应用，由此使得本领域技术人员能够最佳地在各种实施例中使用本发明，且设想适用于实际使用的各种修改。旨在本发明的范围由所附的权利要求来限定。

Claims (24)

1.一种半导体器件，包括：
基板，包括介电层和在所述介电层上的导电层，所述导电层包括导电图案，所述导电图案包括电迹线和接触垫；
在所述导电层上方形成的焊接掩膜层；
在所述基板中形成的腔体，其向下到所述腔体的底部处的所述介电层；
在所述腔体中安装的第一半导体裸芯，其在所述介电层上电隔离，所述第一半导体裸芯包括裸芯键合垫；
在所述基板的接触垫和所述第一半导体裸芯的裸芯键合垫之间形成的电迹线，以将所述第一半导体裸芯电连接到所述基板；以及
在所述基板上安装的第二半导体裸芯，至少覆盖所述腔体中的包括所述第一半导体裸芯的一部分。
2.根据权利要求1所述的半导体器件，还包括填充在所述腔体中在所述第一半导体裸芯的边缘周围的空间的介电材料。
3.根据权利要求1所述的半导体器件，其中，所述第一半导体裸芯是控制器裸芯。
4.根据权利要求1所述的半导体器件，其中，所述第二半导体裸芯是存储器裸芯。
5.根据权利要求1所述的半导体器件，其中，所述腔体的深度基本上等于所述第一半导体裸芯的厚度。
6.根据权利要求1所述的半导体器件，其中，所述腔体的深度大于所述第一半导体裸芯的厚度。
7.一种半导体器件，包括：
包括接触垫的基板；
在所述基板中形成的腔体；
在所述腔体中安装的第一半导体裸芯，所述第一半导体裸芯包括裸芯键合垫；
在所述基板的接触垫和所述第一半导体裸芯的裸芯键合垫之间形成的印刷电迹线，以将所述第一半导体裸芯电连接到所述基板；以及
在所述基板上安装的第二半导体裸芯，至少覆盖所述腔体中的包括所述第一半导体裸芯的一部分。
8.根据权利要求7所述的半导体器件，还包括填充在所述腔体中在所述第一半导体裸芯的边缘周围的空间的介电材料。
9.根据权利要求7所述的半导体器件，其中，所述基板还包括焊接掩膜层，其中，所述腔体被所述焊接掩膜中的开口限定。
10.根据权利要求9所述的半导体器件，其中，所述焊接掩膜中的开口具有与所述第一半导体裸芯的足印基本相同的形状。
11.根据权利要求7所述的半导体器件，其中，所述基板还包括在介电层上的导电材料的层，其中，所述腔体由电导电材料在一个区域内的缺失来限定。
12.根据权利要求7所述的半导体器件，其中，所述腔体的深度基本上等于所述第一半导体裸芯的厚度。
13.根据权利要求7所述的半导体器件，其中，所述腔体的深度大于所述第一半导体裸芯的厚度。
14.一种半导体器件，包括：
包括接触垫的基板；
在所述基板中形成的腔体；
在所述腔体中安装的第一半导体裸芯，所述第一半导体裸芯包括裸芯键合垫；
电迹线和来自柔性膜的粘合剂，所述电迹线被施加在所述基板的接触垫和所述第一半导体裸芯的裸芯键合垫之间，以将所述第一半导体裸芯电连接到所述基板；以及
在所述基板上安装的第二半导体裸芯，至少覆盖所述腔体中的包括所述第一半导体裸芯的一部分。
15.根据权利要求14所述的半导体器件，还包括填充在所述腔体中在所述第一半导体裸芯的边缘周围的空间的介电材料。
16.根据权利要求14所述的半导体器件，其中，所述基板还包括焊接掩膜层，其中，所述腔体被所述焊接掩膜中的开口限定。
17.根据权利要求14所述的半导体器件，其中，所述基板还包括在介电层上的导电材料的层，其中，所述腔体由电导电材料在一个区域内的缺失来限定。
18.根据权利要求14所述的半导体器件，其中，所述腔体的深度基本上等于所述第一半导体裸芯的厚度。
19.根据权利要求14所述的半导体器件，其中，所述腔体的深度大于所述第一半导体裸芯的厚度。
20.根据权利要求14所述的半导体器件，其中，所述第一半导体裸芯是控制器裸芯。
21.根据权利要求20所述的半导体器件，其中，所述第二半导体裸芯是存储器裸芯。
22.一种制造半导体器件的方法，包括：
形成基板，所述基板包括介电层和在所述介电层上的导电层，所述导电层包括导电图案，所述导电图案包括电迹线和接触垫；
在所述导电层上方形成焊接掩膜层；
在所述基板中形成腔体，其向下到所述腔体的底部处的所述介电层；
在所述空腔中安装第一半导体裸芯，其在所述介电层上电隔离，所述第一半导体裸芯包括裸芯键合垫；
在所述基板的接触垫和所述第一半导体裸芯的裸芯键合垫之间印刷电迹线，以将所述第一半导体裸芯电连接到所述基板；以及
在所述基板上安装第二半导体裸芯，其至少覆盖所述腔体中的包括所述第一半导体裸芯的一部分。
23.根据权利要求22的方法，还包括步骤(g)，用介电材料填充在所述第一半导体裸芯的边缘和腔体之间的空间。
24.根据权利要求23的方法，还包括步骤(h)，在所述步骤(g)之后用激光将介电材料或污染物从所述裸芯键合垫移除。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113169183A (zh) * 2019-01-23 2021-07-23 桑迪士克科技有限责任公司 包含接合到支撑管芯的两侧的存储器管芯的三维半导体芯片及其制造方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9627367B2 (en) 2014-11-21 2017-04-18 Micron Technology, Inc. Memory devices with controllers under memory packages and associated systems and methods
KR102420148B1 (ko) * 2016-03-22 2022-07-13 에스케이하이닉스 주식회사 반도체 패키지
US11355427B2 (en) * 2016-07-01 2022-06-07 Intel Corporation Device, method and system for providing recessed interconnect structures of a substrate

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050224944A1 (en) * 2004-04-13 2005-10-13 Stack Devices Corp. Stacked semiconductor device
CN101179068A (zh) * 2006-11-09 2008-05-14 三星电子株式会社 多堆叠封装及其制造方法
CN101872757A (zh) * 2009-04-24 2010-10-27 南茂科技股份有限公司 凹穴芯片封装结构及使用其的层叠封装结构
CN102640283A (zh) * 2009-12-29 2012-08-15 英特尔公司 具有嵌入式管芯的半导体封装及其制造方法
CN202434509U (zh) * 2012-01-18 2012-09-12 刘胜 堆叠式半导体芯片封装结构

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW327247B (en) * 1996-05-31 1998-02-21 Ibm Ball grid array having no through holes or via interconnections
TWI229434B (en) * 2003-08-25 2005-03-11 Advanced Semiconductor Eng Flip chip stacked package
KR100875955B1 (ko) * 2007-01-25 2008-12-26 삼성전자주식회사 스택 패키지 및 그의 제조 방법
US20080217761A1 (en) * 2007-03-08 2008-09-11 Advanced Chip Engineering Technology Inc. Structure of semiconductor device package and method of the same
US8237257B2 (en) 2008-09-25 2012-08-07 King Dragon International Inc. Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same
US8125063B2 (en) * 2010-03-08 2012-02-28 Powertech Technology, Inc. COL package having small chip hidden between leads
US9087701B2 (en) * 2011-04-30 2015-07-21 Stats Chippac, Ltd. Semiconductor device and method of embedding TSV semiconductor die within substrate for vertical interconnect in POP

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050224944A1 (en) * 2004-04-13 2005-10-13 Stack Devices Corp. Stacked semiconductor device
CN101179068A (zh) * 2006-11-09 2008-05-14 三星电子株式会社 多堆叠封装及其制造方法
CN101872757A (zh) * 2009-04-24 2010-10-27 南茂科技股份有限公司 凹穴芯片封装结构及使用其的层叠封装结构
CN102640283A (zh) * 2009-12-29 2012-08-15 英特尔公司 具有嵌入式管芯的半导体封装及其制造方法
CN202434509U (zh) * 2012-01-18 2012-09-12 刘胜 堆叠式半导体芯片封装结构

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113169183A (zh) * 2019-01-23 2021-07-23 桑迪士克科技有限责任公司 包含接合到支撑管芯的两侧的存储器管芯的三维半导体芯片及其制造方法

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