TW201431026A - 用於半導體元件之線尾連接器 - Google Patents

用於半導體元件之線尾連接器 Download PDF

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Publication number
TW201431026A
TW201431026A TW102137958A TW102137958A TW201431026A TW 201431026 A TW201431026 A TW 201431026A TW 102137958 A TW102137958 A TW 102137958A TW 102137958 A TW102137958 A TW 102137958A TW 201431026 A TW201431026 A TW 201431026A
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Taiwan
Prior art keywords
pads
substrate
molding compound
die
semiconductor
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TW102137958A
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English (en)
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TWI518857B (zh
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Chin-Tien Chiu
Cheeman Yu
Hem Takiar
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Sandisk Information Technology Shanghai Co Ltd
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Publication of TW201431026A publication Critical patent/TW201431026A/zh
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Abstract

本發明揭示一種記憶體元件，及一種製造該記憶體元件之方法。該記憶體元件係藉由將一或多個半導體晶粒安裝於一基板上且將該晶粒線結合至該基板而製造。囊封該晶粒及線結合，且單一化該經囊封之元件。在單一化步驟期間切斷該等線結合，且此後藉由在模製化合物之一或多個表面上之外部連接器將該等切斷之線結合連接至該基板。

Description

用於半導體元件之線尾連接器
對可攜式消費電子產品之需求之強勁增長推動對高容量儲存元件之需要。非揮發性半導體記憶體元件(諸如快閃記憶體儲存卡)愈來愈廣泛被使用以滿足對數位資訊儲存及交換之日益增長的需求。其等之可攜性、多功能性及堅固設計以及其等之高可靠性及大容量已使得此等記憶體元件能夠理想地用於各種電子元件中，包含(例如)數位相機、數位音樂播放器、電動遊戲機、PDA及蜂巢式電話。
儘管已知各種封裝組態，然快閃記憶體儲存卡大體上可製造為系統級封裝(SiP)或多晶片模組(MCM)，其中複數個晶粒以一堆疊組態安裝於一基板上。先前技術圖1及圖2中展示一習知半導體封裝20(無模製化合物)之一邊視圖。典型封裝包含安裝至一基板26之複數個半導體晶粒22、24。已知將半導體晶粒層疊於彼此頂部上而具有一偏移(先前技術圖1)或呈一堆疊組態。在一堆疊組態中，晶粒22與24可藉由一間隔層34(先前技術圖2)或一膜層(其中可嵌入來自下晶粒之線結合)而分離。儘管圖1及圖2中未展示，然半導體晶粒形成有在晶粒之一上表面上之晶粒結合墊。基板26可由夾置於上導電層與下導電層之間之一電絕緣芯材(core)形成。
上導電層及/或下導電層可經蝕刻以形成包含電引線及結合指針之電導圖案。線結合可結合於半導體晶粒22、24之晶粒結合墊與基板26之結合指針之間，以將半導體晶粒電耦合至基板。基板上之電引線 繼而提供晶粒與一主機元件之間之一電路徑。一旦建立晶粒與基板之間之電連接，則接著通常將總成裝入一模製化合物(未展示)中以提供一保護封裝。
基板26之長度(且因此經囊封之封裝20之總長度)大於晶粒22、24。此之一原因在於，晶粒與基板上之線結合位置之間需要用於一線結合毛細管32(圖2)之空間以在基板26與晶粒22、24之間形成線結合。若至基板26之線結合太過接近於晶粒而形成，則毛細管32將在形成基板上之結合之前接觸晶粒堆疊中之晶粒之一者。晶粒堆疊愈高，則晶粒與基板上之線結合位置之間所需之空間愈大。
20‧‧‧半導體封裝/封裝
22‧‧‧半導體晶粒
24‧‧‧半導體晶粒
26‧‧‧基板
32‧‧‧線結合毛細管/毛細管
34‧‧‧間隔層
150‧‧‧半導體元件/元件
152‧‧‧基板
153‧‧‧晶粒堆疊/堆疊
154‧‧‧半導體晶粒/快閃記憶體晶粒/記憶體晶粒
156‧‧‧半導體晶粒/快閃記憶體晶粒/記憶體晶粒
158‧‧‧半導體晶粒/快閃記憶體晶粒/記憶體晶粒
160‧‧‧半導體晶粒/快閃記憶體晶粒/記憶體晶粒
161‧‧‧控制器晶粒
162‧‧‧接觸墊
162a‧‧‧第一接觸墊
162b‧‧‧第二接觸墊
164‧‧‧錨定墊
166‧‧‧膜層
168‧‧‧晶粒結合墊
170‧‧‧結合線/第一組結合線
170a‧‧‧第一組結合線/結合線
170b‧‧‧第二組結合線/對角結合線/結合線
176‧‧‧基板面板/面板
178‧‧‧保留區域
180‧‧‧模製化合物
182‧‧‧表面
184‧‧‧外部連接器
184a‧‧‧斜向區段/水平區段
184b‧‧‧斜向區段/外部連接器區段
184c‧‧‧外部連接器
184d‧‧‧外部連接器
220‧‧‧步驟
222‧‧‧步驟
224‧‧‧步驟
226‧‧‧步驟
230‧‧‧步驟
240‧‧‧步驟
244‧‧‧步驟
250‧‧‧步驟
252‧‧‧步驟
256‧‧‧步驟
260‧‧‧步驟
264‧‧‧步驟
L‧‧‧長度
圖1及圖2係其中省略模製化合物之兩個習知半導體封裝設計之先前技術邊視圖。
圖3係本發明之一實施例之一流程圖。
圖4係在製造之第一階段期間安裝於且線結合至基板上之錨定墊之一晶粒堆疊之一側視圖。
圖5A係圖4中所展示之晶粒堆疊及基板之一俯視圖。
圖5B係圖5A中所展示之一替代實施例之一俯視圖。
圖6A、圖6B及圖6C係根據本發明之實施例在囊封之前之記憶體元件之一面板之替代組態之俯視圖。
圖7係如圖4中之進一步包含模製化合物之一側視圖。
圖8係圖7中所展示之晶粒堆疊及基板之一俯視圖。
圖9係如圖7中之其中模製化合物、線結合及基板之一部分已自元件單一化之一側視圖。
圖10係圖9中所展示之半導體元件之一俯視圖。
圖11係圖9中所展示之半導體元件之一端視圖。
圖12係根據本發明之實施例如圖9中之進一步展示形成於模製化 合物之外部上之外部連接器之一側視圖。
圖13係圖12中所展示之半導體元件之一俯視圖。
圖14係圖12中所展示之半導體元件之一端視圖。
圖15係圖12中所展示之半導體元件之一透視圖。
圖16係堆疊於一陣列中以用於形成外部連接器之若干半導體元件之一透視圖。
圖17係在半導體元件之至少兩個側上包含外部連接器之一半導體元件之一替代實施例之一透視圖。
圖18、圖19及圖20分別係根據本發明之一替代實施例之一半導體元件之側視圖、俯視圖及端視圖。
圖21、圖22及圖23分別係圖18至圖20之半導體元件在單一化及移除模製化合物、結合線及基板之一部分之後之側視圖、俯視圖及端視圖。
圖24係如圖23中之進一步展示外部連接器之一端視圖。
圖25及圖26係包含暴露於模製化合物之一外表面中之結合線之一單一化半導體元件之俯視圖及端視圖。
圖27係如圖26中之進一步展示將暴露於模製化合物之外表面上之結合線連接至基板之外部連接器之一端視圖。
圖28係展示圖27中所展示之一替代外部連接器組態之一端視圖。
圖29係根據又一實施例之一半導體元件之一透視圖，其展示自模製化合物之一表面延伸至另一表面之外部連接器。
現將參考圖3至圖29來描述實施例，該等實施例係關於一種包含一小長度及/或寬度之半導體元件。在實例中，小長度及/或寬度可藉由在一晶粒堆疊中之半導體晶粒與基板上之錨定墊之間形成結合線而 達成。在囊封之後，可以一移除錨定墊且沿著結合線之長度切斷該等結合線以達成一整體小長度及/或寬度之方式而單一化半導體元件。切斷之結合線暴露於模製化合物之一表面中，且接著可經由形成於模製化合物之一表面上之外部連接器電耦合至基板上之接觸墊。
應瞭解，本發明可以各種不同形式體現且不應被理解為限制於本文中闡述之實施例。實情係，提供此等實施例以使得本發明將係全面的及完全的，且將透徹地將本發明傳達給熟習此項技術者。實際上，本發明旨在涵蓋此等實施例之替代、修改及等效物，該等替代、修改及等效物包含於如藉由隨附申請專利範圍所定義之本發明之範疇及精神內。此外，在以下本發明之詳細描述中，闡述數種具體細節以便提供本發明之一全面理解。然而，一般技術者將明白，可在無此等具體細節之情況下實踐本發明。
如本文中可使用之術語「頂部」、「底部」、「上」、「下」、「垂直」及/或「水平」僅用於方便及闡釋性目的，且因為可交換所指稱項目之位置，所以該等術語不意謂限制本發明之描述。
圖3係用於形成一微覆蓋區(small footprint)記憶體元件之一實施例之一流程圖。最初參考圖4及圖5A，半導體元件150包含一基板152，該基板上安裝有具有半導體晶粒154、156、158及160之一晶粒堆疊153。儘管圖中所展示之晶粒堆疊153包含四個記憶體晶粒及一控制器晶粒，然在進一步實施例中，晶粒堆疊可包含更多或更少個晶粒。再者，儘管圖4及圖5A(及其他圖)展示一個別半導體元件150，然應瞭解，如下文中所說明，元件150可連同一基板面板176(圖6A)上之複數個其他元件150一起批次處理以達成規模經濟。基板面板176上之元件150之列及行之數目可不同。
基板面板176以複數個基板152(再次，圖4及圖5A中展示之此一基板)開始。基板152可係各種不同晶片載體媒體，其包含一印刷電路 板(PCB)、一引線架或一捲帶式自動結合(TAB)捲帶。在基板152係一PCB之情況下，基板可由具有一頂部導電層及一底部導電層之一芯材形成。該芯材可由各種介電材料(諸如，舉例而言，聚醯亞胺層壓板、包含FR4及FR5之環氧樹脂、雙馬來醯亞胺三嗪(BT)及類似物)形成。儘管此對於本發明係不關鍵的，然芯材可具有介於40微米(μm)至200μm之間之一厚度，然而在替代實施例中，芯材之厚度可在該範圍外變化。在替代實施例中，芯材可係陶瓷的或有機的。
圍繞芯材之導電層可由銅或銅合金、鍍銅或鍍銅合金、鍍銅鋼或已知以用於基板面板上之其他金屬及材料形成。導電層可具有約10μm至25μm之一厚度，然而在替代實施例中，該等層之厚度可在該範圍外變化。
在一步驟220中，基板152經鑽孔以界定基板152中之貫穿導通孔(未展示)。基板152可由若干導電層形成，且該等導通孔可將電信號自一層傳達至另一層。接著在步驟222中，電導圖案形成於一或多個導電層上。(若干)電導圖案可包含電跡線(未展示)、接觸墊162及一或多個錨定墊164(該等墊162、164之一些者在圖中經編號)。所示接觸墊162及錨定墊164之數目僅作為實例，且基板152可包含多於圖中所展示之接觸墊及/或錨定墊，且其等可在不同於圖中所展示之位置中。基板152之頂部及/或底部表面上之電導圖案可藉由各種已知程序(包含(例如)各種微影程序)而形成。
在圖5A中所展示之一實施例中，可存在相同數目個接觸墊162及錨定墊164。接觸墊162可在一第一列中與彼此對準，且錨定墊164可在一第二列中與彼此對準。各接觸墊162可具有一對應錨定墊164。在進一步實施例中，接觸墊162之數目可不同於錨定墊164之數目。作為圖5B中所展示之一實例，可存在多個接觸墊162，而僅存在具有圖5A之若干錨定墊164在一起之一長度之一單個錨定墊164。
再次參考圖2之流程圖，接著在步驟224中可以一自動光學檢測(AOI)來檢測基板152。一經檢測後，則在步驟226中將一焊接遮罩施覆至基板而暴露出接觸墊162及錨定墊164。在施覆焊接遮罩之後，可在步驟230中以一已知電鍍或薄膜沈積程序運用Ni/Au或類似物鍍敷電導圖案上之接觸墊162、錨定墊164及任何其他焊接區域。
已知鍍敷一基板上之接觸墊可提供接觸墊與焊接於其之一結合線之間之一較佳電連接。然而，如下文中說明，不必在結合線與錨定墊164之間提供一最佳電連接，且結合線並未焊接至接觸墊162。相應地，在進一步實施例中可省略接觸墊162及/或錨定墊164之鍍敷。或者，可鍍敷接觸墊162及/或錨定墊164，但運用除Ni/Au外之一材料。
接著在一步驟240中，可將被動組件(未展示)附接至基板152之頂部表面。可如以已知表面安裝及迴焊程序藉由至接觸墊之連接而將一或多個被動組件安裝於基板152上且將其電耦合至電導圖案。被動組件可包含(例如)一或多個電容器、電阻器及/或電感器，然而可設想其他組件。
如(例如)在圖4中所見及如上文所提及，接著在一步驟244中可將一或多個半導體晶粒附接至基板152之頂部表面。圖5之實施例包含具有四個快閃記憶體晶粒154、156、158及160之一晶粒堆疊153及一控制器晶粒161。記憶體晶粒154至160可係(例如)快閃記憶體晶片(NOR/NAND)，然而可設想其他類型之記憶體晶粒。控制器晶粒161可係(例如)一ASIC。為明確起見，自其他圖式中省略控制器晶粒161及來自其之線結合。
如下文中說明，晶粒堆疊153中之晶粒可大體上與彼此對準而堆疊，且可藉由一膜層166(該等層之一者在圖4中經編號)分離，該膜層166允許線結合自來自晶粒堆疊153中之各晶粒之晶粒結合墊至基板而形成。在進一步實施例中，儘管可能放大半導體元件之覆蓋區，然晶 粒可以一交錯、階梯組態堆疊，且可省略膜層166。
在已將晶粒堆疊153中之晶粒安裝於基板上之後(或在已安裝晶粒堆疊中之各晶粒之後)，在步驟250中可使結合線170連接於各晶粒上之晶粒結合墊168與一或多個錨定墊164之間。一或多個錨定墊164可與晶粒堆疊153相間隔達一最小距離，以使得全部線結合可運用一線結合毛細管(未展示)形成而無與晶粒堆疊中之一晶粒接觸之危險。此距離將取決於包含晶粒堆疊153中晶粒之數目之因素而變化。在進一步實施例中，一或多個錨定墊164可與晶粒堆疊153相間隔達多於此最小距離。
儘管未線結合至接觸墊162，然在一實例中，一結合線可在一晶粒結合墊與一錨定墊之間之一接觸墊上方筆直通過。即，如在圖5A之俯視圖中所見，在一實例中，一晶粒結合墊168、一接觸墊162及一錨定墊164可與彼此對準，使得接觸墊162及對應錨定墊164可運用一最短長度結合線170連接。此結合線170可在一接觸墊162上方筆直通過。如下文中說明，一晶粒結合墊168可不與其藉由一結合線170所耦合之一錨定墊對準。
錨定墊164不必使各晶粒上之各自結合線170彼此電隔離。因此，(例如)如在圖5B之實施例中所展示，若干晶粒結合墊168可經由多個結合線170耦合至一單個錨定墊164。
圖6A展示半導體元件150之一面板176。晶粒堆疊153、接觸墊162及錨定墊164在兩個半導體元件150上經編號。如在圖5A中之一個別半導體元件150之視圖中及在圖6A中之元件之一面板176中所見，各半導體元件150之基板152上界定有一保留(keep-out)區域178。保留區域178係一在基板152上當自面板單一化個別半導體元件150時可鋸掉或鋸斷之區域，如下文中說明。習知地，基板152上之保留區域無諸如接觸墊之結構。然而，如下文中說明，根據本發明，錨定墊164 可形成於保留區域178中，且在單一化期間移除。在習知設計中，接納線結合之接觸墊不可定位於此保留區域中，且基板之尺寸需要大於本技術中基板之尺寸，使得單一化基板同時能夠使接納線結合之接觸墊保持完好。
圖6A展示兩列半導體元件150，各列包含具有錨定墊164之一保留區域178。應瞭解，可存在單列半導體元件及包含錨定墊164之一單個保留區域。此外，面板176可具有兩列以上半導體元件，各列包含具有錨定墊164之一保留區域。儘管未展示，然在相鄰半導體元件150之間可存在數行保留區域178，該等保留區域178自圖6A之視角垂直定向。此等垂直保留區域178亦可或替代地包含結合線170附接至其之錨定墊。
在圖6A之實施例中，各列中之各半導體元件150包含一或多個錨定墊164。圖6B展示根據一替代實施例之一面板176，其中一整列之半導體元件150共用大體上跨面板176之寬度延伸之一單個錨定墊。因此，在圖6B之包含兩列半導體元件150之實施例中，存在兩個錨定墊164。圖6C展示一面板176之另一實施例，其中頂部列之半導體元件沿著其等底部邊緣線結合至基板，且底部列之半導體元件沿著其等頂部邊緣線結合至基板。在此一實施例中，頂部列中之全部半導體元件及底部列中之全部半導體元件可共用在該等列之間且大體上延伸達面板176之長度之一單個錨定墊164。可設想其中兩個或更多個半導體元件150共用一保留區域178中之一共同錨定墊164之其他組態。
在實施例中，在結合線170形成於晶粒堆疊153中之晶粒與基板152上之錨定墊164之間之後，如圖7及圖8之側視圖及俯視圖中所展示，可在步驟252中將基板及晶粒囊封於一模製化合物180中。儘管此對於本發明係不關鍵的，然模製化合物180可係諸如(舉例而言)可購自Sumito公司或Nitto Denko公司(其等兩者在日本均具有營運總部)之 環氧樹脂。可設想來自其他製造商之其他模製化合物。可根據各種程序(包含藉由轉移模製或射出模製技術)施覆模製化合物。
在進一步實施例中，囊封程序可藉由FFT(Flow Free Thin)壓縮模製執行。此一FFT壓縮模製程序係已知的，且(例如)在由日本京都Towa公司之Matsutani,H在2009年Microelectronics and Packaging Conference之標題為「Compression Molding Solutions For Various High End Package And Cost Savings For Standard Package Applications」之一刊物中描述此一FFT壓縮模製程序，該刊物之全文以引用的方式併入本文中。
模製化合物至少覆蓋被動組件、堆疊153中之晶粒及結合線170。(在施覆模製化合物180之後，此等組件自端視圖及俯視圖將不可見，但圖中為理解本發明而展示此等組件)。
在已在步驟252中囊封面板176上之半導體元件150之後，可在步驟256中自面板單一化各自元件。特定言之，可在相鄰半導體元件150之間之保留區域178中縱向及橫向切割面板176。各元件150可藉由各種切割方法之任一者而單一化，包含鋸切、水刀切割、雷射切割、水導引雷射切割、乾式介質切割、及金剛石塗層線切割。儘管直線切割將大體上界定矩形或方形形狀元件150，然應瞭解，在本發明之進一步實施例中，元件150可具有除矩形及方形外之形狀。
圖9、圖10及圖11之側視圖、俯視圖及端視圖中分別展示於具有一長度L之一單一化半導體元件150。如所展示，單一化步驟可移除錨定墊164及鋸斷嵌入於模製化合物180中之結合線170。如在圖9及圖10中所見，此留下縮短之結合線170。如在圖11中所見，此亦使得結合線170之尾端沿著單一化切口自模製化合物之一表面182暴露。亦如(例如)在圖9至圖11中所見，單一化切口亦可切斷接觸墊162之一部分，使得其等亦自表面182暴露。
在步驟256中單一化之後，可在步驟260中將外部連接器184施覆至模製化合物之外表面，以便將暴露之結合線170之尾端連接至其等適當接觸墊162以形成一可運行半導體元件。外部連接器184分別展示於圖12、圖13、圖14及圖15之側視圖、俯視圖、端視圖及透視圖中。外部連接器可由各種導電材料形成且可藉由各種方法施覆。作為材料之非限制性實例，外部連接器可由以下材料形成：銅、焊料或Ni/Au鍍敷材料。作為形成方法之非限制性實例，外部連接器可藉由以下方法施覆：微影及其他印刷方法、電鑄及其他金屬化方法、諸如物理汽相沈積及化學汽相沈積之薄膜沈積，以及焊接。可設想其他導電材料及形成方法。
如上文所描述，在一實施例中，結合線170自晶粒堆疊153中之各晶粒上垂直對準之晶粒結合墊168延伸至一共同錨定墊164。相應地，在此等實施例中，如在圖11中所見，在單一化之後，來自一組垂直對準之晶粒結合墊之結合線170之尾端亦可與彼此垂直對準。此外，在實施例中，此等垂直對準之尾端亦可在基板152上之一接觸墊162上方對準。相應地，如在圖14及圖15中所見，在實施例中，各自外部連接器184可利用一單個、筆直長度之材料連接結合線170之適合尾端。如下文中更詳細說明，在進一步實施例中，外部連接器可使用除一直線外之材料而將一組線結合尾端連接至一接觸墊。
外部連接器184可同時施覆至多個半導體元件之表面以達成規模及效率經濟。如圖16之透視圖中所展示，在單一化之後，半導體元件150之一陣列可在多個列及行之一陣列中與彼此對準，使得暴露之表面182接納全部面向相同方向(例如，向上)之外部連接器。接著可將外部連接器同時施覆至陣列中之全部半導體元件之暴露之表面182。在一實例中，一陣列中可設置一百個半導體元件以一次接納全部外部連接器，然而在進一步實例中，陣列中之數目可更多或更少。
如圖中所展示，在實施例中，外部連接器184之一寬度可接近於結合線170之直徑。然而，為提供更大容限，外部連接器184可具有大於結合線170之直徑之一寬度。一外部連接器184可具有一寬度，該寬度允許將全部適當結合線170電連接至其等適當接觸墊162，同時使全部適當結合線170與不應電連接至該接觸墊162之其他外部連接器184及結合線電隔離。
在實施例中，在形成外部連接器184之後，可運用一保護層(其可係一保形塗層、墨或黏著蓋)覆蓋外部連接器以隱藏及保護外部連接器。在其他實施例中可省略該保護層。
使用上文描述之步驟，可製造具有比由習知製造方法所允許之覆蓋區更小之一覆蓋區之一半導體元件。在習知半導體元件之一實例中，晶粒堆疊之一邊緣(線結合在該邊緣外而形成)與模製化合物之相鄰表面之間至少需要600μm。使用本技術，可將晶粒堆疊之一邊緣(線結合在該邊緣外而形成)與模製化合物之相鄰表面182之間之距離減小至100μm。根據本技術之習知元件及元件之此等數目僅作為實例。在本技術之進一步實施例中，在其外形成有結合線之晶粒堆疊之一邊緣與模製化合物之相鄰表面182之間之距離可大於100μm或減小至小於100μm。
本技術提供優於僅減小一半導體元件之尺寸之優點。例如，因為最終結合線短於習知設計中之結合線，所以與習知設計中相比，最終結合線可更緊靠在一起而放置。此允許晶粒結合墊在晶粒上及接觸墊在基板上之一更密集組態。此外，本技術提供有關將電信號自晶粒投送至基板之更大靈活性。在習知設計具有二維佈線(僅在基板之平面中)之情況下，本技術實現三維佈線。佈線不僅可在基板之平面中發生，而且可沿著模製化合物之壁(側及頂部)發生。因此，與習知半導體元件設計相比，電路設計師可設計一種具有更大靈活性及可能性 之三維佈線方案。下文中說明此等設計之非限制性實例。
在上文描述之實例中，結合線170在晶粒堆疊153之一單個邊緣外而形成。然而應瞭解，結合線170可在兩個相對或相鄰邊緣外、三個邊緣外或圍繞晶粒堆疊153之全部四個邊緣外而形成。在此等實施例中，結合線170可在一保留區域178中結合至錨定墊164，且接著在如上文中描述之單一化期間截斷。此後，外部連接器可形成於包含截斷之結合線170之各邊緣上。在圖17中所展示之一實例中，結合線170在兩個相鄰邊緣外而形成。因此，在此實施例中，包含外部連接器184之兩個相鄰邊緣將結合線170之尾端連接至接觸墊162。
如所提及，在上文描述之實施例中，線結合垂直形成於與彼此垂直對準且與接觸墊162及錨定墊164垂直對準之晶粒結合墊之間。然而，此在進一步實施例中可係不同的。例如，如在圖18、圖19及圖20之側視圖、俯視圖及端視圖中所展示，一第一組結合線170a形成於垂直對準之晶粒結合墊168與錨定墊164之間，但第二組結合線170b形成於未與其等所連接至之一錨定墊164垂直對準之晶粒結合墊168之間。
作為斜向結合線170b之一結果，當半導體元件150經囊封及單一化以使線結合之尾端保持於一表面182中時，該等尾端之一些者在一接觸墊162上將不垂直對準。此實例分別展示於圖21、圖22及圖23之側視圖、俯視圖及端視圖中。如在圖22及圖23中所見，垂直對準之結合線170a之尾端在其等相關聯接觸墊162上方對準，但結合線170b之尾端在其等相關聯接觸墊162上方不垂直對準。
相應地，在此實施例中，可運用外部連接器之不連續區段將未對準之結合線170b連接至其等相關聯接觸墊162。例如，圖24展示外部連接器之斜向區段184b。圖21至圖24提供一實例，且應瞭解，在進一步實施例中，外部連接器184可具有不連續區段之各種其他組態。
如在圖25及圖26之俯視圖及端視圖中所展示，在另一實例中， 全部結合線170在晶粒堆疊內可垂直對準且與各自錨定墊164垂直對準，以導致結合線170垂直對準之尾端。然而，電路佈局可具有將一行結合線170之尾端連接至除其等所對準之接觸墊外之接觸墊162之外部連接器。此兩個實例展示於圖27及圖28之端視圖中。在圖27之實例中，兩行結合線170藉由斜向區段184a連接至未對準接觸墊162。在圖28之實例中，兩行結合線170藉由水平區段184a連接至一未對準接觸墊162。外部連接器在電路設計之佈局中添加習知設計中不可用之一程度之靈活性。
圖29圖解說明其中外部連接器184不僅可用以將線結合之尾端連接至未對準接觸墊，而且可將其連接至定位於半導體元件150之一完全不同側上之未對準接觸墊之另一程度之靈活性。在所展示之實例中，一外部連接器區段184b將兩行結合線連接至在半導體元件150之相鄰側中之一晶粒結合墊168。此外，儘管此大體上可係一行線結合中之全部線結合連接至相同接觸墊162，然此在進一步實例中可係不同的。圖29展示一行線結合中經由一外部連接器184c連接至一第一接觸墊162a之一第一組結合線170，及該行中經由在半導體元件150之一不同側上之一外部連接器184d連接至一第二接觸墊162b之一第二組。此外，如所見，外部連接器在電路設計之佈局中添加極大靈活性，且允許形成多維電連接以在各種組態中將晶粒結合墊168連接至接觸墊162。圖29中之實例展示幾個實例，但許多其他組態係可能的及可設想的。
一旦經由外部連接器184建立電連接，則可在步驟264中測試半導體元件以判定封裝是否適當運行。如此項技術中已知，此測試可包含電氣測試、預燒及其他測試。
總結而言，本技術係關於一種記憶體元件，該記憶體元件包括：一基板，其包含複數個接觸墊；一或多個半導體晶粒，其包含複 數個晶粒結合墊；一模製化合物，其囊封該一或多個半導體晶粒；及一電路，其使該複數個接觸墊之一接觸墊與該複數個晶粒結合墊之一晶粒結合墊電耦合，該電路之至少一部分形成於該模製化合物之至少一外表面上。
在另一實例中，本技術係關於一種記憶體元件，該記憶體元件包括：一基板，其包含複數個接觸墊；一或多個半導體晶粒，其包含複數個晶粒結合墊；一模製化合物，其囊封該一或多個半導體晶粒；及一外部連接，其設置於該模製化合物之一或多個表面上以用於使該複數個接觸墊之一接觸墊與該複數個晶粒結合墊之一晶粒結合墊通信電耦合。
在又一實例中，本技術係關於一種記憶體元件，該記憶體元件包括：一基板，其包含複數個接觸墊；一或多個半導體晶粒，其包含複數個晶粒結合墊；一模製化合物，其囊封該一或多個半導體晶粒，該複數個接觸墊之一接觸墊具有暴露於該模製化合物之一表面之一邊緣。
在又一實例中，本技術係關於一種記憶體元件，該記憶體元件包括：一基板，其包含複數個接觸墊；複數個半導體晶粒，該複數個半導體晶粒中之各晶粒包含複數個晶粒結合墊；一模製化合物，其囊封該一或多個半導體晶粒；複數個結合線，其等各自具有電耦合至該複數個晶粒結合墊之一晶粒結合墊之一第一端，且各自具有與該第一端相對而終止於該模製化合物之一表面之一第二尾端；及複數個外部連接，其等設置於該模製化合物之一或多個表面上，該複數個外部連接將該複數個結合線電連接至該基板上之該複數個接觸墊。
在另一實例中，本技術係關於一種形成一半導體元件之方法，該方法包括：(a)將一或多個半導體晶粒安裝於一基板上；(b)將半導體晶粒線結合至該基板上；(c)囊封該一或多個半導體晶粒及結合 線；(d)藉由部分切斷在該步驟(b)中形成之線結合而單一化經囊封之半導體晶粒；及(e)將切斷之線結合電連接至該基板。
已為圖解說明及描述之目的而呈現本發明之前述詳細描述。此並非旨在窮舉性或將本發明限制於所揭示之精確形式。根據上文教示，各種修改及變動係可能的。所描述之實施例係選定以便最佳說明本發明之原理及其實際應用，以藉此使其他熟習此項技術者能夠以各種實施例最佳利用本發明，且使得可設想如適合於特定使用之各種修改。期望本發明之範疇藉由在此所附之申請專利範圍定義。
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Claims (26)

  1. 一種記憶體元件，其包括：一基板，其包含複數個接觸墊；一或多個半導體晶粒，其包含複數個晶粒結合墊；一模製化合物，其囊封該一或多個半導體晶粒；及一電路，其使該複數個接觸墊之一接觸墊與該複數個晶粒結合墊之一晶粒結合墊電耦合，該電路之至少一部分係形成於該模製化合物之至少一外表面上。
  2. 如請求項1之元件，其中形成於該模製化合物之至少一外表面上的該電路之該部分連接至終止於該模製化合物之該外表面中之一結合線。
  3. 如請求項2之元件，其中形成於該模製化合物之一外表面上的該電路之該部分連接至終止於該模製化合物之該外表面中之一結合線之一尾端。
  4. 如請求項3之元件，其中該結合線包含與該尾端相對且電耦合至該複數個晶粒結合墊之一晶粒結合墊之一端。
  5. 如請求項1之元件，其中形成於該模製化合物之至少一外表面上的該電路之該部分係形成於該模製化合物之一單個表面上。
  6. 如請求項1之元件，其中形成於該模製化合物之至少一外表面上的該電路之該部分係形成於該模製化合物之至少兩個表面上。
  7. 一種記憶體元件，其包括：一基板，其包含複數個接觸墊；一或多個半導體晶粒，其包含複數個晶粒結合墊；一模製化合物，其囊封該一或多個半導體晶粒；及一外部連接，其設置於該模製化合物之一或多個表面上以用 於使該複數個接觸墊之一接觸墊與該複數個晶粒結合墊之一晶粒結合墊通信電耦合。
  8. 如請求項7之元件，其進一步包括一線結合，該線結合具有電連接至該晶粒結合墊之一第一端及與該第一端相對且終止於該模製化合物之一表面之一第二尾端。
  9. 如請求項7之元件，其中外部連接器終止於半導體元件之一第一表面上之一接觸墊且開始於該相同第一表面上。
  10. 如請求項7之元件，其中該外部連接器終止於該半導體元件之一第一表面上之一接觸墊且開始於該半導體元件之不同於該第一表面之第二表面上。
  11. 如請求項7之元件，其中該連接器係與該接觸墊接觸而在一直線上自其起點延伸至其終點。
  12. 如請求項7之元件，其中該連接器包含自其起點延伸之一第一部分及終止於該接觸墊之一第二部分，該第一部分及該第二部分以相對於彼此之不連續角度延伸。
  13. 如請求項7之元件，其中該一或多個半導體晶粒包含至少兩個堆疊半導體晶粒。
  14. 如請求項13之元件，其進一步包括自該至少兩個堆疊半導體晶粒之各者上之晶粒結合墊延伸之電引線，該等電引線終止於該模製化合物之一表面，該等外部連接器將該等電引線電連接至該複數個接觸墊之至少一接觸墊。
  15. 一種記憶體元件，其包括：一基板，其包含複數個接觸墊；一或多個半導體晶粒，其包含複數個晶粒結合墊；一模製化合物，其囊封該一或多個半導體晶粒，該複數個接觸墊之一接觸墊具有暴露於該模製化合物之一表面之一邊緣。
  16. 如請求項15之元件，其進一步包括一外部連接，該外部連接係設置於該模製化合物之一或多個表面上以用於使該接觸墊與該複數個晶粒結合墊之一晶粒結合墊通信電耦合。
  17. 如請求項15之元件，其進一步包括一線結合，該線結合具有電連接至該晶粒結合墊之一第一端及與該第一端相對且終止於該模製化合物之一表面之一第二尾端。
  18. 一種記憶體元件，其包括：一基板，其包含複數個接觸墊；複數個半導體晶粒，該複數個半導體晶粒中之各晶粒包含複數個晶粒結合墊；一模製化合物，其囊封該一或多個半導體晶粒；複數個結合線，其等各自具有電耦合至該複數個晶粒結合墊之一晶粒結合墊之一第一端，且各自具有與該第一端相對且終止於該模製化合物之一表面之一第二尾端；及複數個外部連接，其等設置於該模製化合物之一或多個表面上，該複數個外部連接將該複數個結合線電連接至該基板上之該複數個接觸墊。
  19. 如請求項18之元件，其中該複數個晶粒結合墊包括一組晶粒結合墊，一晶粒結合墊來自該複數個晶粒中之該晶粒之各者，該組晶粒結合墊中之各晶粒結合墊部分藉由該複數個外部連接器之一外部連接器而電連接至該複數個接觸墊之一單個接觸墊。
  20. 如請求項19之元件，來自該組晶粒結合墊中之各晶粒結合墊之該等線結合之該等第二尾端一起在該模製化合物之該表面中形成一直線。
  21. 如請求項19之元件，該外部連接器連接來自該組晶粒結合墊之該等線結合之該等第二尾端與該基板上之該接觸墊而形成一實 質上直線。
  22. 如請求項19之元件，該外部連接器連接來自該組晶粒結合墊之該等線結合之該等第二尾端與該基板上之該接觸墊而形成一不連續線。
  23. 一種形成一半導體元件之方法，其包括：(a)將一或多個半導體晶粒安裝於一基板上；(b)將該等半導體晶粒線結合至該基板；(c)囊封該一或多個半導體晶粒及結合線；(d)藉由部分切斷在該步驟(b)中形成之該等線結合而單一化該等經囊封之半導體晶粒；及(e)將該等切斷之線結合電連接至該基板。
  24. 如請求項23之方法，其中將該等切斷之線結合電連接至該基板之該步驟(e)包括：在模製化合物之一表面上形成外部連接器之步驟，該等外部連接器將該等切斷之線結合電連接至該基板上之接觸墊。
  25. 如請求項23之方法，其中將該等半導體晶粒線結合至該基板之該步驟(b)包括：將該等半導體晶粒線結合至該基板上之一或多個墊之步驟，在單一化該等經囊封之半導體晶粒之該步驟(d)中移除該一或多個墊。
  26. 如請求項25之方法，其中將該等切斷之線結合電連接至該基板之該步驟(e)包括：將該等切斷之線結合連接至與在該步驟(d)中移除之該一或多個墊分離之接觸墊之步驟。
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