CN102194740A - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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Publication number
CN102194740A
CN102194740A CN2011100616908A CN201110061690A CN102194740A CN 102194740 A CN102194740 A CN 102194740A CN 2011100616908 A CN2011100616908 A CN 2011100616908A CN 201110061690 A CN201110061690 A CN 201110061690A CN 102194740 A CN102194740 A CN 102194740A
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Prior art keywords
insulating barrier
interconnection structure
conductive layer
sealant
semiconductor element
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CN2011100616908A
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CN102194740B (zh
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林耀剑
P.C.马里穆图
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Changdian Integrated Circuit Shaoxing Co ltd
Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

一种半导体器件具有安装在载体上的半导体管芯。密封剂被沉积在载体和半导体管芯上。除去载体。第一互连结构形成在密封剂和所述管芯的第一表面上。第二互连结构形成在密封剂和所述管芯的第二表面上。在形成所述通路之前，第一保护层形成在第一互连结构上，且第二保护层形成在第二互连结构上。通过第二互连结构、密封剂和第一互连结构形成多个通路。第一导电层形成在所述通路中以电连接第一互连结构和第二互连结构。绝缘层形成在第一互连结构和第二互连结构上并进入所述通路中。分立半导体部件可以安装到第一互连结构。

Description

半导体器件及其形成方法
技术领域
本发明总体上涉及半导体器件，更具体地说涉及半导体器件和形成通过晶片级芯片规模封装的第一和第二互连结构以及密封剂的导电通路的方法。
背景技术
在现代电子产品中通常会发现有半导体器件。半导体器件在电部件的数量和密度上有变化。分立的半导体器件一般包括一种电部件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器、以及功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件通常包括数百到数百万的电部件。集成半导体器件的实例包括微控制器、微处理器、电荷耦合器件（CCD）、太阳能电池、以及数字微镜器件（DMD）。
半导体器件执行多种功能，例如高速计算、发射和接收电磁信号、控制电子器件、将日光转换成电、以及为电视显示器生成可视投影。在娱乐、通信、功率转换、网络、计算机、以及消费品领域中有半导体器件的存在。在军事应用、航空、汽车、工业控制器、以及办公设备中也有半导体器件的存在。
半导体器件利用半导体材料的电特性。半导体材料的原子结构允许通过施加电场或基极电流（base current）或者通过掺杂工艺来操纵（manipulated）它的导电性。掺杂把杂质引入半导体材料中以操纵和控制半导体器件的导电性。
半导体器件包括有源和无源电结构。有源结构（包括双极和场效应晶体管）控制电流的流动。通过改变掺杂水平并且施加电场或基极电流，晶体管促进或限制电流的流动。无源结构（包括电阻器、电容器、和电感器）产生执行多种电功能所必需的电压和电流之间的关系。无源和有源结构被电连接以形成电路，所述电路能够使半导体器件执行高速计算和其它有用的功能。
通常利用两个复杂的制造工艺来制造半导体器件，即前端制造和后端制造，每个可能包括数百个步骤。前端制造包括在半导体晶片的表面上形成多个管芯。每个管芯通常相同并且包括通过电连接有源和无源部件形成的电路。后端制造包括从已完成的晶片单体化（singulating）单个管芯并且封装管芯以提供结构支撑和环境隔离。
半导体制造的一个目标是制造更小的半导体器件。更小的半导体器件通常消耗更少功率、具有更高的性能、并且能够被更有效地制造。另外，更小的半导体器件具有更小的占用空间（footprint），其对于更小的最终产品而言是期望的。通过改善导致产生具有更小、更高密度的有源和无源部件的管芯的前端工艺可以实现更小的管芯尺寸。通过改善电互连和封装材料，后端工艺可以产生具有更小占用空间的半导体器件封装。
例如当堆叠半导体器件以便有效集成时，半导体器件通常需要垂直互连结构。多级半导体器件（例如包含半导体管芯的扇出型晶片级芯片规模封装（FO-WLCSP））和外部器件之间的电互连可以利用导电直通硅通路（TSV）、导电直通孔通路（THV）、导电直通模塑通路（through mold vias，TMV）、镀铜导电柱和导电凸块来实现。这些垂直互连结构常常使用激光钻孔来形成通路，之后利用导电材料填充这些通路并且对上和下装配互连结构中的再分配层进行单独电镀。该必要的制造工艺耗费成本且耗时。
发明内容
存在对在WLCSP中形成导电通路的简单且节省成本的工艺的需要。因此，在一个实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供临时载体，在临时载体上安装半导体管芯且有源表面面向临时载体，在临时载体和半导体管芯上沉积密封剂，除去临时载体，在有源表面和密封剂上形成第一互连结构，在密封剂和半导体管芯的与有源表面相对的后表面上形成第二互连结构，形成通过第二互连结构、密封剂和第一互连结构的多个通路，在所述通路中形成第一导电层以电连接第一互连结构和第二互连结构，以及在第一互连结构和第二互连结构上形成第一绝缘层。
在另一个实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供载体，在载体上安装半导体管芯，在载体和半导体管芯上沉积密封剂，除去载体，在密封剂和半导体管芯的第一表面上形成第一互连结构，在密封剂和半导体管芯的与半导体管芯的第一表面相对的第二表面上形成第二互连结构，形成通过第二互连结构、密封剂和第一互连结构的多个通路，在所述通路中形成第一导电层以电连接第一互连结构和第二互连结构，以及在第一互连结构和第二互连结构上形成第一绝缘层。
在另一个实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供载体，在载体上安装半导体管芯，在载体和半导体管芯上沉积密封剂，除去载体，在密封剂和半导体管芯的第一表面上形成第一互连结构，形成通过第一互连结构且部分地通过密封剂至半导体管芯的与半导体管芯的第一表面相对的第二表面上的某一位置的多个通路，除去密封剂在半导体管芯的第二表面上的部分以打开所述通路，在所述通路中形成第一导电层，在密封剂和半导体管芯的第二表面上形成第二互连结构，以及在第一互连结构和第二互连结构上形成第一绝缘层。
在另一个实施例中，本发明是一种半导体器件，该半导体器件包括半导体管芯和沉积在半导体管芯上的密封剂。第一互连结构形成在密封剂和半导体管芯的第一表面上。第二互连结构形成在密封剂和半导体管芯的与半导体管芯的第一表面相对的第二表面上。多个导电通路被形成为通过第二互连结构、密封剂和第一互连结构以电连接第一互连结构和第二互连结构。第一绝缘层形成在第一互连结构和第二互连结构上。
附图说明
图1示出具有安装到其表面的不同类型封装的PCB；
图2a-2c示出安装到所述PCB的半导体封装的更多细节；
图3a-3j示出从WLCSP的顶面形成导电通路的过程；
图4示出通过具有一侧细间距RDL的WLCSP的导电通路；
图5示出安装到WLCSP的分立半导体封装；以及
图6a-6d示出从下装配互连结构的底面形成导电通路的过程。
具体实施方式
参考附图在下列描述中的一个或多个实施例中描述本发明，在附图中相似的数字表示相同或类似的元件。虽然根据用来实现本发明的目的的最佳方式描述本发明，但是本领域技术人员将理解的是，它旨在覆盖可以被包含在由被下列公开和各图所支持的所附权利要求及其等效物限定的本发明的精神和范围内的替代物、变型、和等效物。
一般利用两个复杂的制造工艺制造半导体器件：前端制造和后端制造。前端制造包括在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包括有源和无源电部件，所述有源和无源电部件被电连接以形成功能电路。有源电部件，例如晶体管和二极管，具有控制电流的流动的能力。无源电部件，例如电容器、电感器、电阻器、和变压器，产生执行电路功能所必需的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、刻蚀、和平面化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过例如离子注入或热扩散的技术将杂质引入到半导体材料中。所述掺杂工艺改变有源器件中的半导体材料的导电性，将半导体材料转变成绝缘体、导体，或响应于电场或基极电流动态改变半导体材料导电性。晶体管包括有变化的掺杂类型和程度的区域，所述区域根据需要被设置为使晶体管能够在施加电场或基极电流时促进或限制电流的流动。
通过具有不同电特性的材料的层形成有源和无源部件。所述层可以通过部分地由被沉积的材料的类型决定的多种沉积技术形成。例如，薄膜沉积可以包括化学汽相沉积（CVD）、物理汽相沉积（PVD）、电解电镀、以及无电极电镀（electroless plating）工艺。每个层通常被图案化以形成有源部件、无源部件、或部件之间的电连接的各部分。
可以利用光刻图案化所述层，所述光刻包括在将被图案化的层上沉积光敏材料，例如光致抗蚀剂。利用光将图案从光掩模转移到光致抗蚀剂。利用溶剂将经受光的光致抗蚀剂图案部分除去，暴露将被图案化的下层的各部分。光致抗蚀剂的剩余物被除去，留下被图案化的层。可替换地，利用例如无电极电镀或电解电镀的技术通过直接将材料沉积到通过先前的沉积/刻蚀工艺形成的区域或空隙中来图案化一些类型的材料。
在现有图案上沉积材料的薄膜可能会放大下面的图案并且引起不均匀的平面。需要均匀的平面来制造更小和更密集包装的有源和无源部件。可以利用平面化从晶片的表面除去材料和制造均匀平面。平面化包括利用抛光垫抛光晶片的表面。在抛光期间，磨料和腐蚀性化学品被添加到晶片的表面。组合的磨料机械作用和化学品腐蚀作用除去了任何不规则的表面形貌（topography），产生均匀的平面。
后端制造指的是将已完成的晶片切割或单体化成单个管芯，并且然后封装管芯用于结构支撑和环境隔离。为单体化管芯，沿被叫做划片街区（saw street）或划线的晶片非功能区域刻划和断开所述晶片。利用激光切割工具或锯条来单体化晶片。在单体化之后，单个管芯被安装到封装衬底，所述封装衬底包括用来与其它系统部件互连的引脚或接触焊盘。形成在半导体管芯上的接触焊盘然后被连接到封装内的接触焊盘。可以利用焊料凸块、柱形凸块（stud bump）、导电胶、或线结合（wirebond）来制作电连接。密封剂或其它成型材料被沉积到封装上以提供物理支撑和电隔离。已完成的封装然后被插入电系统中并且半导体器件的功能可以用到其它系统部件。
图1示出具有芯片载体衬底或印刷电路板（PCB）52的电子器件50，所述芯片载体衬底或印刷电路板（PCB）52具有多个安装在它的表面上的半导体封装。电子器件50可以具有一种半导体封装、或多种半导体封装，这取决于应用。为了说明的目的，在图1中示出不同类型的半导体封装。
电子器件50可以是利用半导体封装来执行一个或多个电功能的独立系统。可替换地，电子器件50可以是更大系统的子部件。例如，电子器件50可以是能被插入计算机中的图形卡、网络接口卡、或其它信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、RF电路、分立器件、或其它半导体管芯或电部件。
在图1中，PCB 52提供普通的衬底用于安装在PCB上的半导体封装的结构支撑和电互连。利用蒸发、电解电镀、无电极电镀、丝网印刷、或其它合适的金属沉积工艺将导电信号迹线（trace）54形成在PCB 52的表面上或各层内。信号迹线54提供半导体封装、安装的部件、以及其它外部系统部件中的每一个之间的电通信。迹线54也将电源和地连接提供给半导体封装中的每一个。
在一些实施例中，半导体器件可以具有两个封装级。第一级封装是用来将半导体管芯以机械和电的方式附着到中间载体的技术。第二级封装包括将所述中间载体以机械和电的方式附着到PCB。在其它实施例中，半导体器件可以仅具有第一级封装，其中管芯被以机械和电的方式直接安装到PCB。
为了说明的目的，几种第一级封装，包括线结合封装56和倒装芯片58，被示出在PCB 52上。另外，几种第二级封装，包括球栅阵列（BGA）60、凸块芯片载体（BCC）62、双列直插式封装（DIP）64、岸面栅格阵列（land grid array，LGA）66、多芯片模块（MCM）68、四侧无引脚扁平封装（quad flat non-leaded package，QFN）70、以及四侧扁平封装72被示出安装在PCB 52上。根据系统要求，利用第一和第二级封装形式的任何组合配置的半导体封装的任何组合、以及其它电子部件，可以被连接到PCB 52。在一些实施例中，电子器件50包括单个附着的半导体封装，虽然其它实施例要求多互连封装。通过在单个衬底上组合一个或多个半导体封装，制造商可以将预先制作的部件并入电子器件和系统中。因为所述半导体封装包括复杂功能，所以可以利用更便宜的部件和流水线制造工艺来制造电子器件。所得到的器件较少可能失效并且制造起来花费较少，对用户而言导致更低的成本。
图2a-2c示出示范性半导体封装。图2a示出安装在PCB 52上的DIP 64的更多细节。半导体管芯74包括包含模拟或数字电路的有源区，所述模拟或数字电路被实现为根据管芯的电设计形成在管芯内并且被电互连的有源器件、无源器件、导电层、和介电层。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及形成在半导体管芯74的有源区内的其它电路元件。接触焊盘76是导电材料（例如铝（AL）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）、或银（Ag））的一个或多个层，并且电连接到形成在半导体管芯74内的电路元件。在DIP 64的组装期间，利用金硅共晶层或粘附材料（例如热的环氧或环氧树脂）将半导体管芯74安装到中间载体78。封装体包括绝缘封装材料，例如聚合物或陶瓷。导体引线80和线结合82在半导体管芯74和PCB 52之间提供电互连。密封剂84被沉积在封装上用于通过防止湿气与粒子进入所述封装以及污染管芯74或线结合82来进行环境保护。
图2b示出安装在PCB 52上的BCC 62的更多细节。半导体管芯88利用底层填充材料或环氧树脂粘附材料92被安装到载体90上。线结合94在接触焊盘96和98之间提供第一级封装互连。模塑料或密封剂100被沉积在半导体管芯88和线结合94上以为所述器件提供物理支撑和电隔离。接触焊盘102利用电解电镀或无电极电镀这样合适的金属沉积形成在PCB 52的表面上以防止氧化。接触焊盘102电连接到PCB 52中的一个或多个导电信号迹线54。凸块104被形成在BCC 62的接触焊盘98与PCB 52的接触焊盘102之间。
在图2c中，利用倒装芯片型第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区108包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计形成的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及在有源区108内的其它电路元件。半导体管芯58通过凸块110被电连接和机械连接到载体106。
BGA 60 利用凸块112电连接和机械连接到具有BGA型第二级封装的PCB 52。半导体管芯58通过凸块110、信号线114、以及凸块112电连接到导电信号迹线54。模塑料或密封剂116被沉积在半导体管芯58和载体106上以为所述器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电轨迹的短导电路径以便减小信号传播距离、降低电容、并且改善总的电路性能。在另一个实施例中，半导体管芯58可以在没有中间载体106的情况下利用倒装芯片型第一级封装被以机械和电的方式直接连接到PCB 52。
图3a-3j示出从WLCSP的顶面形成导电通路的过程。在图3a中，衬底或载体120包含临时或牺牲基底材料，例如硅、聚合物、聚合物复合材料、金属、陶瓷、玻璃、玻璃纤维环氧树脂、氧化铍、或其它合适的低成本、刚性材料，用于结构支撑。可选的界面层122形成在载体120上，作为可利用紫外（UV）光或热释放的临时粘性结合层。
在图3b中，半导体管芯或部件124安装到界面层122且接触焊盘126和介电层128面向载体120。半导体管芯124是已经被电学地和机械地测试以符合设计规范的已知良好的部件（KGU）。半导体管芯124具有有源表面129，其包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面129内的其它电路元件以实现模拟电路或数字电路，例如数字信号处理器（DSP）、ASIC、存储器、或其它信号处理电路。半导体管芯124也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。在另一实施例中，分立半导体部件可以被安装到界面层122和载体120。
图3c示出利用浆料印刷（paste printing）、压缩模塑、传递模塑、液体密封剂模塑、真空层压、或其它合适的施加器（applicator）沉积在半导体管芯124和载体120上的密封剂或模塑料130。密封剂130可以是具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、聚合物、LCP（液晶聚合物）膜、或其它聚合物复合材料。密封剂130在半导体管芯124的与有源表面129相对的后表面132上延伸。密封剂130不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。
在图3d中，通过化学腐蚀、机械剥离、CMP、机械研磨、热烘、激光扫描、或湿法脱模来除去载体120和界面层122。利用PVD、CVD、印刷、旋涂、喷涂、层压或热氧化在密封剂130和半导体管芯124上形成可选的绝缘或钝化层136。绝缘层136可以是一层或多层的二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、五氧化二钽（Ta2O5）、氧化铝（Al2O3）、低温固化（小于250℃）的聚合物电介质、紫外（UV）光可固化的聚合物电介质、干膜聚合物电介质、或其它具有类似绝缘和结构特性的材料。通过显影、刻蚀或激光钻孔工艺除去绝缘层136的一部分以暴露接触焊盘126，或其它具有类似绝缘和结构特性的材料。通过显影、刻蚀或激光钻孔工艺除去绝缘层136的一部分以暴露接触焊盘126。
使用图案化和PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在绝缘层136和接触焊盘126上形成导电层138。导电层138可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。导电层138电连接到半导体管芯124的接触焊盘126并且用作再分配层（RDL）以扩展半导体管芯124的电连接性。RDL 138具有小于30微米（μm）的细间距。
利用PVD、CVD、印刷、旋涂、喷涂、层压或热氧化在绝缘层136和导电层138上形成绝缘或钝化层140。绝缘层140可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、低温固化（小于250℃）的聚合物电介质、UV光可固化的聚合物电介质、干膜聚合物电介质、或其它具有类似绝缘和结构特性的材料。通过显影、刻蚀或激光钻孔工艺除去绝缘层140的一部分以暴露导电层138。绝缘层136和140以及导电层138构成装配互连结构142。临时载体144，例如高温胶带（100o到250℃）、玻璃、Si、箔、或粘合剂，被形成、结合、或层压在绝缘层140和导电层138上，用于结构支撑。
在图3e中，研磨器146从半导体管芯124的后表面132除去体材料和密封剂130的一部分，直到管芯厚度小于300 μm。在研磨工艺之后，半导体管芯124的后表面132与密封剂130的顶表面共面，如图3f所示。在另一个实施例中，背面研磨可以发生在图3c中的密封之后，或者背面研磨被省略，将密封剂130留在半导体管芯124的后表面132上。
在图3g中，利用PVD、CVD、印刷、旋涂、喷涂、层压或热氧化将绝缘或钝化层150形成在密封剂130和半导体管芯124的后表面132上。绝缘层150可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、低温固化（小于250℃）的聚合物电介质、UV光可固化的聚合物电介质、干膜聚合物电介质、或其它具有类似绝缘和结构特性的材料。在密封剂130保留在半导体管芯124上的情况下，可以省略绝缘层150。
使用图案化和PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在绝缘层150上形成导电层152。导电层152可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。导电层152用作RDL以扩展电连接性。RDL 152能够具有小于30微米（μm）的细线/间距。
利用PVD、CVD、印刷、旋涂、喷涂、层压或热氧化将绝缘或钝化层154形成在绝缘层150和导电层152上。绝缘层154可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、低温固化（小于250℃）的聚合物电介质、UV光可固化的聚合物电介质、干膜聚合物电介质、或其它具有类似绝缘和结构特性的材料。通过显影、刻蚀或激光钻孔工艺除去绝缘层154的一部分以暴露导电层152。绝缘层150和154以及导电层152构成装配互连结构156。
在另一个实施例中，在将半导体管芯124安装到载体120时密封剂130经历背面研磨，并且在装配互连结构142之前形成绝缘层150。可替换地，不执行背面研磨，并且密封剂130的在半导体管芯124的后表面132上延伸的部分用作绝缘层150。
在图3h中，保护层158形成在绝缘层154上。保护层158可以是水可漂洗的（water rinseable）材料，例如Hogomax 002。利用激光钻孔、机械钻孔或深反应离子刻蚀（DRIE）形成通过保护层158、装配互连结构156、密封剂130和装配互连结构142且部分地进入载体144的多个通路160。保护层158保护通路160进入装配互连结构156的入口且载体144保护通路160离开装配互连结构142的出口。
在图3i中，在形成通路160之后通过刻蚀或衬底清洗工艺除去载体144和保护层158。在通路160中形成导电层162作为导电通路164。在一个实施例中，导电通路164形成在通路160的侧壁上。可替换地，导电层162完全填充通路160。可选的导电层168形成在绝缘层154上并电连接到导电通路164。可选的导电层170形成在绝缘层140上并电连接到导电通路164。使用回蚀（etch back）或选择性图案化和PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺形成导电层162、168和170。在一个实施例中，导电层162、168和170同时使用无电极Cu电镀、之后是电解Cu电镀的相同双电镀工艺以降低成本。导电层162、168和170也可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。
在图3j中，利用PVD、CVD、旋涂、喷涂、层压或热氧化将绝缘或钝化层172形成在通路160中以及导电层168和170上。通路160可以使用真空填充用于完全绝缘填充。绝缘层172可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、低温固化（小于250℃）的聚合物电介质、UV光可固化的聚合物电介质、干膜聚合物电介质、或其它具有类似绝缘和结构特性的材料。通过显影、刻蚀或激光钻孔工艺除去绝缘层172的一部分以暴露导电层168和170。
使用蒸发、电解电镀、无电极电镀、球滴（ball drop）或丝网印刷工艺在导电层170上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，或其组合，以及可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层170。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块174。在一些应用中，凸块174二次回流以改善到导电层170的电接触。所述凸块也可以被压缩结合到导电层170。凸块174表示一种可以形成在导电层170上的互连结构。所述互连结构也可以使用结合线、导电胶、柱形凸块、微凸块、或其它电互连。
在WLCSP 176中，装配互连结构156通过导电通路164电连接到装配互连结构142和半导体管芯124。通过激光钻孔或机械钻孔利用在入口点和出口点上的保护层来形成导电通路164。导电层162、168和170同时使用相同的双Cu电镀工艺以降低成本。
图4示出类似于图3j的特征的WLCSP 180，其中在安装到图3b中的载体120之前，RDL 182形成在接触焊盘126和有源表面129上。WLCSP 180遵循图3b-3j中描述的类似工艺，除了绝缘层136和导电层138的形成。在这种情况下，细间距RDL 152形成在位于半导体管芯124的一侧的装配互连结构156中。装配互连结构142不具有细间距RDL。
图5示出类似于图4中描述的特征的WLCSP 186，其中分立半导体部件188被安装并电连接到导电层170。分立半导体部件188可以是有源器件，例如晶体管和二极管，或者是无源器件，例如电容器、电阻器和电感器。
图6a-6d示出从下装配互连结构的底面形成导电通路的过程。继续图3d，利用激光钻孔、机械钻孔或DRIE来形成通过载体144、装配互连结构142和密封剂130的多个通路190。载体144保护通路190进入装配互连结构142的入口并且密封剂130保护通路160离开装配互连结构142的出口。
在图6b中，研磨器191除去密封剂130的一部分以打开通路190。
在图6c中，利用PVD、CVD、印刷、旋涂、喷涂、层压或热氧化将可选的绝缘或钝化层192形成在密封剂130和半导体管芯124的后表面132上。绝缘层192可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、低温固化（小于250℃）的聚合物电介质、UV光可固化的聚合物电介质、干膜聚合物电介质、或其它具有类似绝缘和结构特性的材料。可替换地，背面研磨工艺可以使密封剂130的一部分保留在半导体管芯124的后表面132上作为背面绝缘层。
在图6d中，通过刻蚀、剥离或脱模工艺除去载体144。导电层194形成在通路190中作为导电通路196。在一个实施例中，导电通路196形成在通路190的侧壁上。可替换地，导电层194完全填充通路190。导电层198形成在绝缘层192上并电连接到导电通路196。导电层200形成在绝缘层140上并电连接到导电通路196。使用回蚀或选择性图案化和PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺形成导电层194、198和200。在一个实施例中，导电层194、198和200同时使用无电极Cu电镀、之后是电解Cu电镀的相同双电镀工艺以降低成本。导电层194、198和200也可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。
利用PVD、CVD、旋涂、喷涂、层压或热氧化将绝缘或钝化层202形成在通路190中以及导电层198和200上。通路190可以使用真空填充用于完全绝缘填充。绝缘层202可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、低温固化（小于250℃）的聚合物电介质、UV光可固化的聚合物电介质、干膜聚合物电介质、或其它具有类似绝缘和结构特性的材料。通过显影、刻蚀或激光钻孔工艺除去绝缘层202的一部分以暴露导电层198和200。
使用蒸发、电解电镀、无电极电镀、球滴或丝网印刷工艺在导电层200上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，或其组合，以及可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层200。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块204。在一些应用中，凸块204二次回流以改善到导电层200的电接触。所述凸块也可以被压缩结合到导电层200。凸块204表示一种可以形成在导电层200上的互连结构。所述互连结构也可以使用结合线、导电胶、柱形凸块、微凸块、或其它电互连。
在WLCSP 206中，导电层198通过导电通路196电连接到装配互连结构142和半导体管芯124。通过激光钻孔或机械钻孔利用在入口点和出口点上的保护层来形成导电通路196。导电层194、198和200同时使用相同的双Cu电镀工艺以降低成本。
虽然已经详细说明本发明的一个或多个实施例，但是本领域技术人员将理解的是，在不脱离由下列权利要求所阐述的本发明的范围的情况下可以对那些实施例进行变型和修改。

Claims (25)

1. 一种制造半导体器件的方法，包括：
提供临时载体；
在临时载体上安装半导体管芯且有源表面面向临时载体；
在临时载体和半导体管芯上沉积密封剂；
除去临时载体；
在有源表面和密封剂上形成第一互连结构；
在密封剂和半导体管芯的与有源表面相对的后表面上形成第二互连结构；
形成通过第二互连结构、密封剂和第一互连结构的多个通路；
在所述通路中形成第一导电层以电连接第一互连结构和第二互连结构；以及
在第一互连结构和第二互连结构上形成第一绝缘层。
2. 根据权利要求1的方法，还包括：
在形成所述通路之前在第一互连结构上形成第一保护层；以及
在形成所述通路之前在第二互连结构上形成第二保护层。
3. 根据权利要求1的方法，其中形成第一互连结构包括：
在有源表面和密封剂上形成第二绝缘层；
利用无电极电镀和电解电镀在第二绝缘层上形成第二导电层；
在第二绝缘层和第二导电层上形成第三绝缘层；以及
在第三绝缘层和第二导电层上形成第三导电层。
4. 根据权利要求1的方法，其中形成第二互连结构包括：
在密封剂和半导体管芯的后表面上形成第二绝缘层；
利用无电极电镀和电解电镀在第二绝缘层上形成第二导电层；
在第二绝缘层和第二导电层上形成第三绝缘层；以及
在第三绝缘层和第二导电层上形成第三导电层。
5. 根据权利要求1的方法，还包括在所述通路中形成第一绝缘层。
6. 根据权利要求1的方法，还包括在第一互连结构上安装分立半导体部件。
7. 根据权利要求1的方法，还包括在将半导体管芯安装到临时载体上之前在有源表面上形成第二导电层。
8. 一种制造半导体器件的方法，包括：
提供载体；
在载体上安装半导体管芯；
在载体和半导体管芯上沉积密封剂；
除去载体；
在密封剂和半导体管芯的第一表面上形成第一互连结构；
在密封剂和半导体管芯的与半导体管芯的第一表面相对的第二表面上形成第二互连结构；
形成通过第二互连结构、密封剂和第一互连结构的多个通路；
在所述通路中形成第一导电层以电连接第一互连结构和第二互连结构；以及
在第一互连结构和第二互连结构上形成第一绝缘层。
9. 根据权利要求8的方法，还包括在形成所述通路之前在第一互连结构上形成保护层。
10. 根据权利要求8的方法，还包括在形成所述通路之前在第二互连结构上形成保护层。
11. 根据权利要求8的方法，还包括除去半导体管芯的第二表面和密封剂的一部分。
12. 根据权利要求8的方法，形成第一互连结构包括：
在第一表面和密封剂上形成第二绝缘层；
利用无电极电镀和电解电镀在第二绝缘层上形成第二导电层；
在第二绝缘层和第二导电层上形成第三绝缘层；以及
在第三绝缘层和第二导电层上形成第三导电层。
13. 根据权利要求8的方法，其中形成第二互连结构包括：
在密封剂和半导体管芯的第二表面上形成第二绝缘层；
利用无电极电镀和电解电镀在第二绝缘层上形成第二导电层；
在第二绝缘层和第二导电层上形成第三绝缘层；以及
在第三绝缘层和第二导电层上形成第三导电层。
14. 根据权利要求8的方法，还包括在所述通路中形成第一绝缘层。
15. 一种制造半导体器件的方法，包括：
提供载体；
在载体上安装半导体管芯；
在载体和半导体管芯上沉积密封剂；
除去载体；
在密封剂和半导体管芯的第一表面上形成第一互连结构；
形成通过第一互连结构且部分地通过密封剂至半导体管芯的与半导体管芯的第一表面相对的第二表面上的某一位置的多个通路；
除去密封剂在半导体管芯的第二表面上的部分以打开所述通路；
在所述通路中形成第一导电层；
在密封剂和半导体管芯的第二表面上形成第二互连结构；以及
在第一互连结构和第二互连结构上形成第一绝缘层。
16. 根据权利要求15的方法，其中形成第一互连结构包括：
在第一表面和密封剂上形成第二绝缘层；
利用无电极电镀和电解电镀在第二绝缘层上形成第二导电层；
在第二绝缘层和第二导电层上形成第三绝缘层；以及
在第三绝缘层和第二导电层上形成第三导电层。
17. 根据权利要求15的方法，其中形成第二互连结构包括：
在密封剂和半导体管芯的第二表面上形成第二绝缘层；
利用无电极电镀和电解电镀在第二绝缘层上形成第二导电层；
在第二绝缘层和第二导电层上形成第三绝缘层；以及
在第三绝缘层和第二导电层上形成第三导电层。
18. 根据权利要求15的方法，还包括在所述通路中形成第一绝缘层。
19. 根据权利要求15的方法，还包括在第一互连结构上安装分立半导体部件。
20. 一种半导体器件，包括：
半导体管芯；
沉积在半导体管芯上的密封剂；
形成在密封剂和半导体管芯的第一表面上的第一互连结构；
形成在密封剂和半导体管芯的与半导体管芯的第一表面相对的第二表面上的第二互连结构；
被形成为通过第二互连结构、密封剂和第一互连结构以电连接第一互连结构和第二互连结构的多个导电通路；
形成在第一互连结构和第二互连结构上的第一绝缘层。
21. 根据权利要求20的半导体器件，其中半导体管芯的第二表面和密封剂的一部分被除去。
22. 根据权利要求20的半导体器件，其中第一互连结构包括：
形成在第一表面和密封剂上的第二绝缘层；
利用无电极电镀和电解电镀形成在第二绝缘层上的第一导电层；
形成在第二绝缘层和第一导电层上的第三绝缘层；和
形成在第三绝缘层和第一导电层上的第二导电层。
23. 根据权利要求20的半导体器件，其中第二互连结构包括：
形成在密封剂和半导体管芯的第二表面上的第二绝缘层；
利用无电极电镀和电解电镀形成在第二绝缘层上的第一导电层；
形成在第二绝缘层和第一导电层上的第三绝缘层；和
形成在第三绝缘层和第一导电层上的第二导电层。
24. 根据权利要求20的半导体器件，其中第一绝缘层形成在所述通路中。
25. 根据权利要求20的半导体器件，还包括安装在第一互连结构上的分立半导体部件。
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