CN1459857A - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN1459857A
CN1459857A CN03101292A CN03101292A CN1459857A CN 1459857 A CN1459857 A CN 1459857A CN 03101292 A CN03101292 A CN 03101292A CN 03101292 A CN03101292 A CN 03101292A CN 1459857 A CN1459857 A CN 1459857A
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semiconductor chip
semiconductor device
terminal surface
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板东晃司
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

半导体器件(1)具备有开口(6)的管芯底座(5)、被定位于开口(6)处的半导体芯片(21)以及半导体芯片(31)。半导体芯片(21)具有端子面(21a)及位于与端子面(21a)相反一侧的非端子面(21b)。半导体芯片(31)具有面对非端子面(21b)和管芯底座(5)的非端子面(31a)及位于与非端子面(31a)相反一侧的端子面(31b)。提供了设计自由度高的、并且高密度安装半导体芯片的半导体器件。

Description

半导体器件
[发明的背景]
[发明的领域]
本发明一般涉及半导体器件，更特定地说，涉及具有固定在管芯底座上的半导体芯片的半导体器件。
[背景技术的说明]
安装有多个半导体芯片的半导体器件称为MCP(多芯片封装)。为实现小型化或高速工作，MCP要求在同一封装内高密度地安装半导体芯片。而且，这类半导体器件曾在特开2001-127244上作为多芯片半导体器件予以公开展示。
图14是展示在特开2001-127244上的多芯片半导体器件的平面图。图15是沿图14中的XV-XV线剖开的多芯片半导体器件的剖面图。
参见图14及图15，多芯片半导体器件101具有从外围向中心延伸的多条内部引线103和在中心形成的岛102。岛102由四角延伸来的悬吊引线102a支撑，悬吊引线102a与内部引线103在外围成为一体，形成框架部(图上未示出)。由岛102、悬吊引线102a、内部引线103及框架部形成引线框架。在岛102的中央部形成开口107。
在横跨开口107的状态下设置上侧芯片106。下侧芯片105被设置成被容纳在开口107内。这样来设置上侧芯片106及下侧芯片105时，使得上侧芯片106及下侧芯片105的有源元件面106a及105a面朝向同一方向。上侧芯片106及下侧芯片105的有源元件面106a及105a经键合丝104与内部引线103进行电连接。
在上述多芯片半导体器件101中，上侧芯片106大面积地覆盖下侧芯片105的有源元件面105a。因此，下侧芯片105的有源元件面105a之中只有与上侧芯片106不重叠的区域105b可由键合丝104与内部引线103连接。如设置此类限制，就不能自由地进行多芯片半导体器件101的键合设计，使键合丝104的布线变得繁杂。
另外，在多芯片半导体器件101上装载半导体芯片的场合，必须考虑下侧芯片105及上侧芯片106的形状或重叠的形态，使得下侧芯片105的有源元件面105a与上侧芯片106产生不重叠的区域105b。为此，在多芯片半导体器件101中，上侧芯片106及下侧芯片105的平面形状被形成为长方形，以上侧芯片106及下侧芯片105各自的长方形的长边相互正交的方式设置在岛102上。这样，如在半导体芯片的形状或重叠的形态方面设置此类限制，则进行半导体器件的设计就受到很大的制约。
[发明的概要]
因此，本发明的目的在于解决上述课题，提供设计自由度高的，并且能够高密度地安装半导体芯片的半导体器件。
本发明的半导体器件具有：有开口的管芯底座、被定位于开口处的第1半导体芯片以及第2半导体芯片。第1半导体芯片有作为端子面的第1面和位于与第1面相反一侧的第2面。第2半导体芯片有面向第2面和管芯底座的第3面以及位于与第3面相反一侧并且作为端子面的第4面。
按照如此构成的半导体器件，由于第1半导体芯片与第2半导体芯片被设置在管芯底座上，使得作为端子面的第1面与第4面相互背靠背地设置在管芯底座上，因而端子面不会与第1或第2半导体芯片重叠。因此，可以在作为端子面的第1面及第4面的整个表面上进行第1及第2半导体芯片的键合。另外，端子面与第1及第2半导体芯片重叠而变窄，但这不可能使键合设计受到限制。另外，在设计第1及第2半导体芯片的形状或组合时，亦不受端子面设置因素的制约。管芯底座上有开口，开口决定第1半导体芯片的位置，管芯底座开口的厚度与第1半导体芯片的厚度有重叠部分，因而使半导体器件的整个高度相应地变薄，变薄的厚度相当于重叠的厚度。
另外，理想情况是，半导体器件还具有：将与第1及第4面连接起来的键合丝、与键合丝连接的引线端子、以及使第1和第2半导体芯片、引线端子的一部分、键合丝及管芯底座等被覆盖起来而设置的树脂。按照如此构成的半导体器件，将第1及第2半导体芯片设置在管芯底座上，将键合丝连接到独立于管芯底座而形成的引线端子上，所以键合工序中产生的热量可由半导体芯片有效地发散出去。另外，通过将第1和第2半导体芯片安装在管芯底座上，所以安装的抗扭强度增强。另外，将键合丝使用于第1或第2半导体芯片与引线端子的连接，因而半导体芯片的定位误差可被键合丝吸收掉，所以可以提高半导体芯片的定位的自由度。
通过参照附图的后述的本发明的详细说明，本发明的上述和其它的目的、特征、方面和优点会变得更加明白。
[附图的简单说明]
图1为示出本发明实施例1的半导体器件的剖面图。
图2～图9示出图1所示半导体器件的制造方法的工序，图2、图8及图9为斜视图，图3～图7为剖面图。
图10为示出本发明实施例2的半导体器件的剖面图。
图11为示出本发明实施例3的半导体器件的剖面图。
图12为示出本发明实施例4的半导体器件的剖面图。
图13为示出本发明实施例5的半导体器件的剖面图。
图14为示出在特开2001-127244中展示的多芯片半导体器件的平面图。
图15为示出沿图14中XV-XV线的多芯片半导体器件的剖面图。
优选实施例的形态
以下参见附图来说明本发明的实施例。
(实施例1)
请参见图1，半导体器件1具有管芯底座5、半导体芯片21及31、引线端子3、键合丝41及密封树脂51。管芯底座5与引线端子3之间相隔规定的间隔而形成。开口6的剖面形状为长方形，是按着可容纳半导体芯片21的大小形成的。开口6要与半导体芯片21的剖面形状一致，其剖面形状为正方形或多边形均可。半导体芯片31具有端子面31b和在其反面形成的非端子面31a。半导体芯片31通过粘合剂22而被设置，使得其非端子面31a面向管芯底座5的一个面。半导体芯片21具有端子面21a和在其反面形成的非端子面21b。半导体芯片21通过粘合剂22而被设置，使得其非端子面21b面向半导体芯片31的非端子面31a。半导体芯片21被设置成定位于由管芯底座5上形成的开口6处。半导体芯片21例如为高速存储器；半导体芯片31例如为CPU(中央处理装置)。作为粘合剂22，可以使用粘合用的膜或膏状的粘合剂。
半导体芯片21的端子面21a与引线端子3的一个面通过多条键合丝41进行电连接。半导体芯片31的端子面31b与引线端子3的另一面通过多条键合丝41进行电连接。设有覆盖半导体芯片21和31、管芯底座5、键合丝41及引线端子3的一部分的密封树脂51。被密封树脂51覆盖的引线端子3的一部分上包括连接键合丝41与引线端子3的所有部分。密封树脂51系在环氧树脂、硅树脂或硅环氧混合树脂内根据需要与固化剂或充填剂等添加剂混合而被使用。例如，环氧树脂方面典型的有酚醛环氧树脂、酚醛苯酚树脂等。另外，硅环氧混合树脂是指环氧树脂与硅树脂按规定比例混合而成的树脂。
另外，管芯底座5与引线端子3通过设置有规定的台阶而被形成。这是为了在将半导体芯片21及31固定于管芯底座5的状态下，使端子面21a与引线端子3的一个面的台阶同端子面31b与引线端子3的另一面的台阶相等。藉此，可以使距引线端子3的一个面的密封树脂51的厚度与距另一面的密封树脂51的厚度相等。然而，台阶的大小由弯曲引线端子3的形状，或半导体芯片21及31的厚度等任意地决定，并不限于图1中所示的台阶。另外，与这种目的无关，不设台阶亦可。
本发明实施例1的半导体器件1具备：具有开口6的管芯底座5；由开口6定位的作为第1半导体芯片的半导体芯片21；以及作为第2半导体芯片的半导体芯片31。半导体芯片21具有作为端子面的第1面的端子面21a以及位于端子面21a相反一侧的作为第2面的非端子面21b。半导体芯片31具有与非端子面21b和管芯底座5面对面的作为第3面的非端子面31a以及位于与非端子面相反一侧的作为的第4面的端子面31b。
半导体器件1还具有与端子面21a及31b连接的键合丝41、连接到键合丝41的引线端子3以及密封树脂51。密封树脂51被设置成覆盖半导体芯片21和31、引线端子3的一部分、键合丝41以及管芯底座5。
密封树脂51包括由环氧树脂、硅树脂以及硅环氧混合树脂构成的树脂组中的至少一种。
接下来，说明半导体器件1的制作方法。
请参见图2，准备铁-镍(Fe-Ni)合金板或铜(Cu)合金板7。对合金板7进行冲压或刻蚀处理，加工成规定的形状。加工后的合金板7具有由框架2及引线端子3构成的引线框架4以及管芯底座5。管芯底座5靠从框架2的四角延伸的管芯底座支撑部5a来支撑。在管芯底座5的中心部形成剖面形状为长方形的开口6。开口6被形成为能够容纳半导体芯片21的大小。自框架2向管芯底座5的周围形成多条引线端子3。
请参见图3，图3是沿图2中的III-III线的剖面图。管芯底座5与引线端子3之间设有间隙，并形成规定的台阶。
请参见图4，在半导体芯片31的非端子面31a上涂敷粘合剂22。在横跨管芯底座5上形成的开口6的状态下，将半导体芯片31固定在管芯底座5上。
请参见图5，在半导体芯片21的非端子面21b上涂敷粘合剂22。将半导体芯片21对半导体芯片31的非端子面31a进行固定，使得半导体芯片21被定位于开口6处。另外，在将粘合膜用作粘合剂22的场合，在半导体芯片21的非端子面21b上可不涂敷粘合剂22，将半导体芯片21固定在半导体芯片31上。
请参见图6，用超声键合法将半导体芯片21的端子面21a与引线端子3的一个面经键合丝41进行电连接。用金(Au)线作键合丝41。同样，将半导体芯片31的端子面31b与引线端子3的另一面经键合丝41进行电连接。
请参见图7，半导体芯片21及31、管芯底座5、键合丝41以及引线端子一部分被密封树脂51覆盖。
请参见图8，在外层上镀锡(Sn)。通过引线端子3上镀锡可提高耐氧化性和耐腐蚀性。
请参见图9，从框架2切断引线端子3。被设置在四角的管芯底座支持部5a也从框架2切断。引线端子3向规定的方向弯曲。图1是图9中沿I-I线的剖面图。经以上各个工序，半导体器件1即被制成。
按照如此构成的半导体器件，端子面21a及31b与半导体芯片21或31重叠，不存在可进行键合的区域变窄的可能性。因此，在键合设计方面不受制约，并可以防止键合丝41的布线处理变得繁杂。另外，在决定半导体芯片的形状或重叠的组合时，不以设置端子面为理由而受到制约。
另外，由于半导体芯片21被定位于管芯底座5上形成的开口6处，半导体器件1的整个高度可减薄相当于半导体芯片21与管芯底座5重叠厚度的部分。尤其在移动电话，便携式信息终端(PDA：个人数字助理)，或笔记本个人计算机等领域，强烈要求组装在其内部的半导体器件的薄型化。但是，单纯地为了减薄半导体芯片等各结构部件，在制作上看来有一定的限制。另外，管芯底座是在半导体器件制造的中间工序中为固定半导体芯片而设置的，从而半导体芯片的整个非端子面没有必要固定在管芯底座上，局部地固定在管芯底座上即可。于是，通过在管芯底座5上设置开口6，将半导体芯片21定位于开口6处可实现半导体器件1的薄型化。
另外，在用粘合膜作粘合剂22的场合，在固定半导体芯片21时，也可不再次使用粘合剂22，因而可以简化制造工艺，还可减少粘合剂22的用量。
另外，半导体芯片21和31已固定在管芯底座5上，管芯底座5是隔离引线端子3而设置的，在用键合丝连接半导体芯片21及31与引线端子3的工序中所产生的热量能够高效率地散去。藉此，可以防止半导体芯片21及31因发热而造成的损害。另外，半导体芯片21及31与引线端子3的连接是用键合丝41进行的，因而半导体芯片21及31的定位误差可被键合丝41吸收掉。因此，可以防止因半导体芯片21及31的定位产生制造方面的误差而引起的键合工序中所出现的弊病。
另外，密封树脂所含的环氧树脂等树脂有很好的电绝缘性，粘合性、耐药品性及耐热性等，可防止与密封树脂51内部的半导体芯片21及31与外部引起物理性或化学性接触的弊端。
(实施例2)
请参见图10，实施例2的半导体器件60在实施例1的半导体器件1上还具有无源元件61。半导体芯片21的端子面21a上设置无源元件61。无源元件61为电阻元件、电容元件或电感元件。
本发明实施例2的半导体器件60还具有在端子面21a上设置的元源元件61。
按照如此构成的半导体器件，可以得到实施例1中所记载的效果。另外，通过将无源元件61的电阻值、电容值或电感值取规定的值，并通过将它们连接到半导体芯片21的端子面21a，可以得到预期的电路结构。
(实施例3)
请参见图11，实施例3的半导体器件70在实施例1的半导体器件1上还具有晶体管71。在半导体芯片21的端子面21a上设置晶体管71。晶体管71的引线端子71a与引线端子3由键合丝72进行电连接。
本发明实施例3的半导体器件70还具有在端子面21a上设置的晶体管71，晶体管71与引线端子3进行电连接。
按照如此构成的半导体器件，除了实施例1所记载的效果之外，还能弥补半导体芯片21的输出电流之不足。
(实施例4)
请参见图12，实施例4的半导体器件80在实施例1的半导体器件1上还具有半导体芯片81。在半导体芯片21的端子面21a上，通过金属凸点82设置半导体芯片81。半导体芯片81具有端子面81b及在其相反一侧形成的非端子面81a。半导体芯片81被设置成使端子面81b与半导体芯片21的端子面21a面对面配置。密封树脂51被设置成覆盖半导体芯片21、31及81、管芯底座5、键合丝4以及引线端子3的一部分。
本发明实施例4的半导体器件80还具有装载在端子面21a之上的作为第3半导体芯片的半导体芯片81。
按照如此构成的半导体器件，除了实施例1记载的效果之外，在同一封装内可更高密度地安装半导体芯片，能实现半导体器件的小型化或高速工作性能。
(实施例5)
请参见图13，实施例5的半导体器件90在设置密封树脂51的形态上与实施例4的半导体器件80不同。
在半导体芯片21的端子面21a上，通过金属凸点82设置半导体芯片81。密封树脂51仅使半导体芯片81的非端子面81a暴露在外，而将非端子面81a以外的半导体芯片81、21及31、管芯底座5、键合丝41以及引线端子3的一部分覆盖起来。
本发明实施例5的半导体器件90还具有：与端子面21a和31b连接的键合丝41；连接到键合丝41的引线端子3；以及为使半导体芯片21及31、半导体芯片81的一部分、引线端子3的一部分、键合丝41以及管芯底座5等覆盖起来而设置的密封树脂51。半导体芯片81具有面向端子面21a的端子面81b以及作为独立于端子面81b而设置的端子的面的非端子面81a。半导体芯片81的非端子面81a暴露在密封树脂51之外。
按照如此构成的半导体装置，可以得到记载于实施例4中的效果，另外，因半导体芯片81的非端子面81a暴露在密封树脂51之外，可以使半导体器件90的整个高度进一步变薄。
这次公开的实施例在全部方面可认为是例示性的而不是限制性的。本发明的范围由权利要求书的范围而不是由上述实施例的说明来表示，其意图是包含与权利要求的范围均等的意义和范围的全部的变更。

Claims (8)

1.一种半导体器件，其特征在于，具备：
有开口的管芯底座；
有作为端子面的第1面和位于与上述第1面相反一侧的第2面、被定位于上述开口处的第1半导体芯片；以及
有面向上述第2面和上述管芯底座的第3面和位于与上述第3面相反一侧、并且是端子面的第4面的第2半导体芯片。
2.如权利要求1所述的半导体器件，其特征在于，还具备：
与上述第1及第4面连接的键合丝；
连接到上述键合丝的引线端子；以及
为覆盖上述第1及第2半导体芯片、上述引线端子的一部分、上述键合丝以及上述管芯底座而设置的树脂。
3.如权利要求2所述的半导体器件，其特征在于：
上述树脂包括从环氧树脂、硅树脂及硅环氧混合树脂构成的组中选择的至少一种。
4.如权利要求2所述的半导体器件，其特征在于：
还包括在上述第1或第4面上设置的晶体管，上述晶体管与上述引线端子进行电连接。
5.如权利要求1所述的半导体器件，其特征在于：
还包括在上述第1或第4面上设置的无源元件。
6.如权利要求1所述的半导体器件，其特征在于：
还包括在上述第1或第4面上装载的第3半导体芯片。
7.如权利要求6所述的半导体器件，其特征在于：
还具备：
与上述第1及第4面连接的键合丝；
连接到上述键合丝的引线端子；以及
为覆盖上述第1及第2半导体芯片、上述第3半导体芯片的一部分、上述引线端子的一部分、上述键合丝及上述管芯底座而设置的树脂，
上述第3半导体芯片包括面向上述第1或第4面的端于面，未形成独立于上述端子面而设置的端子的面，
上述未形成端子的面暴露在上述树脂之外。
8.如权利要求7所述的半导体器件中，其特征在于：
上述树脂包括从环氧树脂、硅树脂及硅环氧混合树脂构成的组中选择的至少一种。
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