TW563240B - Semiconductor device - Google Patents
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- TW563240B TW563240B TW091124208A TW91124208A TW563240B TW 563240 B TW563240 B TW 563240B TW 091124208 A TW091124208 A TW 091124208A TW 91124208 A TW91124208 A TW 91124208A TW 563240 B TW563240 B TW 563240B
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Description
563240
[發明之領域] 點晶 本發明係關於半導體裝置,尤其是關於具有固定在 塾(die pad)之半導體晶片之半導體裝置者。 [先前技術] (Mul 3 th複數P個:導體晶片之半導體裝置稱為多晶片封妒 (Mujti Chip Package,以下簡稱為虹?)。為實現小型1 或高2作性’ MCP是需要高密度地安裝半導體晶片於同 一封展肢内。在日本特開2〇〇1_1 27 244號公報内有揭示 述之半導體裝置作為多晶片半導體裝置者。 圖14為顯示在日本特開2〇〇 1 -1 27244號公報内所揭示之 多晶片半導體裝置之俯視圖。圖15係顯示沿著圖14中之 XV-XV線上之多晶片半導體裝置之剖視圖。 參考圖14及圖15,多晶片半導體裝置1〇1具備有從外周 向中心延伸之複數條之内部引線丨〇 3及形成在中心之島 1 0 2。島1 〇 2係由自四方延伸之懸吊引線丨〇 2 a所支撐;懸吊 引線1 0 2 a及内部引線1 〇 3係在外周成為一體而形成未圖示 之框架部。由島1 〇 2、懸吊引線1 〇 2 a、内部引線1 0 3及框架 部構成引線架。在島1 〇 2之中央部形成開口 1 〇 7。 以跨越開口 1 0 7的狀態設有上部側晶片1 〇 6。下部側晶片 1 0 5係形成為收容於開口 1 〇 7内。以使上部側晶片1 〇 6及下 部側晶片105之有源元件面106a及l〇5a面向同一方向的方 式,設置上部側晶片1 0 6及下部側晶片1 〇 5。上部側晶片 1 0 6及下部側晶片1 〇 5之有源元件面1 〇 6 a、1 0 5 a,與内部引 線1 0 3係以接合引線1 〇 4電性連接。
\\A312\2d-code\92-01\9l124208.ptd 第5頁 563240 五、發明說明(2) 地ί芸ί :晶片半導體裝置1 °1中’上部侧晶片10 6廣範圍 二::部側晶片105之有源元件面i〇5a。因此,在下部 :曰重,,有源元件面105a當中,只有未與上部側晶片 、卓接。域105b始能介由接合引線104與内部引線1〇3 詈1 0 1夕右/又有"亥種限制則無法自由地設計多晶片半導體裝 之打線接合,恐有使接合引線1G4之配線繁雜之可能 兩ί老ΐ ?載半導體晶片於多晶片半導體裝置1 〇"夺,必 二能,=# 曰曰曰片106及下部側晶片105之形狀或重疊之 Μ便產生丁部側晶片1〇5之有源元件面Mb與上部 = 之區域嶋。因此,在多晶片半導體裝 #成為# t卩側晶片1〇6及下部侧晶片105之平面形狀 h 2 形,上部側晶片1 06及下部侧晶片1 05則以該等 斜车莫之長邊互相垂直交又之狀態設在島102。如此 俨# w Γ sa片之形狀或重疊形態設有限制,則當執行半導 體裝置之設計時會成為很大的限制。 [發明内容] 自t 5 :本發日f :目的在於解決上述問題,其提供設計之 ,且咼始、度地安裝半導體晶片之半導體裝置者。 =本發明之半導體裝置係包括設有開口之黏晶塾,定 2開口之第1半導體晶片及第2半導體晶片。第!半導體 日日片具有作為端子面之第!面,及位於第!面之相反側的第 面。第2半導體晶片具有與黏晶墊相對之第3面,及位於 第3面之相反側的位置且作為端子面之第4面。
563240 、發明說明(3) 、胃依具有上述構成之半導體裝置,第1半導體晶片與第2半 , ^體晶片係設在黏晶墊,使端子面之第1及第4面互相向相 反側’因此,端子面不會與第1或第2半導體晶片重疊。因 、 在作為端子面之第1及第4面之全面可執行第1以及弟2 半導體晶片之打線接合。又,不會發生端子面與第1或第2 半導體晶片重疊而變狹窄使打線接合設計受到限制的情 形。再者,在設計第1或第2半導體晶片之形狀或組合時, 不會受到因設置端子面為理由之限制。又,黏晶墊設有開 口而苐1半導體晶片定位於該開口的關係,可使半導體裝 置之全體高度減少相當於黏晶墊之開口之厚度與第1半導 _ 體晶片厚度重疊之厚度。 又’半導體裝置係更具有與第1及第4面連接之接合引 線’連接於接合引線之引線端子,以及以覆蓋第1及第2半 f體晶片、引線端子之一部分、接合引線及黏晶墊而設之 Μ脂為宜。根據具有上述構成之半導體裝置,由於將第1 及第2半導體晶片設在黏晶墊,並將接合引線連接於與黏 晶塾另行形成之引線端子,因而,可使在接合步驟中所產 生之熱有效地從半導體晶片散熱。又,把第1及第2半導歸 晶片設在黏晶塾之結果,可以增加安裝之抗扭曲強度。^ 者’使用接合引線來連接第1或第2半導體晶片與引線端 子,因此可用接合引線來吸收半導體晶片固定位置之= 差。因此,可提高半導體晶片之固定位置之自由度。、 [實施方式] & 茲參考圖示,說明本發明之實施形態。
C:\2D-CX3DE\92-01\91l24208.ptd 第7頁 563240 五、發明說明(4) (實施形態1 ) 蒼考圖1。半導體裝置1係具備有黏晶墊5、半導體晶片 21及31、引線端子3、接合引線4〗及封裝樹脂51。黏Z 與引線端子3係保持預定之間隔而形成。黏晶墊5之中8=部 形成有開口 6。開口 6係其剖面形狀呈長方形,形: 谷半導體晶片21之大小。開口 6係配合半導體晶片2丨”之剖 ,形狀’其剖面形狀也可以呈正方形或多角形等。半導。體 曰曰片3丨、係具有端子面3 1 b,及形成在相反側之非端子面_ 31a。半導體晶片31係介由黏接劑22而設成其非端子面 相對於黏晶墊5 一方之面。半導體晶片21具有端子面21&,a 及形成在相反側之非端子面21b。半導體晶片21係介由黏 接劑22而設成其非端子面21b相對於半導體晶片3ι之非俨 子面3 1 a、。半導體晶片2 1係定位而設在形成於黏晶墊5之 口 6。半導體晶片2丨係例如快閃記憶體,半導體晶片”汗 =如中央處理單位(Central Processing Unit,以下 ^CPU)者。黏接劑22則使用黏接用薄膜或糊膠狀之黏接 以複數條之接合引線41電性連接半導體晶片21之端子面 引線端子3之一側面。用複數條之接合引線41電性連 妾半導體晶片31之端子面31b與引線端子3之另一側面。# . |έ0^5 . 引線端子3之一部分。在以封裝樹脂51覆蓋之引 ί Ϊ 一部分係完全包含連接接合引線41及引線端子3 之h。封裝樹脂51係以對環氧樹脂1樹脂㈣環氧混 \\A3l2\2d-code\92-01\91124208.ptd 第8頁 I·! 563240 五、發明說明(5) 合樹脂等混合硬化劑或 用環氧樹脂則使用具代丨:::劑而使用。例如’使 等。又,砂产气·曰入ί 酚醛型環氧、酚醛苯酚 夕衣乳此δ树脂係指以預定 及矽樹脂所成者。 疋之比羊〜合裱氧Μ月曰 又,黏晶墊5及引線端子3係保持 之。此乃因把半導體曰Η 91 β Q1 =貝疋之同低差而形成 乂太山 日日片2 1及3 1固定於黏晶墊5之狀能 下,使步而子面21a與引線端子3之 ^之狀: 面3ib與引線端子3之另 低差,及知子 是,可使引線端子3之-側面m差面成/4相等者。於 厚产A i日笪你工 1〗向及另側面之封裝樹脂5 1之 厚度為相’。然而,該高低差之 形狀或丰導鲈b Η 9 1 η 〇 · 1了弓萌⑴綠ί而千d之 於圖Λ Λ 之厚度等可任意決定’並非限定 高:差。不之间低差。又,無論該目的如何,也可不設 口 6根之據/Λ:之實施形態11半導體裝置1係、包括具備有開 乂; iV定位於開口6之第1半導體晶片之半導體晶 ^ V體晶片之半導體晶片3 1。半導體晶片21係 of作為端子面之^面之端子面21a,及位於端子面2u ,才:反側之作為第2面之非端子面21b。半導體晶片31包括 與非端子面21b及黏晶墊5相對之作為第3面之非端子面 31a,及位於非端子面31a之相反侧,且為端子面之作為第 4面之端子面31b。 半‘體裝置1更包括連接於端子面2丨a及3〗b之接合引線 41、連接於接合引線41之引線端子3及封裝樹脂51。封裝 樹脂51係設成覆蓋半導體晶片21及31、引線端子3之一部 \\A312\2d-code\92-01\91124208.ptd 第9頁 563240
分、接合引線4 1及黏晶墊5者。 、曰封裝樹脂51係包含有選自由環氧樹脂,秒樹脂 混合樹脂所成之群中之至少一種者。 及矽環氧 其次,就半導體裝置1之製造方法說明如下。 =圖2 ’準備鐵-鎳(Fe_Ni)合金板或銅( 用衝壓加工或用姓刻處理合金板7而加工成預定之=7。 2 ^後之合金板7具備有由框架2及引線端子3成 線架4及黏晶堅5。黏晶塾5係自框"之四方#成之日引 支禮部5a所支樓。在黏晶塾5之中心部,形成有其=曰塾 狀呈長方形之開口 6。開口 6係形成為可收容半 & =小。。從框架2向黏晶塾5之周緣部有形成複數條 高 間 圖 低 隙 =:=1二所二之:二7二 參考圖4,在半等體晶片31之非端子面31a塗敷黏接劑 。以跨越形成在黏晶墊5之開口 6之狀態固定半導體晶片 3 1於黏晶墊5。 參考圖5,在半導體晶片21之非端子面21b塗敷黏接劑 2 2。將半導體晶片2 1固定在半導體晶片3 j之非端子面 31a,、使半導體晶片21定位於開口6。又,使用黏接用之薄 膜作為黏接劑2 2時,對半導體晶片2丨之非端子面2丨b不必 塗敷黏接劑22,即可將半導體晶片21固定在半導體晶片 3 1 〇
563240
電 面 電 面 ::圖6,利用超音波打線接合法等,藉由接合引線“ 。體!片21之端子面2ia與引線端子3之-側 性連i半線。同樣地’藉由接合引線41 。連接丰V肢日日片31之端子面3lb與引線端子3之另一側 B曰 參考圖7,用封裝樹脂51覆蓋半導體晶片以 塾5、接合引線41及引線端子3之—部分。 ^ 之i考r耐/作為外裝°引線端子3 1經電鍵 <便’其耐乳化性及耐腐蝕性優良。 參考圖9,⑨框架2切斷引線端子3。從框 四 处之黏晶墊支撐部5a。然後,將引線端子 /又 折f。阳為沿著圖9中之Η線所作之之定之方= 之步驟後完成半導體裝置1者。 圖。經上述 根據如此構成之半導體裝置,不會 31b與半導體晶片21或31重疊 Χ 而子面21a及 小的問題。因此,在設計接合時不執會订受打^/之區主域變 止接合引線4 1之配線處理變繁雜。A去 f 片之形狀或重疊組合之際不=到Π置;;定半導體晶 限制。 又"j U °又置碥子面為理由之 又,半導體晶片21係定位於形成在黏晶墊5 係,可以減少半導體裝置!之全體高度;?胃 片21與黏晶墊5重疊厚度之量。尤i/牛導體曰曰 位助理(Personal Digital Assistant,以下口 J = 或筆記型電腦等之領域中,裝設於Α θ’ %為_) n丨之+導體裝置薄
563240 五、發明說明(8) 型化之要求非常強。铁& 各構成組#,則快要;;U純地薄型化半導體晶片等之 製造半導體裝置之中間造之界限…黏晶塾係在 者。因此,不必將半Ξ = 用以固定半導體晶片而設 晶墊’局部性地固定^曰曰曰^非端子面之全面固定在黏 置開口6,把半導體曰曰上塾則可。於是,在黏晶墊5設 導體裝置1之薄型化者 疋位於開口6之結果’可實現半 片2H 5 I ί ί用薄膜作為黏接劑22時’固定半導體晶 片21之際不必再度使用黏接劑22此 驟,又可減少所使用的黏接劑22之量。 再者,將半導體晶片21及31固定於黏晶塾5,黏晶^係 子I而設的關係,可以有效地散熱當使用接合 引Λ連接半導體晶片21、31及引線端子3之步驟中所發 生:熱。⑥是’可以防止半導體晶片21及31因熱所引起之 害处。又,使用接合引線41來連接半導體晶片2丨、3丨及引 線η的關係,可用接合引線41吸收半導體晶片21及31 之定位抉差。因此,可以防止在製造上因半導體晶片2丨及 3 1之疋位發生誤差所導致之在打線接合步驟中所發生之宝 處。 ^ 再者,封裝樹脂51含有之環氧樹脂等之樹脂之電絕緣 性、黏接性、耐化學藥品性或耐熱性等均優良;可防止封 裝樹脂5 1内部之半導體晶片2 1及31與外部發生物理性成化 學性接觸者。 / (實施形態2)
C:\2D-CODE\92-Ol\91124208.ptd
563240 五、發明說明(9) 置6 0係在實施形態1 半導體晶片2 1之端 係電阻元件、電容 置6 0係更具備有設 參考圖10,實施形態2中之半導體| 中之半導體裝置1更設有被動元件61 ^ 子面21a設有被動元件61。被動元彳牛Μ 器元件或電感元件。 有關本發明之實施形態2之半導體# 在端子面21a之被動元件61。 ~ 根據具有上述構造之半導體裝署 記載之效果。又,將被動元件61之雷^,實施形態1, 值設定成預定之值,然後將該等連拯=谷1值或電感 工而夕处婁叮π不丨私而 接於半導體晶片21之綠
子面2 1 a之結果,可以付到所需要之電路 (實施形態3 ) 霉成。 參考圖1 1 ,實施形態3中之 中之半導體裝置1更具備有電 之端子面21a設有電晶體71。 體71之引線端子71a與引線端 半導體裝置7 〇係對實施形態j 日日體71者。在半導體晶片21 由接合引線72電性連接電晶 子3 〇 按照本發明之實施形態3之半導體裳置7〇更具有設在端 子面2 1 a之電晶體71,電晶體71與引線端子3係電性連接。
具有上述構成之半導體裝置為,除了在實施形態丨記載 之效果外’可補充半導體晶片2 1之輸出電流的不足。 (實施形態4 ) 參考圖12,實施形態4中之半導體裝置80係對實施形態] 之半導體裝置1再具備有半導體晶片81。介由金屬突出^ 82 ’對半導體晶片21之端子面21a設有半導體晶片81。半 導體晶片8 1具有與端子面8 1 b相反側形成之非端子面8丨a。
C:\2D-C0DE\92-01\91124208.ptd 第13頁 ^3240 五、發明說明(10) 半導體晶片8 1係設成為其 子面21a相對之狀態。以覆 ”半導體晶片21之端 晶塾5、接合引線41及弓j線;:^導體_^片21、m點 樹脂5 1。 、、'而子3之部分之方式設置封裴 按照本發明之實施形熊 於端子面21a之作為第3半導體晶、置』0係曰更具有搭载 根據上i盖成夕坐、曾 日日之半導體晶片8 1者。 果外,可更高密度地安施形態1中記載之效 (可Λ實現半導體裝置之二 封裝體内,
(貫施形態5) <初uI 參考圖1 3,實施形離5夕主it J3A # m 51之態樣相異於實施;'態4中之半;3 = = 片81二由:屬突出物82設在半導體晶片21之端子面 81aJi ;5」::以只有露出半導體晶片81之非端子面 I*子面仏以外之半導體晶片81、半導 ^ '黏晶塾5、接合引線41以及引線端子3之- 以ϊίΓί:之實施形態5之半導體裝置9°,係更具備有 .^ Λ ^面21 a及31b連接之接合引線41、連接於接合 引^之引線端子3、半導體晶片21及31、半導體晶片81 之邛刀引線端子3之一部分、接合引線41以及黏晶墊5 之方式而設之封裂樹脂51。半導體晶片81係包含相對於端 子面21 a之端子面81b、與端子面81b分開而設之未形成端 子之面之非端子面81a者。半導體晶片81之非端子面8ia係 第14頁 C:\2D-C0DE\92-01\9ll24208.ptd 563240 五、發明說明(11) 從封裝樹脂5 1露出。 根據如此構成之半導體裝置,可得到如同實施形態4之 效果。又,半導體晶片8 1之非端子面8 1 a從封裝樹脂51露 出的關係,更可減低半導體裝置9 0之全體高度。 [元件編號之說明] 1、60、70、80、90 半導體裝置 2 3 4 5 5a 框架 引線端子 引線架 黏晶塾 黏晶墊支撐部 6 7 21 ^ 31 '81 開口 合金板 半導體晶片 21a 、 31b 、 81b 21b 、 31a 、 81a 22 41 51 61 端子面 非端子面 黏接劑 接合引線 封裝樹脂 被動元件 71 71a 72 82 電晶體 引線端子 接合引線 金屬突出物
C:\2D-C0DE\92-01\91124208.ptd 第15頁 563240 五、發明說明(12) 101 102 102a 103 104 105 105a 105b 106 106a 107 多晶片半導體裝置 島 懸吊引線 内部引線 接合引線 下部側晶片 有源元件面 區域 上部側晶片 有源元件面 f 開口
C:\2D-C0DE\92-01\91124208.ptd 第 16 頁 563240 圖式簡單說明 圖1為顯示本發明實施形態1之半導體裝置之剖視圖。 圖2至圖9為顯示圖示之半導體裝置之製造方法之步驟; 其中,圖2、圖8及圖9為立體圖,而圖3至圖7為剖視圖。 圖1 0為顯示本發明實施形態2之半導體裝置之剖視圖。^ 圖1 1為顯示本發明實施形態3之半導體裝置之剖視圖。 圖1 2為顯示本發明實施形態4之半導體裝置之剖視圖。 圖1 3為顯示本發明實施形態5之半導體裝置之剖視圖。 圖14為顯示如日本特開20 0 1 - 1 2 7 244號公報揭示之多晶 片半導體裝置之俯視圖。 圖15為顯示沿著圖14中之XV-XV線上之多晶片半導體裝 f 置之剖視圖。
C:\2D-C0DE\92-01\9I124208.ptd 第 17 頁
Claims (1)
- — ----—— 六、申請專利範圍 1 · 一種半導體裝置, ^ ^ 設有開口之黏晶墊;其包含有··具備 第1半導體晶片,具有 第1面之相反側之第/、作為端子面之Η 7 π 笤2本道蛐η 面而定位^、, 弟1面,及位於前述 弟2丰導體晶片,農 疋位在耵述開D· ^ 第3面,及位於第3而、有與前述第2面邀^ i 面者。、43面之相反側之位述黏晶塾相對之 且作為端子面之第4 以::1:專利範圍第1項之丰道 用以復盍與前述第、之+導體裝置, 接靖之引線端子及第“;,之接合弓丨線Λ 線鈿子之一部分 ^ 及第2半導體晶片、前述引 脂。 接合弓丨線以及前述黏晶塾而設之樹 3. 如申請專利範圍 脂係含有選自環氧樹 員之半導體裝置,其中,前述樹 群中之至少一種者。曰、矽樹脂及矽環氧混合樹脂所成之 4. 如申請專利範圍 設在前述第1或第4面之、曰半導體裝置,其中,更具有 子係電性連接者。之電晶體;前述電晶體與前述引線端 5·如申請專利範圍第llf 設在前述第1或第4 、+導體哀置’其中’更具有 6.如申請專利範圍ils件者。 安裝在前述第!咬第4ϊλ之半導體裝置,其中,更具有 7如由往ί次第之第3半導體晶片者。 • νη利範圍第6項之半導體裝置,1中,费真有 與前述第1及第4面中更具 面連接之接合引線;連接於前述接合引線 第18頁 C:\2D-CODE\92-01\91124208.ptd 563240 六、申請專利範圍 之引線端子;以及以覆蓋前述第1及第2半導體晶片;前述 第3半導體晶片之一部分;前述引線端子之一部分;前述 接合引線及黏晶墊之方式而設之樹脂, 前述第3半導體晶片係包含與前述第1或第4面相對之端 子面、與前述端子面分開而設之未形成有端子之面, 前述未形成有端子之面為從前述樹脂露出者。 8.如申請專利範圍第7項之半導體裝置,其中,前述樹 脂係含有選自環氧樹脂、矽樹脂及矽環氧混合樹脂所成之 群中之至少一種者。C:\2D-CODE\92-01\91124208.ptd 第 19 頁
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JP2002142739A JP2003332522A (ja) | 2002-05-17 | 2002-05-17 | 半導体装置 |
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JP (1) | JP2003332522A (zh) |
KR (1) | KR20030089411A (zh) |
CN (1) | CN1459857A (zh) |
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US7405468B2 (en) * | 2003-04-11 | 2008-07-29 | Dai Nippon Printing Co., Ltd. | Plastic package and method of fabricating the same |
US7489219B2 (en) | 2003-07-16 | 2009-02-10 | Marvell World Trade Ltd. | Power inductor with reduced DC current saturation |
US7307502B2 (en) * | 2003-07-16 | 2007-12-11 | Marvell World Trade Ltd. | Power inductor with reduced DC current saturation |
US7023313B2 (en) | 2003-07-16 | 2006-04-04 | Marvell World Trade Ltd. | Power inductor with reduced DC current saturation |
US8324872B2 (en) | 2004-03-26 | 2012-12-04 | Marvell World Trade, Ltd. | Voltage regulator with coupled inductors having high coefficient of coupling |
JP4668729B2 (ja) * | 2005-08-17 | 2011-04-13 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US20070200210A1 (en) * | 2006-02-28 | 2007-08-30 | Broadcom Corporation | Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in integrated circuit (IC) packages |
US7535110B2 (en) * | 2006-06-15 | 2009-05-19 | Marvell World Trade Ltd. | Stack die packages |
JP2009252815A (ja) * | 2008-04-02 | 2009-10-29 | Toppan Printing Co Ltd | 複合リードフレーム構造体及び半導体装置 |
WO2009143492A1 (en) * | 2008-05-23 | 2009-11-26 | Statek Corporation | Piezoelectric resonator |
CN103390563B (zh) * | 2013-08-06 | 2016-03-30 | 江苏长电科技股份有限公司 | 先封后蚀芯片倒装三维系统级金属线路板结构及工艺方法 |
CN103489792B (zh) * | 2013-08-06 | 2016-02-03 | 江苏长电科技股份有限公司 | 先封后蚀三维系统级芯片倒装封装结构及工艺方法 |
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JP3266815B2 (ja) * | 1996-11-26 | 2002-03-18 | シャープ株式会社 | 半導体集積回路装置の製造方法 |
US6441495B1 (en) * | 1997-10-06 | 2002-08-27 | Rohm Co., Ltd. | Semiconductor device of stacked chips |
JPH11330347A (ja) | 1998-05-20 | 1999-11-30 | Rohm Co Ltd | 半導体ic |
KR100277438B1 (ko) * | 1998-05-28 | 2001-02-01 | 윤종용 | 멀티칩패키지 |
JP3235589B2 (ja) | 1999-03-16 | 2001-12-04 | 日本電気株式会社 | 半導体装置 |
JP2001127244A (ja) | 1999-11-01 | 2001-05-11 | Nec Corp | マルチチップ半導体装置およびその製造方法 |
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JP2003332522A (ja) | 2003-11-21 |
KR20030089411A (ko) | 2003-11-21 |
CN1459857A (zh) | 2003-12-03 |
US20030214050A1 (en) | 2003-11-20 |
US6661091B1 (en) | 2003-12-09 |
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