CN2461149Y - 一种堆叠集成电路 - Google Patents

一种堆叠集成电路 Download PDF

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CN2461149Y
CN2461149Y CN00265904U CN00265904U CN2461149Y CN 2461149 Y CN2461149 Y CN 2461149Y CN 00265904 U CN00265904 U CN 00265904U CN 00265904 U CN00265904 U CN 00265904U CN 2461149 Y CN2461149 Y CN 2461149Y
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integrated circuit
piling
lower floor
substrate
signal input
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陈文铨
周镜海
陈明辉
叶乃华
彭国峰
黄宴程
王志峰
李文赞
吴志成
彭镇滨
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Kingpak Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

一种堆叠集成电路,其有一基板;一设有一下表面和一上表面的下层集成电路;数条导线,其一端连接在下层集成电路上,另一端连接在基板上;一具有一下表面和一上表面的上层集成电路,该下表面两侧有凹槽。上层集成电路堆叠在下层集成电路上时,由于数条导线位于上层集成电路的凹槽内,使其堆叠时不会压着导线,且下集成电路粘着到基板上时,溢胶将填充在下集成电路的凹槽内,而减少溢胶的区域,可使集成电路的封装体积减小。

Description

一种堆叠集成电路
本实用新型涉及一种堆叠集成电路，特别是指一种便于将集成电路有效堆叠，在制造上更为方便的堆叠集成电路。
在科技领域，各项科技产品都追求轻、薄、短、小，因此，集成电路的体积越小越理想，越符合产品的需求。而以往集成电路即使体积小，也只能并列式地连接在电路板上，而在有限的电路板上，无法增加集成电路的数量，所以，要使产品达到更为轻、薄、短、小的目的，将有其困难之处。
将若干个集成电路予以叠合使用，可达到轻、薄、短小的目的，然而，若干个集成电路叠合时，上层集成电路将会压到下层集成电路的导线，以致将影响到下层集成电路的信号传递。
现有的一种堆叠集成电路，如图1所示，其包括一基板10、一下层集成电路12、一上层集成电路14、数条导线16及一隔离层18。下层集成电路12设在基板10上，上层集成电路14由隔离层18叠合在下层集成电路12上方，使下层集成电路12与上层集成电路14形成一适当的间距20，如此，导线16即可连接在下层集成电路12边缘，使上层集成电路14叠合在下层集成电路12上时，不致于压损导线16。
此种结构在制造时必须先制作隔离层18，再将其粘着在下层集成电路12上，而后再将上层集成电路14粘着在隔离层18上，所以，其制造程序较为复杂，生产成本较高。
本实用新型的主要目的在于提供一种堆叠集成电路，其可方便地将集成电路堆叠，提高生产效率。
本实用新型的另一目的在于提供一种堆叠集成电路，其可避免产生溢胶，而影响导电性。
本实用新型的又一目的在于提供一种堆叠集成电路，其可减少溢胶区域，减小封装体积。
本实用新型的目的是通过如下技术方案实现的：
一种堆叠集成电路，其包括一具有一第一表面及一第二表面的基板，第一表面有一用来与堆叠集成电路连接的信号输入端，第二表面有一连接在电路板上的信号输出端；一设有一下表面及一上表面的下层集成电路，其下表面粘设在基板的第一表面上，上表面具有多个焊垫；数条导线，其一端连接到下层集成电路的焊垫上，另一端连接到基板的信号输入端；一具有一下表面及一上表面的上层集成电路，其下表面两侧有凹槽，其粘着在下层集成电路的上表面与下层集成电路形成堆叠，数条导线位于凹槽内。
所述的基板信号输出端为球栅阵列式的金属球；数条导线连接在下层集成电路的第二表面边缘；数条导线是以楔形焊接与下层集成电路连接的；下集成电路的下表面两侧有用来填充当其粘着在基板上时产生的溢胶的凹槽；数条导线是以球打线的方式焊接在下层集成电路焊垫上的；基板的第一面上设有一有信号输入端的凸缘，导线连接在该凸缘的信号输入端和上层集成电路之间。
本实用新型的上层集成电路堆叠在下层集成电路上时，由于导线位于上层集成电路的凹槽内，其堆叠时不会压到导线，且下集成电路粘着到基板上时，溢胶将填充到下集成电路的凹槽内，而减少溢胶的区域，可使集成电路的封装体积减小。
下面结合附图对本实用新型作进一步的详细说明。
图1为现有堆叠集成电路的剖视图。
图2为本实用新型堆叠集成电路的剖视图。
图3为本实用新型堆叠集成电路的第一实施例示意图。
图4为本实用新型堆叠集成电路的第二实施例示意图。
图5为一晶圆的上视图。
图6为本实用新型堆叠集成电路制造的示意图。
如图2所示，为本实用新型堆叠集成电路的剖视图，包括有一基板22，其具有一第一表面24，其有一信号输入端26，用以与集成电路连接，一第二表面28，其有一信号输出端30，用以与电路板连接(图未显示)。基板22的第二表面28的信号输出端30可为数个球栅阵列金属球，用以与电路板连接。
一设有一下表面36及一上表面3 8的下层集成电路34，下表面36是由粘胶层40粘着在基板22的第一表面24上，而上表面38具有数个焊垫42，用以与基板22连接，使下集成电路34的信号传递到基板22的第一表面24的信号输入端26。
数条导线44，一端连接在下层集成电路34的焊垫42上，另一端连接在基板24的信号输入端26，在本实施例中，数条导线44是以楔形打线的方式(Wedge Bond)连接在下层集成电路34的边缘，也可以球打线(Ballbond)的方式连接在下集成电路34的焊垫42上，使下层集成电路34的信号传递到基板22的第一表面24的信号输入端26。
一上层集成电路46具有一上表面48及一下表面50，而下表面50两侧形成有凹槽51，该上层集成电路46是由粘着层52粘着在下集成电路34的上表面38，而与下层集成电路34形成堆叠，而数条导线44则位于凹槽51内，不致因上层集成电路46下压而损坏。
如图3所示，下层集成电路34两侧具有凹槽51，当该下层集成电路34粘着在基板22的第一表面24时，粘胶层40的胶量可能控制不当，所形成的溢胶54可填充在下层集成电路34的凹槽51内，而不会覆盖住基板22的信号输入端26，影响导线44的打线作业。如此，即可解决现有因溢胶而必须将基板22加大的情形，所以本实施例的堆叠装置可达到与晶片尺寸相同大小(Chip Scale Package)的封装结构。
如图4所示，基板22的第一表面24上形成有一凸缘54，而基板22的信号输入端26在凸缘54上，使上层集成电路46的导线44可连接在凸缘54上，从而使连接在上层集成电路46与基板22间的导线44缩短，使信号的传递更佳。
如图5所示，晶圆56上具有多个集成电路46，每一集成电路46间形成有一切割线58，因此，如图6所示，在制造上层集成电路46的凹槽51时，首先用一较宽的切割刀具自切割线58切开一不贯穿晶圆56的凹槽51，再用一较窄的切割刀具自切割线58切穿整个晶圆56，如此，可将晶圆56上的每一个集成电路46分开，并使每一集成电路46形成凹槽51。
由此，本实用新型堆叠集成电路可使上层集成电路46叠合在下层集成电路34上时，连接下层集成电路34与基板22的导线44恰位于上层集成电路46两侧的凹槽51内，而不会被上层集成电路46压损。同时由于下层集成电路34的下表面两侧有凹槽51，避免了溢胶的情形，使基板22可制成与晶片相同尺寸大小的堆叠封装。

Claims (7)

1、一种堆叠集成电路，其特征在于：其包括有：
一具有一第一表面及一第二表面的基板，该第一表面有一用来与堆叠集成电路连接的信号输入端，第二表面有一连接在电路板上的信号输出端；
一设有一下表面及一上表面的下层集成电路，其下表面粘设在基板的第一表面上，上表面具有多个焊垫；
数条导线，其一端连接到下层集成电路的焊垫上，另一端连接到基板的信号输入端；
一具有一下表面及一上表面的上层集成电路，其下表面两侧有凹槽，其粘着在下层集成电路的上表面与下层集成电路形成堆叠，数条导线位于凹槽内。
2、如权利要求1所述的堆叠集成电路，其特征在于：所述的基板信号输出端为球栅阵列式的金属球。
3、如权利要求1所述的堆叠集成电路，其特征在于：所述的数条导线连接在下层集成电路的第二表面边缘。
4、如权利要求3所述的堆叠集成电路，其特征在于：所述的数条导线是以楔形焊接与下层集成电路连接的。
5、如权利要求1所述的堆叠集成电路，其特征在于：所述的下集成电路的下表面两侧有用以当其粘着在基板上时填充溢胶的凹槽。
6、如权利要求1所述的堆叠集成电路，其特征在于：所述的数条导线是以球打线的方式焊接在下层集成电路焊垫上的。
7、如权利要求1所述的堆叠集成电路，其特征在于：所述的基板的第一面上设有一有信号输入端的凸缘，导线连接在该凸缘的信号输入端和上层集成电路之间。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103515257A (zh) * 2012-06-18 2014-01-15 智瑞达科技（苏州）有限公司 高密度半导体封装结构的封装方法
CN105789146A (zh) * 2014-12-16 2016-07-20 中芯国际集成电路制造(上海)有限公司 一种堆叠式芯片封装结构
CN106784293A (zh) * 2017-01-13 2017-05-31 江苏汇博机器人技术股份有限公司 一种堆叠式压电陶瓷

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103515257A (zh) * 2012-06-18 2014-01-15 智瑞达科技（苏州）有限公司 高密度半导体封装结构的封装方法
CN105789146A (zh) * 2014-12-16 2016-07-20 中芯国际集成电路制造(上海)有限公司 一种堆叠式芯片封装结构
CN106784293A (zh) * 2017-01-13 2017-05-31 江苏汇博机器人技术股份有限公司 一种堆叠式压电陶瓷
CN106784293B (zh) * 2017-01-13 2019-08-23 江苏汇博机器人技术股份有限公司 一种堆叠式压电陶瓷

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