CN2459754Y - 一种集成电路 - Google Patents

一种集成电路 Download PDF

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Publication number
CN2459754Y
CN2459754Y CN00265909U CN00265909U CN2459754Y CN 2459754 Y CN2459754 Y CN 2459754Y CN 00265909 U CN00265909 U CN 00265909U CN 00265909 U CN00265909 U CN 00265909U CN 2459754 Y CN2459754 Y CN 2459754Y
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integrated circuit
substrate
groove
adhesive layer
signal input
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陈文铨
周镜海
陈明辉
叶乃华
彭国峰
黄宴程
王志峰
彭镇滨
李文赞
吴志成
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Kingpak Technology Inc
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Kingpak Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种集成电路,其包括有一基板;一包括一下表面及一上表面的集成电路,其下表面两侧各有一凹槽,上表面有数个焊垫;一用来使集成电路的下表面粘着在基板上的粘胶层;数条连接在集成电路的焊垫与基板间的导线。粘胶层将集成电路粘着在基板上时,粘胶层的溢胶将填充在集成电路的凹槽内,而不会覆盖住基板的信号输入端,因此,可有效防止集成电路封装的溢胶问题。

Description

一种集成电路
本实用新型涉及一种集成电路，特别指一种可便于将集成电路粘着在基板上，而有效解决溢胶问题，使集成电路可达到与晶片尺寸相同(ChipScale Package)的封装效果的集成电路。
在科技领域，各项科技产品都需要轻、薄、短小，集成电路的体积是越小越理想，使其符合产品的需求。因此，一种与晶片尺寸相同(Chip ScalePackage)的封装技术，可使集成电路封装后的体积缩小，而达到轻薄短小的需求。
如图1所示，现有的集成电路的封装、或与晶片尺寸相同(Chip ScalePackage)的封装技术，将集成电路10粘着在基板12上时，由于粘胶层14可能控制不好，常造成粘胶溢出集成电路10的粘着面，而直接溢至基板12上，溢出的溢胶16可能覆盖住基板12的信号输入端18，而影响到导线20的打线作业。因此，一般为了避免基板12的信号输入端18被溢胶16覆盖住，通常将基板12扩大，使其上的信号输入端18远离集成电路10，如此，溢胶16将不致于覆盖住基板12的信号输入端18，而解决上述溢胶的问题。
如此，整个集成电路的封装体积，将随着基板12的扩大而变大，无法达到所谓与晶片尺寸相同(Chip Scale Package)的封装，无法达到轻、薄、短、小的需求。
本实用新型的主要目的在于提供一种集成电路，其可有效解决溢胶的问题。
本实用新型的另一目的在于提供一种集成电路，其具有降低封装尺寸的效果，以达到轻、薄、短、小的目的。
本实用新型的目的是通过如下技术方案实现的：一种集成电路，其包括：
一具有一第一表面及一第二表面的基板，该第一表面设有信号输入端，第二表面设有连接到电路板的信号输出端；
一包括有一下表面及一上表面的集成电路，该下表面两侧有一凹槽，而上表面设有数个焊垫；
一用来使集成电路的下表面粘着在基板第一表面上的粘胶层；
数条连接在集成电路的焊垫和基板的信号输入端间的导线；
一将数条导线和集成电路包覆住的封胶层。
所述的基板的第二表面的信号输出端有球栅阵列金属球(Ball GridArray)；集成电路粘着到基板时，粘胶层所形成的溢胶是填充在集成电路下表面的凹槽内的；集成电路的下表面的凹槽为垂直状；集成电路的下表面的凹槽为斜面状；集成电路的下面的凹槽是用切割刀切割而成的。
由于粘胶层集成电路粘着在基板上时，粘胶层的溢胶将填充在集成电路的凹槽内，而不会覆盖住基板的信号输入端，因此，可有效防止集成电路封装的溢胶问题。同时，不需要加大基板，所以具有降低封装尺寸的效果，以达到轻、薄、短小的需求。
下面结合附图对本实用新型作进一步详细的说明。
图1为现有集成电路封装的剖视示意图。
图2为本实用新型集成电路的剖视示意图。
图3为本实用新型集成电路的一实施例示意图。
图4为晶圆的上视图。
图5为本实用新型集成电路的切割示意图。
如图2所示，本实用新型集成电路，包括有一基板24，其具有一第一表面26及一第二表面28，第一表面26有一信号输入端30，用以将集成电路32的信号传递到基板24，第二表面28有一信号输出端34，用来将集成电路32的信号传递到电路扳上，信号输出端34可为球栅阵列式的金属球(Ball Grid Array)。
集成电路32有一下表面36及上一表面38，集成电路32的下表面36两侧各有一垂直状的凹槽40，且下表面36粘设在基板24的第一表面26上，上表面38具有数个焊垫39，用来与基板24连接。
数条导线42一端连接在集成电路32的焊垫39上，另一端连接在基板24的信号输入端30上，使集成电路32的信号传递到基板24上，数条导线42可用楔形打线(Wedge Bond)连接在集成电路32的焊垫39上，该数条导线42位于集成电路32的上表面38的边缘，另外，该数条导线42也可用球打线(ball bond)方式连接在集成电路32的焊垫39上。
粘胶层44是涂布在集成电路32与基板24之间，用来使集成电路32粘着在基板24上，由于一般粘胶层44的胶量控制不易，使得粘胶层44的胶常有溢出集成电路32的下表面36的问题，本实用新型中粘胶层44所溢出的溢胶46将填充在集成电路32的凹槽40内，而不会有覆盖基板24的信号输入端30的问题。
如图3所示，集成电路32的凹槽40可为斜面状，当溢胶量可以控制为较少时，溢胶可完全的填充在凹槽40内，而不会使凹槽40有较大的间隙存在。
封胶层47是用来包覆集成电路32与数条导线42的，使集成电路32与教条导线可以被保护住。
本实用新型集成电路的集成电路32下有凹槽40，在封装时不会有溢胶的问题产生，可便于封装、制造，并可降低生产成本，提高生产优良率；由于可解决溢胶的问题，因此，基板24可制成与晶片尺寸相同，而达到与晶片尺寸相同大小的封装(Chip Scale Package)，使产品满足轻、薄、短、小的需求。

Claims (6)

1、一种集成电路，其特征在于：其包括：
一具有一第一表面和一第二表面的基板，该第一表面设有信号输入端，第二表面设有连接到电路板的信号输出端；
一包括有一下表面和一上表面的集成电路，该下表面两侧各有一凹槽，而上表面设有数个焊垫；
一用来将集成电路的下表面粘着在基板第一表面上的粘胶层；
数条用来连接集成电路的焊垫与基板的信号输入端的导线；
一将数条导线和集成电路包覆住的封胶层。
2、如权利要求1所述的集成电路，其特征在于：所述的基板的第二表面的信号输出端有球栅阵列金属球。
3、如权利要求1所述的集成电路，其特征在于：所述的集成电路粘着到基板时，粘胶层所形成的溢胶是填充在集成电路下表面的凹槽内的。
4、如权利要求1所述的集成电路，其特征在于：所述的集成电路的下表面的凹槽为垂直状。
5.如权利要求1所述的集成电路，其特征在于：所述的集成电路的下表面的凹槽为斜面状。
6.如权利要求1所述的集成电路，其特征在于：所述的集成电路的下表面的凹槽是用切割刀切割而成的。
CN00265909U 2000-12-14 2000-12-14 一种集成电路 Expired - Fee Related CN2459754Y (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102290700A (zh) * 2011-04-25 2011-12-21 东莞市维美德电子材料有限公司 一种多层连接器自动装配方法、自动装配设备及该多层连接器
CN102903684A (zh) * 2011-07-27 2013-01-30 矽品精密工业股份有限公司 半导体晶片、芯片、具有该芯片的半导体封装件及其制法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102290700A (zh) * 2011-04-25 2011-12-21 东莞市维美德电子材料有限公司 一种多层连接器自动装配方法、自动装配设备及该多层连接器
CN102290700B (zh) * 2011-04-25 2013-07-31 东莞市维美德电子材料有限公司 一种多层连接器自动装配方法、自动装配设备
CN102903684A (zh) * 2011-07-27 2013-01-30 矽品精密工业股份有限公司 半导体晶片、芯片、具有该芯片的半导体封装件及其制法

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