CN2461240Y - 积体电路堆叠构造 - Google Patents

积体电路堆叠构造 Download PDF

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CN2461240Y
CN2461240Y CN00264806.7U CN00264806U CN2461240Y CN 2461240 Y CN2461240 Y CN 2461240Y CN 00264806 U CN00264806 U CN 00264806U CN 2461240 Y CN2461240 Y CN 2461240Y
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integrated circuit
lower floor
substrate
metal ball
stacking construction
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CN00264806.7U
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陈文铨
周镜海
陈明辉
叶乃华
彭国峰
黄宴程
黄富勇
林钦福
郑清水
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Kingpak Technology Inc
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Kingpak Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H01L2224/48991—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on the semiconductor or solid-state body to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

本实用新型涉及积体电路,使便利制造、成本降低。基板有一第一表面及一第二表面,第一表面形成有一讯号输入端,第二表面形成有一与电路板连接的讯号输出端;下层积体电路设有一第一表面及一第二表面,第一表面粘设于基板的第一表面,第二表面具有一个以上焊垫;该等导线一端电连接于下层积体电路的焊垫上,另端电连接于基板的第一表面的讯号输入端。用于电器。

Description

积体电路堆叠构造
本实用新型涉及积体电路。
已有的一积体电路构造如图1所示：其有一基板10、一下层积体电路12、一上层积体电路14、多条导线16及隔离层18。下层积体电路12设于基板1 0上，上层积体电路14藉隔离层18叠合于下层积体电路12上方，使下层积体电路12与上层积体电路14形成一间距，导线16电连接于下层积体电路12边缘，使上层积体电路14叠合于下层积体电路12上时，不会压坏导线16。但是这种构造，制造上必须先制作隔离层18，再将其粘着于下层积体电路12，而后再将上层积体电路14粘于隔离层18，故制造复杂，成本增加。
本实用新型的目的是提供一种制造较便利，成本可降低的积体电路堆叠构造。
本实用新型的目的是这样实现的：积体电路堆叠构造，其包括：一基板、一下层积体电路、一条以上导线、一上层积体电路及金属球，其特征是：基板有一第一表面及一第二表面，第一表面形成有一讯号输入端，第二表面形成有一与电路板连接的讯号输出端；下层积体电路设有一第一表面及一第二表面，第一表面粘设于基板的第一表面，第二表面具有一个以上焊垫；该等导线一端电连接于下层积体电路的焊垫上，另端电连接于基板的第一表面的讯号输入端；金属球设于下层积体电路的第二表面上，上层积体电路叠设于金属球上，与下层积体电路形成堆叠状态。
上述设计，由于金属球的设置，避免了导线被上层积体电路压坏，达到了制作较便利，成本可降低的有益效果。
下面以附图、实施例再进一步说明。
图1为已有积体电路堆叠构造剖视图；
图2为本实用新型剖视图；
图3为本实用新型基板与下层积体电路组合图；
图4为本实用新型另一剖视示意图。
如图2-4所示：本实用新型包括：一基板24、一下层积体电路32、一条以上导线40、一上层积体电路44及金属球30、42，其特征是：基板24有一第一表面26及一第二表面28，第一表面26形成有一讯号输入端29，第二表面28形成有一与电路板连接的讯号输出端；下层积体电路32设有一第一表面34及一第二表面36，第一表面34粘设于基板24的第一表面26，第二表面36具有一个以上焊垫38；该等导线40一端电连接于下层积体电路32的焊垫38上，另端电连接于基板24的第一表面26的讯号输入端29；金属球42设于下层积体电路32的第二表面36上，上层积体电路44叠设于金属球42上，与下层积体电路32形成堆叠状态。基板24的讯号输出端为球栅阵列式的金属球30；该等导线40一端电连接于下层积体电路32的第二表面36边缘；该等导线40以楔形打线焊接于下层积体电路32的焊垫38上；金属球42焊接于下层积体电路32的第二表面36的四周；金属球42为焊接于该等导线40上；金属球42上涂布有粘着层并与上层积体电路44粘合；该等导线40以球焊接的方式打线于下层积体电路32的焊垫38上；上层积体电路44电连接于基板24的第一表面26上；上层积体电路44以打线方式电连接于基板24的第一表面26上。并且上层积体电路44藉由多个金属球42与下层积体电路32形成隔离状态，使其不会压到多条导线40。这样，优点是：1、可以现有球栅阵列封装设备形成金属球于下层积体电路，不必另行购置制造阻隔层的设备；2、金属球作为阻隔层，制造便利；3、不必另行购置隔离层粘着设备，因此成本大为降低。

Claims (10)

1、积体电路堆叠构造，其包括：一基板、一下层积体电路、一条以上导线、一上层积体电路及金属球，其特征是：基板有一第一表面及一第二表面，第一表面形成有一讯号输入端，第二表面形成有一与电路板连接的讯号输出端；下层积体电路设有一第一表面及一第二表面，第一表面粘设于基板的第一表面，第二表面具有一个以上焊垫；该等导线一端电连接于下层积体电路的焊垫上，另端电连接于基板的第一表面的讯号输入端；金属球设于下层积体电路的第二表面上，上层积体电路叠设于金属球上，与下层积体电路形成堆叠状态。
2、如权利要求1所述的积体电路堆叠构造，其特征是：其中，基板的讯号输出端为球栅阵列式的金属球。
3、如权利要求1所述的积体电路堆叠构造，其特征是：其中，该等导线一端电连接于下层积体电路的第二表面边缘。
4、如权利要求3所述的积体电路堆叠构造，其特征是：其中，该等导线以楔形打线焊接于下层积体电路的焊垫上。
5、如权利要求1所述的积体电路堆叠构造，其特征是：其中，金属球焊接于下层积体电路的第二表面的四周。
6、如权利要求1所述的积体电路堆叠构造，其特征是：其中，金属球为焊接于该等导线上。
7、如权利要求1所述的积体电路堆叠构造，其特征是：其中，金属球上涂布有粘着层并与上层积体电路粘合。
8、如权利要求1所述的积体电路堆叠构造，其特征是：其中，该等导线以球焊接的方式打线于下层积体电路的焊垫上。
9、如权利要求1所述的积体电路堆叠构造，其特征是：其中，上层积体电路电连接于基板的第一表面上。
10、如权利要求9所述的积体电路堆叠构造，其特征是：其中，上层积体电路以打线方式电连接于基板的第一表面上。
CN00264806.7U 2000-12-13 2000-12-13 积体电路堆叠构造 Expired - Fee Related CN2461240Y (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103515252A (zh) * 2012-06-21 2014-01-15 新科金朋有限公司 形成嵌入式sop扇出型封装的半导体器件和方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103515252A (zh) * 2012-06-21 2014-01-15 新科金朋有限公司 形成嵌入式sop扇出型封装的半导体器件和方法
US10217702B2 (en) 2012-06-21 2019-02-26 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming an embedded SoP fan-out package

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