CN2461239Y - 积体电路堆叠装置 - Google Patents

积体电路堆叠装置 Download PDF

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CN2461239Y
CN2461239Y CN00264805U CN00264805U CN2461239Y CN 2461239 Y CN2461239 Y CN 2461239Y CN 00264805 U CN00264805 U CN 00264805U CN 00264805 U CN00264805 U CN 00264805U CN 2461239 Y CN2461239 Y CN 2461239Y
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integrated circuit
lower floor
substrate
stack device
upper strata
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CN00264805U
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陈文铨
彭国峰
张家荣
吴志成
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Kingpak Technology Inc
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Kingpak Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8314—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

本实用新型涉及积体电路,使便于制造。基板有一第一表面及一第二表面,第一表面形成有一讯号输入端,第二表面形成有一讯号输出端;下层积体电路设有一第一表面及一第二表面,第一表面粘设于基板的第一表面上,第二表面有一个以上焊垫;该等导线一端电连接于下层积体电路的焊垫上,另一端电连接于基板的讯号输入端;粘着层涂布于下层积体电路的第二表面,上、下层积体电路间有间距。用于电器。

Description

积体电路堆叠装置
本实用新型涉及积体电路。
已有的积体电路堆叠构造如图1所示：包括有一基板10、一下层积体电路12、一上层积体电路14、多条导线16、17及一隔离层18，下层积体电路1 2设于基板10上，上层积体电路14藉由隔离层18叠合于下层积体电路12上方，使上、下积体电路形成一间距20，导线16电连接于下层积体电路12边缘，使上层积体电路14叠合于下层积体电路12时，不会压坏下层的导线17。但这种结构必须先制作隔离层18，再粘着于下层积体电路12上，而后再上层积体电路14粘着于隔离层18，所以制造程序复杂，成本较高。
本实用新型的目的是提供一种可降低成本，制造较便利的积体电路堆叠装置。
本实用新型的目的是这样实现的：积体电路堆叠装置，其包括：一基板、一下层积体电路、一条以上导线、一粘着层及一上层积体电路；其特征是：基板有一第一表面及一第二表面，第一表面形成有一讯号输入端，第二表面形成有一讯号输出端；下层积体电路设有一第一表面及一第二表面，第一表面粘设于基板的第一表面上，第二表面有一个以上焊垫；该等导线一端电连接于下层积体电路的焊垫上，另一端电连接于基板的讯号输入端；粘着层涂布于下层积体电路的第二表面，其包含有粘着液及填充元件；上层积体电路叠合于下层积体电路的第二表面上，藉由粘着液与下层积体电路粘合固定且藉填充元件的阻隔，使下层积体电路与上层积体电路间形成间距。
上述设计，避免了繁琐的工序，达到了制造较便利的效果。
下面以附图、实施例进一步说明。
图1为已有积体电路堆叠构造示意图；
图2为本实用新型剖视示意图；
图3为本实用新型构造示意图；
图4为本实用新型另一实施例示意图。
如图2-4所示：本实用新型包括：一基板24、一下层积体电路32、一条以上导线40、一粘着层42及一上层积体电路48；其特征是：基板24有一第一表面26及一第二表面28，第一表面26形成有一讯号输入端29，第二表面28形成有一讯号输出端；下层积体电路32设有一第一表面34及一第二表面36，第一表面34粘设于基板24的第一表面26上，第二表面36有一个以上焊垫38；该等导线40一端电连接于下层积体电路32的焊垫38上，另一端电连接于基板24的讯号输入端29；粘着层42涂布于下层积体电路32的第二表面36，其包含有粘着液44及填充元件46；上层积体电路48叠合于下层积体电路32的第二表面36上，藉由粘着液44与下层积体电路32粘合固定且藉填充元件46的阻隔，使下层积体电路32与上层积体电路48间形成间距50。基板24的讯号输出端为球相陈列式的金属环30；该等导线40电连线于下层积体电路32的第二表面36边缘；该等导线40为以楔形焊接打线于下层积体电路32的焊垫38上；粘着层42涂布于下层积体电路32的第二表面36中央部位，且为不规则状的，当固定时将被压平；并且，粘着层42涂布于下层积体电路32的第二表面36四周部位，可得到更稳固连接。

Claims (6)

1、积体电路堆叠装置，其包括：一基板、一下层积体电路、一条以上导线、一粘着层及一上层积体电路；其特征是：基板有一第一表面及一第二表面，第一表面形成有一讯号输入端，第二表面形成有一讯号输出端；下层积体电路设有一第一表面及一第二表面，第一表面粘设于基板的第一表面上，第二表面有一个以上焊垫；该等导线一端电连接于下层积体电路的焊垫上，另一端电连接于基板的讯号输入端；粘着层涂布于下层积体电路的第二表面，其包含有粘着液及填充元件；上层积体电路叠合于下层积体电路的第二表面上，藉由粘着液与下层积体电路粘合固定且藉填充元件的阻隔，使下层积体电路与上层积体电路间形成间距。
2、如权利要求1所述的积体电路堆叠装置，其特征是：其中，基板的讯号输出端为球相陈列式的金属环。
3、如权利要求1所述的积体电路堆叠装置，其特征是：其中，该等导线电连线于下层积体电路的第二表面边缘。
4、如权利要求3所述的积体电路堆叠装置，其特征是：其中，该等导线为以楔形焊接打线于下层积体电路的焊垫上。
5、如权利要求1所述的积体电路堆叠装置，其特征是：其中，粘着层涂布于下层积体电路的第二表面中央部位。
6、如权利要求1所述的积体电路堆叠装置，其特征是：其中，粘着层涂布于下层积体电路的第二表面四周部位。
CN00264805U 2000-12-13 2000-12-13 积体电路堆叠装置 Expired - Lifetime CN2461239Y (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107258014A (zh) * 2015-02-18 2017-10-17 皇家飞利浦有限公司 具有多个堆叠的发光设备的设备

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107258014A (zh) * 2015-02-18 2017-10-17 皇家飞利浦有限公司 具有多个堆叠的发光设备的设备

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Granted publication date: 20011121