JP4903966B2 - フリップチップ接合構造及びフリップチップ接合構造を形成する方法 - Google Patents
フリップチップ接合構造及びフリップチップ接合構造を形成する方法 Download PDFInfo
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- JP4903966B2 JP4903966B2 JP2001566849A JP2001566849A JP4903966B2 JP 4903966 B2 JP4903966 B2 JP 4903966B2 JP 2001566849 A JP2001566849 A JP 2001566849A JP 2001566849 A JP2001566849 A JP 2001566849A JP 4903966 B2 JP4903966 B2 JP 4903966B2
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
Description
【発明の属する技術分野】
本発明はフリップチップ接合構造に関し、更に詳しくは、機械的な変形と接合される表面間にある凹凸の噛み合わせとによって形成される接合構造に関する。
【0002】
【従来の技術・発明が解決しようとする課題】
集積回路(IC)のチップと基板とのフリップチップ接合は普通、電子パッケージ組立品内においてなされている。このような接合の最も一般的な形態は、ICチップ上にあるバンプが基板上に形成されたパッドに冶金的に、通常バンプ材料を溶融して接合される。この方法は強固な接合を提供するが、溶融および固化工程中に橋絡(すなわち、隣接した接合箇所間のショート)するリスクがあるため、接合箇所のピッチを小さくすることが難しい。他の方法として、微粒子フィルムあるいはペーストを用いる方法があり、ペーストあるいはフィルム中の導電性微粒子が樹脂の収縮とともに電気的な接合を行う。この方法は、接合箇所のピッチを減少できるが、微粒子接合の妨害感受性のため、長時間の信頼性に限界があり、規定時間を超えると性能が低下する。
【0003】
【課題を解決するための手段】
本発明は、フリップチップ接合構造を形成する方法であって、
変形可能な材料で構成された第1要素をICチップ上に配設すること、
第1要素と結合する部分に凹凸表面を有し、且つ第1要素に対向する面とICチップ面に垂直な側壁面とこれら面の間のエッジとを有する第2要素を、基板上に配設すること、及び、
第2要素におけるエッジ及び側壁面の周り、並びに前記第1要素と結合する部分の凹凸表面に対して前記第1要素の一部が可塑的な流れを起こすに足りる力で、第1要素及び第2要素を互いに押し付け合うことにより、前記第1要素に対向する面及び前記側壁面とに沿って機械的な噛み合わせをつくること、を含むことを特徴とするフリップチップ接合構造を形成する方法を提供する。
【0004】
前記第1要素は、ICチップ上に形成されたバンプとされ、典型的にはそのようなバンプのセットとされる。特に有用な第1要素の変形可能な材料として、金が挙げられる。前記第2要素は、基板上に形成されたパッドとされる。第2要素は、本発明に従って凹凸が設けられた表面パッドとされる。
【0005】
又本発明は、本発明の方法によって製造されたフリップチップ接合構造を提供する。
【0006】
更に本発明は、チップに接続した第1要素と基板に接続した第2要素とを備えるフリップチップ接合構造であって、第1要素が変形可能な材料であって、第1及び第2要素が、第1要素の変形可能な材料の第2要素の表面の凹凸への機械的な噛み合いによって接合されているフリップチップ接合構造を提供する。
【0007】
【発明の実施の形態】
図1A、1Bに概略的に表されているように、10で示されるフリップチップ接合構造は、第1要素12と第2要素14とを備える。第1要素12はICチップ上に形成されたバンプであり、第2要素14は基板上に形成されたパッドである。第1要素12は、柔軟で変形可能な材料であって、低降伏強さ及び高破断伸びをもつもので構成されているのがさらに好ましい。第2要素14は、通常のめっき表面仕上げがされ、該表面に凹凸16(図では大げさに表されている)が形成された基板パッドを含むものが更に好ましい。凹凸の寸法は普通1μm〜25μmのオーダ−である。バンプは通常の規格材料、すなわち、ある特定の形にされた、約250gの垂直荷重に等しい力がかかった時約25μmを越える塑性変形に耐える材料である。本発明のバンプ用の材料として、金は特に有用である。
【0008】
接合は、第1要素12と第2要素14とを互いに押しつけあい、第1要素から第2要素へ可塑的流れを起こすことによって行われる。第1要素12の高さおよび柔軟さのため、接合が達成した後でもかなりの変形が起こる。従って、結合させるべきバンプ/パッドペアの平面性が劣っていても、接合は首尾よくいく。接合に必要な圧力及び温度は、継ぎ合せる材料の冶金的拡散が要求される従来の熱圧着に必要とされる圧力及び温度に比べると非常に小さい。これらが低減するため、チップ上に起こるダメージが非常に少なくなる。特に同時に行う接合の数が多い場合、ダメージは非常に少なくなる。
【0009】
第1の実施の形態を図2A、2Bに示す。第1要素22が第2要素あるいはトレース28の側壁24およびエッジ26の周りに可塑的に流れることによって、20で示される微細噛み合い形状が形成される。第1要素22の材料の流れは側壁24の周りに起こり、隣接するトレース間の領域には起こらず、同じ面内の垂直方向に起こるのが好ましい。噛み合い形状20は、接合力をあまり増大させず、噛み合う表面積を増大させているため、より強固な接合を提供する。さらに、チップ面に対して垂直方向に付加的に移動するため、複数の継ぎ合せ面の共平面性が劣っていても、容認できる範囲が広い。最後に、該接合は、通常のチップ面に対する水平の噛み合わせに加えて、チップ面に対して垂直方向の面に沿う噛み合わせもあるので、ダイと基板間の垂直方向の相対運動に対して保護されている。
【0010】
第2の実施の形態を図3A、3Bに示す。図中、接合は30で示されている。第1要素32の材料が第2要素34周りに可塑的に流れることによって、接合30が形成される。第2要素34の幅は第1要素32より小さく、従って、第1要素32の材料は、第2要素34の両サイド36、38に可塑的に流れる。
【0011】
第2の参考形態を図4A,4Bに示す。図中、接合は40で示されている。第2要素42のリードの形はV字型で、サブトラクティブエッチング法によって造られる、実際使用されている基板の中で最も典型的な “アンダーカット”リードの形をしているという利点がある。接合40は、第1要素44の材料が第2要素42の周りに可塑的に流れることによって形成される。図示された構成は、トレースの最小幅の制限、特に従来のワイヤボンディング法では必要であった水平域46の最小幅の制限がない。接合40は、バイアパッドに直接、あるいはバイアホールを介して基板の次の低層に結合して形成することも意図されている。
【0012】
図2A、2B、3A、3B、4A、4B中の微細噛み合い形状によって、より小さい力で接合を形成することができ、例えば、図1A、1Bで示されている第1の参考形態に比べて2だけ下がる。このように、圧縮力を低減させると加工中にチップに加わるダメージがより少なくなる。
【0013】
好ましい実施の形態として、接着性樹脂がチップと基板との隙間に塗布される。こうすると、硬化した樹脂によって供給された圧力が、電気接続の長時間保持特性をさらに改良する。接着性樹脂は、継ぎ合わせ面が接合する前に塗布され、前記接合の形成時に硬化する。圧力をかけて樹脂材料を前記継ぎ合わせ面から取り除き、所望の機械的に噛み合った接合を形成する。あるいは、樹脂はアンダーフィル法によって、接合の後に塗布することもできる。
【0014】
好ましい実施の形態において、第1要素12、22、32、42の材料として、Cu、非電着性NiAuおよびAuが好ましい。基板材料としては、片面FR5ラミネート、2面BT−樹脂ラミネートが好ましい。
【0015】
バンプは、前記したように、圧縮変形前は長方形の断面をもつものの他、種々の形状がある。特に2つの有用なものとして、図5、図6に線図で示す。図5は、“階段”形状のものを示し、チップに隣接する部分(べース)が、基板上のパッドに対して押しつけられる部分(先端)より広くなっている。図6は、“スタッドバンプ”形状を示し、ベースの周辺形状が円形で、先端より広くなっている。これらの構造はどちらも、先端の寸法がより小さいので、バンプと基板上の凹凸との追従性(コンプライアンス)が改良され、ベース形状がより広くなっているため、形状安定性が良好である。
【0016】
第2要素は、前記したように、リードでもパッドでもよい。バンプは、バイアホールに電気的に接合している従来のハンダパッドに接合してもよい。別の実施の形態として、第2要素そのものがバイアホールを含んでいてもよい。この実施の形態によれば、ハンダパッドのようなパッドの上にバンプを押しつけるというより、バンプをバイアホール内及び縁にある導電性材料に直接押しつけるため、バイアホールから少し離れて、接合が形成される。こうするとチップ上の面積をより効率的に使えることとなる。バイアホール中の開口は概して、バンプの先端より小さく、従って、バンプはバイアホールに直接プレスされ、バイアホールの中へと変形し始め、接合される。事実、バイアホールはこの構造において、凹凸として働き、バンプはバイアホールより小さいのでバイアホール中に入り込み、従って結合がバイアオープニングのリムの部分に形成される。
【図面の簡単な説明】
【図1A】 チップ接合構造を備える組立品を製造する工程における第1の参考形態を示す断面概略図。
【図1B】 チップ接合構造を備える組立品を製造する工程における第1の参考形態を示す断面概略図。
【図2A】 本発明のチップ接合構造を備える組立品を製造する工程における第1の実施の形態を示す断面概略図。
【図2B】 本発明のチップ接合構造を備える組立品を製造する工程における第1の実施の形態を示す断面概略図。
【図3A】 本発明のチップ接合構造を備える組立品を製造する工程における第2の実施の形態を示す断面概略図。
【図3B】 本発明のチップ接合構造を備える組立品を製造する工程における第2の実施の形態を示す断面概略図。
【図4A】 チップ接合構造を備える組立品を製造する工程における第2の参考形態を示す断面概略図。
【図4B】 チップ接合構造を備える組立品を製造する工程における第2の参考形態を示す断面概略図。
【図5】 本発明で有用な接合用バンプの別の形を示す断面概略図。
【図6】 本発明で有用な接合用バンプの又別の形を示す断面概略図。
Claims (7)
- フリップチップ接合構造を形成する方法であって、
変形可能な材料で構成されたバンプをICチップ上に配設すること、
バンプと結合する部分に凹凸表面を有し、且つバンプに対向する面とICチップ面に垂直な側壁面とこれら面の間のエッジとを有するパッドを、基板上に配設すること、及び、
パッドにおけるエッジ及び側壁面の周り、並びにバンプと結合する部分の凹凸表面に対してバンプの一部が可塑的な流れを起こすに足りる力で、バンプ及びパッドを互いに押し付け合うことにより、バンプに対向する面及び前記側壁面とに沿って機械的な噛み合わせをつくること、を含むことを特徴とするフリップチップ接合構造を形成する方法。 - 前記バンプの幅が、前記パッドの幅より広い請求項1記載の方法。
- 前記バンプは、ICチップ面に垂直な断面にて階段状の形状を有し、前記ICチップに隣接する部分が前記パッドに押し付けられる部分より広くなっている請求項1記載の方法。
- ICチップと、
変形可能な材料で構成されたバンプと、
基板と、
ICチップ面に垂直な側壁面及びバンプに対向する面を有しめっき表面処理されたパッドとを備え、
前記パッドのめっき表面処理された表面に1〜25μmの複数の表面凹凸が形成され、バンプ及びパッドに圧力をかけてパッドのめっき表面の凹凸にバンプの可塑的な流れを起こすことによりバンプ及びパッドが機械的に噛み合わされ、ICチップと基板との間が電気接続され、少なくとも25μmの塑性変形に耐え変形可能なバンプによりパッドのめっき表面の凹凸が埋められ、ICチップ面に垂直な側壁面に沿った噛み合い及びバンプに対向する面に沿った噛み合いがつくられているフリップチップ接合構造。 - 前記バンプの幅が、前記パッドの幅より広い請求項4記載のフリップチップ接合構造。
- ICチップと、
該ICチップ上に配設され変形可能な材料を含み、圧力によって変形可能な材料が可塑的に流れて形成された面を有するバンプと、
基板と、
基板上に配設されたパッドとを備え、
前記パッドは、ICチップ面に垂直な側壁面と、前記バンプに対向する面とを有し、しかも前記側壁面と前記バンプに対向する面とに形成された凹凸を有し、前記凹凸を埋める前記可塑的な流れにより、前記側壁面及び前記バンプに対向する面に沿って噛み合い面が形成され、バンプと機械的に噛み合っているフリップチップ接合構造。 - 前記バンプの幅が、前記パッドの幅より広い請求項6記載のフリップチップ接合構造。
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US09/802,664 US6815252B2 (en) | 2000-03-10 | 2001-03-09 | Method of forming flip chip interconnection structure |
US09/802,664 | 2001-03-09 | ||
PCT/US2001/007580 WO2001068311A1 (en) | 2000-03-10 | 2001-03-09 | Flip chip interconnection structure |
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JPH07283268A (ja) * | 1994-04-04 | 1995-10-27 | Matsushita Electric Ind Co Ltd | 配線基板とその製造方法 |
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US5940729A (en) * | 1996-04-17 | 1999-08-17 | International Business Machines Corp. | Method of planarizing a curved substrate and resulting structure |
JPH1050765A (ja) * | 1996-08-01 | 1998-02-20 | Nec Corp | 半導体素子の実装方法および半導体装置 |
JPH11186324A (ja) * | 1997-12-22 | 1999-07-09 | Matsushita Electric Ind Co Ltd | バンプ付電子部品の実装方法 |
JPH11204913A (ja) * | 1998-01-09 | 1999-07-30 | Sony Corp | 回路基板及び実装方法並びにプリント配線板 |
Also Published As
Publication number | Publication date |
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US20040212101A1 (en) | 2004-10-28 |
KR20020089379A (ko) | 2002-11-29 |
WO2001068311A1 (en) | 2001-09-20 |
ATE459099T1 (de) | 2010-03-15 |
US7033859B2 (en) | 2006-04-25 |
US6815252B2 (en) | 2004-11-09 |
EP1278612B1 (en) | 2010-02-24 |
US7994636B2 (en) | 2011-08-09 |
TW564528B (en) | 2003-12-01 |
EP1278612A1 (en) | 2003-01-29 |
EP1278612A4 (en) | 2008-04-16 |
KR100817646B1 (ko) | 2008-03-27 |
JP2003526937A (ja) | 2003-09-09 |
US20110260321A1 (en) | 2011-10-27 |
US20010055835A1 (en) | 2001-12-27 |
DE60141391D1 (de) | 2010-04-08 |
US20140145340A1 (en) | 2014-05-29 |
US8697490B2 (en) | 2014-04-15 |
US20040212098A1 (en) | 2004-10-28 |
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