JP2003526937A - フリップチップ接合構造 - Google Patents
フリップチップ接合構造Info
- Publication number
- JP2003526937A JP2003526937A JP2001566849A JP2001566849A JP2003526937A JP 2003526937 A JP2003526937 A JP 2003526937A JP 2001566849 A JP2001566849 A JP 2001566849A JP 2001566849 A JP2001566849 A JP 2001566849A JP 2003526937 A JP2003526937 A JP 2003526937A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- deformable material
- bonding structure
- flip
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
Abstract
Description
される表面間にある凹凸の噛み合わせとによって形成される接合構造に関する。
ージ組立品内においてなされている。このような接合の最も一般的な形態は、I
Cチップ上にあるバンプが基板上に形成されたパッドに冶金的に、通常バンプ材
料を溶融して接合される。この方法は強固な接合を提供するが、溶融および固化
工程中に橋絡(すなわち、隣接した接合箇所間のショート)するリスクがあるた
め、接合箇所のピッチを小さくすることが難しい。他の方法として、微粒子フィ
ルムあるいはペーストを用いる方法があり、ペーストあるいはフィルム中の導電
性微粒子が樹脂の収縮とともに電気的な接合を行う。この方法は、接合箇所のピ
ッチを減少できるが、微粒子接合の妨害感受性のため、長時間の信頼性に限界が
あり、規定時間を超えると性能が低下する。
ップ上に配設し、前記第1要素と結合される部分に凹凸表面を有する第2要素を
基板上に配設する工程と、 前記第1要素の一部が前記第2要素の凹凸表面に可塑的な流れを起こすに足り
る力で、該第1要素及び第2要素を互いに押し付け合う工程とを含むことを特徴
とするフリップチップ接合構造を形成する方法を提供する。
、典型的にはそのようなバンプのセットとされる。特に有用な第1要素の変形可
能な材料として、金が挙げられる。一態様においては、前記第2要素は、基板上
に形成されたリード、パッドおよびバイアオープニングとされる。該態様におい
ては、第2要素は、通常のめっき表面処理が施された表面パッドであって、本発
明に従って凹凸が設けられた表面パッドとされる。
する。
るフリップチップ接合構造であって、第1要素が変形可能な材料であって、第1
及び第2要素が、第1要素の変形可能な材料の第2要素の表面の凹凸への機械的
な噛み合いによって接合されているフリップチップ接合構造を提供する。
接合構造は、第1要素12と第2要素14とを備える。第1要素12はICチッ
プ上に形成されたバンプが好ましく、第2要素14は基板上に形成されたリード
及びパッドが好ましい。第1要素12は、柔軟で変形可能な材料であって、低降
伏強さ及び高破断伸びをもつもので構成されているのがさらに好ましい。第2要
素14は、通常のめっき表面仕上げがされ、該表面に凹凸16(図では大げさに
表されている)が形成された基板パッドを含むものが更に好ましい。凹凸の寸法
は普通1μm〜25μmのオーダ−である。バンプは通常の規格材料、すなわち
、ある特定の形にされた、約250gの垂直荷重に等しい力がかかった時約25
μmを越える塑性変形に耐える材料である。本発明のバンプ用の材料として、金
は特に有用である。
第2要素へ可塑的流れを起こすことによって行われる。第1要素12の高さおよ
び柔軟さのため、接合が達成した後でもかなりの変形が起こる。従って、結合さ
せるべきバンプ/パッドペアの平面性が劣っていても、接合は首尾よくいく。接
合に必要な圧力及び温度は、継ぎ合せる材料の冶金的拡散が要求される従来の熱
圧着に必要とされる圧力及び温度に比べると非常に小さい。これらが低減するた
め、チップ上に起こるダメージが非常に少なくなる。特に同時に行う接合の数が
多い場合、ダメージは非常に少なくなる。
レース28の側壁24およびエッジ26の周りに可塑的に流れることによって、
20で示される微細噛み合い形状が形成される。第1要素22の材料の流れは側
壁24の周りに起こり、隣接するトレース間の領域には起こらず、同じ面内の垂
直方向に起こるのが好ましい。噛み合い形状20は、接合力をあまり増大させず
、噛み合う表面積を増大させているため、より強固な接合を提供する。さらに、
チップ面に対して垂直方向に付加的に移動するため、複数の継ぎ合せ面の共平面
性が劣っていても、容認できる範囲が広い。最後に、該接合は、通常のチップ面
に対する水平の噛み合わせに加えて、チップ面に対して垂直方向の面に沿う噛み
合わせもあるので、ダイと基板間の垂直方向の相対運動に対して保護されている
。
第1要素32の材料が第2要素34周りに可塑的に流れることによって、接合3
0が形成される。第2要素34の幅は第1要素32より小さく、従って、第1要
素32の材料は、第2要素34の両サイド36、38に可塑的に流れる。
第2要素42のリードの形はV字型で、サブトラクティブエッチング法によって
造られる、実際使用されている基板の中で最も典型的な “アンダーカット”リ
ードの形をしているという利点がある。接合40は、第1要素44の材料が第2
要素42の周りに可塑的に流れることによって形成される。図示された構成は、
トレースの最小幅の制限、特に従来のワイヤボンディング法では必要であった水
平域46の最小幅の制限がない。接合40は、バイアパッドに直接、あるいはバ
イアホールを介して基板の次の低層に結合して形成することも意図されている。
小さい力で接合を形成することができ、例えば、図1A、1Bで示されている実
施の形態に比べて2だけ下がる。このように、圧縮力を低減させると加工中にチ
ップに加わるダメージがより少なくなる。
。こうすると、硬化した樹脂によって供給された圧力が、電気接続の長時間保持
特性をさらに改良する。接着性樹脂は、継ぎ合わせ面が接合する前に塗布され、
前記接合の形成時に硬化する。圧力をかけて樹脂材料を前記継ぎ合わせ面から取
り除き、所望の機械的に噛み合った接合を形成する。あるいは、樹脂はアンダー
フィル法によって、接合の後に塗布することもできる。
、Cu、非電着性NiAuおよびAuが好ましい。基板材料としては、片面FR
5ラミネート、2面BT−樹脂ラミネートが好ましい。
の形状がある。特に2つの有用なものとして、図5、図6に線図で示す。図5は
、“階段”形状のものを示し、チップに隣接する部分(べース)が、基板上のパ
ッドに対して押しつけられる部分(先端)より広くなっている。図6は、“スタ
ッドバンプ”形状を示し、ベースの周辺形状が円形で、先端より広くなっている
。これらの構造はどちらも、先端の寸法がより小さいので、バンプと基板上の凹
凸との追従性(コンプライアンス)が改良され、ベース形状がより広くなってい
るため、形状安定性が良好である。
ホールに電気的に接合している従来のハンダパッドに接合してもよい。別の実施
の形態として、第2要素そのものがバイアホールを含んでいてもよい。この実施
の形態によれば、ハンダパッドのようなパッドの上にバンプを押しつけるという
より、バンプをバイアホール内及び縁にある導電性材料に直接押しつけるため、
バイアホールから少し離れて、接合が形成される。こうするとチップ上の面積を
より効率的に使えることとなる。バイアホール中の開口は概して、バンプの先端
より小さく、従って、バンプはバイアホールに直接プレスされ、バイアホールの
中へと変形し始め、接合される。事実、バイアホールはこの構造において、凹凸
として働き、バンプはバイアホールより小さいのでバイアホール中に入り込み、
従って結合がバイアオープニングのリムの部分に形成される。
実施の形態を示す断面概略図。
実施の形態を示す断面概略図。
第2の実施の形態を示す断面概略図。
第2の実施の形態を示す断面概略図。
第3の実施の形態を示す断面概略図。
第3の実施の形態を示す断面概略図。
第4の実施の形態を示す断面概略図。
第4の実施の形態を示す断面概略図。
Claims (17)
- 【請求項1】 フィリップチップ接合構造を形成する方法であって、 低降伏強さ且つ高破断伸びを有する変形可能な材料からなる第1要素をICチ
ップ上に配設し、前記第1要素と結合される部分に凹凸表面を有する第2要素を
基板上に配設する工程と、 前記第1要素の一部が前記第2要素の凹凸表面に可塑的な流れを起こすに足り
る力で、該第1要素及び第2要素を互いに押し付け合う工程とを含むことを特徴
とするフリップチップ接合構造を形成する方法。 - 【請求項2】 前記第1要素がICチップ上に形成されたバンプである請求項
1記載の方法。 - 【請求項3】 前記第1要素の変形可能な材料が金を含む請求項1記載の方法
。 - 【請求項4】 前記第2要素が表面パッドである請求項1記載の方法。
- 【請求項5】 前記第2要素がリードである請求項1記載の方法。
- 【請求項6】 前記第2要素がバイアオープニングである請求項1記載の方法
。 - 【請求項7】 第2要素はハンダ仕上げが施されている請求項1記載の方法。
- 【請求項8】 前記バンプがバンプのセットを含む請求項1記載の方法。
- 【請求項9】 請求項1記載の方法によって造られるフリップチップ接合構造
。 - 【請求項10】 チップに接続した第1要素と基板に接続した第2要素とを備
えるフリップチップ接合構造であって、第1要素が変形可能な材料であって、第
1及び第2要素が、第1要素の変形可能な材料の第2要素の凹凸表面への機械的
な噛み合いによって接合されているフリップチップ接合構造。 - 【請求項11】 前記第1要素が前記チップ上に形成されたバンプを含む請求
項10記載のフリップチップ接合構造。 - 【請求項12】 前記第1要素の変形可能な材料が金を含む請求項10記載の
方法。 - 【請求項13】 前記第2要素が表面パッドを含む請求項10記載の方法。
- 【請求項14】 前記第2要素がリードを含む請求項10記載の方法。
- 【請求項15】 前記第2要素がバイアオープニングを含む請求項10記載の
方法。 - 【請求項16】 第2要素はハンダ仕上げが施されている請求項10記載の方
法。 - 【請求項17】 前記バンプがバンプのセットを含む請求項10記載の方法。
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US09/802,664 | 2001-03-09 | ||
PCT/US2001/007580 WO2001068311A1 (en) | 2000-03-10 | 2001-03-09 | Flip chip interconnection structure |
US09/802,664 US6815252B2 (en) | 2000-03-10 | 2001-03-09 | Method of forming flip chip interconnection structure |
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EP (1) | EP1278612B1 (ja) |
JP (1) | JP4903966B2 (ja) |
KR (1) | KR100817646B1 (ja) |
AT (1) | ATE459099T1 (ja) |
DE (1) | DE60141391D1 (ja) |
TW (1) | TW564528B (ja) |
WO (1) | WO2001068311A1 (ja) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007266555A (ja) * | 2006-03-30 | 2007-10-11 | Denso Corp | バンプ接合体の製造方法 |
JP2009130095A (ja) * | 2007-11-22 | 2009-06-11 | Dainippon Printing Co Ltd | 部品内蔵配線板、部品内蔵配線板の製造方法 |
JP2011176368A (ja) * | 2011-06-01 | 2011-09-08 | Fujitsu Ltd | 電極、電子部品及び基板 |
JP2012109507A (ja) * | 2010-11-16 | 2012-06-07 | Stats Chippac Ltd | 半導体素子およびフリップチップ相互接続構造を形成する方法 |
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JP2012148342A (ja) * | 2004-11-04 | 2012-08-09 | Microchips Inc | 冷間圧接封止の方法及び装置 |
US8350388B2 (en) | 2007-11-01 | 2013-01-08 | Dai Nippon Printing Co., Ltd. | Component built-in wiring board and manufacturing method of component built-in wiring board |
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Families Citing this family (68)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6468638B2 (en) * | 1999-03-16 | 2002-10-22 | Alien Technology Corporation | Web process interconnect in electronic assemblies |
WO2001068311A1 (en) * | 2000-03-10 | 2001-09-20 | Chippac, Inc. | Flip chip interconnection structure |
US6606247B2 (en) | 2001-05-31 | 2003-08-12 | Alien Technology Corporation | Multi-feature-size electronic structures |
US7214569B2 (en) * | 2002-01-23 | 2007-05-08 | Alien Technology Corporation | Apparatus incorporating small-feature-size and large-feature-size components and method for making same |
US7253735B2 (en) | 2003-03-24 | 2007-08-07 | Alien Technology Corporation | RFID tags and processes for producing RFID tags |
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US7495179B2 (en) | 2003-10-06 | 2009-02-24 | Tessera, Inc. | Components with posts and pads |
US7709968B2 (en) | 2003-12-30 | 2010-05-04 | Tessera, Inc. | Micro pin grid array with pin motion isolation |
US7353598B2 (en) * | 2004-11-08 | 2008-04-08 | Alien Technology Corporation | Assembly comprising functional devices and method of making same |
US7452748B1 (en) | 2004-11-08 | 2008-11-18 | Alien Technology Corporation | Strap assembly comprising functional block deposited therein and method of making same |
US7688206B2 (en) | 2004-11-22 | 2010-03-30 | Alien Technology Corporation | Radio frequency identification (RFID) tag for an item having a conductive layer included or attached |
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US7560813B2 (en) * | 2005-06-14 | 2009-07-14 | John Trezza | Chip-based thermo-stack |
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US7767493B2 (en) | 2005-06-14 | 2010-08-03 | John Trezza | Post & penetration interconnection |
US7946331B2 (en) | 2005-06-14 | 2011-05-24 | Cufer Asset Ltd. L.L.C. | Pin-type chip tooling |
US8456015B2 (en) | 2005-06-14 | 2013-06-04 | Cufer Asset Ltd. L.L.C. | Triaxial through-chip connection |
US7790504B2 (en) * | 2006-03-10 | 2010-09-07 | Stats Chippac Ltd. | Integrated circuit package system |
US20070281460A1 (en) * | 2006-06-06 | 2007-12-06 | Cubic Wafer, Inc. | Front-end processed wafer having through-chip connections |
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US8193034B2 (en) | 2006-11-10 | 2012-06-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertical interconnect structure using stud bumps |
US7670874B2 (en) * | 2007-02-16 | 2010-03-02 | John Trezza | Plated pillar package formation |
CN101578929A (zh) * | 2007-09-20 | 2009-11-11 | 揖斐电株式会社 | 印刷线路板及其制造方法 |
US8238114B2 (en) * | 2007-09-20 | 2012-08-07 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing same |
KR101388538B1 (ko) * | 2007-09-28 | 2014-04-23 | 테세라, 인코포레이티드 | 이중 포스트를 사용하여 플립칩 상호연결한 마이크로전자 어셈블리 |
US8201325B2 (en) * | 2007-11-22 | 2012-06-19 | International Business Machines Corporation | Method for producing an integrated device |
JP2009158593A (ja) * | 2007-12-25 | 2009-07-16 | Tessera Interconnect Materials Inc | バンプ構造およびその製造方法 |
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FR2954588B1 (fr) * | 2009-12-23 | 2014-07-25 | Commissariat Energie Atomique | Procede d'assemblage d'au moins une puce avec un element filaire, puce electronique a element de liaison deformable, procede de fabrication d'une pluralite de puces, et assemblage d'au moins une puce avec un element filaire |
US9142533B2 (en) | 2010-05-20 | 2015-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate interconnections having different sizes |
US8330272B2 (en) | 2010-07-08 | 2012-12-11 | Tessera, Inc. | Microelectronic packages with dual or multiple-etched flip-chip connectors |
US8580607B2 (en) | 2010-07-27 | 2013-11-12 | Tessera, Inc. | Microelectronic packages with nanoparticle joining |
US8853558B2 (en) | 2010-12-10 | 2014-10-07 | Tessera, Inc. | Interconnect structure |
US8288871B1 (en) | 2011-04-27 | 2012-10-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduced-stress bump-on-trace (BOT) structures |
US8409979B2 (en) | 2011-05-31 | 2013-04-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties |
US10833033B2 (en) | 2011-07-27 | 2020-11-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bump structure having a side recess and semiconductor structure including the same |
US9105533B2 (en) | 2011-07-27 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structure having a single side recess |
US8643196B2 (en) * | 2011-07-27 | 2014-02-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for bump to landing trace ratio |
US8853853B2 (en) | 2011-07-27 | 2014-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structures |
JP2013093405A (ja) * | 2011-10-25 | 2013-05-16 | Ngk Spark Plug Co Ltd | 配線基板及びその製造方法 |
US9425136B2 (en) | 2012-04-17 | 2016-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conical-shaped or tier-shaped pillar connections |
US9646923B2 (en) | 2012-04-17 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices |
US9299674B2 (en) | 2012-04-18 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump-on-trace interconnect |
US20130320451A1 (en) | 2012-06-01 | 2013-12-05 | Taiwan Semiconductor Manufacturing Company, Ltd., ("Tsmc") | Semiconductor device having non-orthogonal element |
US9111817B2 (en) | 2012-09-18 | 2015-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structure and method of forming same |
JP2015041729A (ja) * | 2013-08-23 | 2015-03-02 | イビデン株式会社 | プリント配線板 |
US20150187719A1 (en) * | 2013-12-30 | 2015-07-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Trace Design for Bump-on-Trace (BOT) Assembly |
US9859200B2 (en) | 2014-12-29 | 2018-01-02 | STATS ChipPAC Pte. Ltd. | Integrated circuit packaging system with interposer support structure mechanism and method of manufacture thereof |
US10886250B2 (en) | 2015-07-10 | 2021-01-05 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
US9633971B2 (en) | 2015-07-10 | 2017-04-25 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
US9842819B2 (en) | 2015-08-21 | 2017-12-12 | Invensas Corporation | Tall and fine pitch interconnects |
KR102423813B1 (ko) | 2015-11-27 | 2022-07-22 | 삼성전자주식회사 | 반도체 소자 |
AU2019449884B8 (en) * | 2019-07-24 | 2022-05-19 | Boe Technology Group Co., Ltd. | Display substrate and method for manufacturing the same |
KR20210138223A (ko) | 2020-05-12 | 2021-11-19 | 삼성전자주식회사 | 반도체 패키지 |
KR20220040138A (ko) * | 2020-09-23 | 2022-03-30 | 삼성전자주식회사 | 반도체 칩의 접속 구조물 및 그의 제조 방법, 및 접속 구조물을 포함하는 반도체 패키지 및 그의 제조 방법 |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01226160A (ja) * | 1988-03-07 | 1989-09-08 | Nippon Telegr & Teleph Corp <Ntt> | 電子部品接続用の端子装置および端子の製造方法 |
JPH0267742A (ja) * | 1988-07-21 | 1990-03-07 | American Teleph & Telegr Co <Att> | 半導体集積回路チップの組合体及びその接着方法 |
JPH036828A (ja) * | 1989-06-02 | 1991-01-14 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JPH0786346A (ja) * | 1993-09-03 | 1995-03-31 | Micron Semiconductor Inc | 動作可能性について半導体回路を検査する方法及び装置と、当該装置を形成する方法 |
JPH07115097A (ja) * | 1993-10-18 | 1995-05-02 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JPH07142488A (ja) * | 1993-11-15 | 1995-06-02 | Nec Corp | バンプ構造及びその製造方法並びにフリップチップ実装 構造 |
JPH07201917A (ja) * | 1993-12-28 | 1995-08-04 | Matsushita Electric Ind Co Ltd | 回路形成基板とその製造方法 |
JPH07283268A (ja) * | 1994-04-04 | 1995-10-27 | Matsushita Electric Ind Co Ltd | 配線基板とその製造方法 |
JPH0997816A (ja) * | 1995-07-27 | 1997-04-08 | Nec Corp | 半導体装置の実装方法および実装構造 |
JPH09275125A (ja) * | 1996-02-08 | 1997-10-21 | Oki Electric Ind Co Ltd | インナーリード接続方法 |
JPH1050765A (ja) * | 1996-08-01 | 1998-02-20 | Nec Corp | 半導体素子の実装方法および半導体装置 |
JPH11186324A (ja) * | 1997-12-22 | 1999-07-09 | Matsushita Electric Ind Co Ltd | バンプ付電子部品の実装方法 |
JPH11204913A (ja) * | 1998-01-09 | 1999-07-30 | Sony Corp | 回路基板及び実装方法並びにプリント配線板 |
US5940729A (en) * | 1996-04-17 | 1999-08-17 | International Business Machines Corp. | Method of planarizing a curved substrate and resulting structure |
Family Cites Families (89)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3665590A (en) * | 1970-01-19 | 1972-05-30 | Ncr Co | Semiconductor flip-chip soldering method |
JPS54105774A (en) | 1978-02-08 | 1979-08-20 | Hitachi Ltd | Method of forming pattern on thin film hybrid integrated circuit |
US4813129A (en) * | 1987-06-19 | 1989-03-21 | Hewlett-Packard Company | Interconnect structure for PC boards and integrated circuits |
US5323035A (en) * | 1992-10-13 | 1994-06-21 | Glenn Leedy | Interconnection structure for integrated circuits and method for making same |
US5634267A (en) * | 1991-06-04 | 1997-06-03 | Micron Technology, Inc. | Method and apparatus for manufacturing known good semiconductor die |
JPH0429338A (ja) | 1990-05-24 | 1992-01-31 | Nippon Mektron Ltd | Icの搭載用回路基板及びその搭載方法 |
US5011066A (en) * | 1990-07-27 | 1991-04-30 | Motorola, Inc. | Enhanced collapse solder interconnection |
JPH04355933A (ja) | 1991-02-07 | 1992-12-09 | Nitto Denko Corp | フリツプチツプの実装構造 |
US5865365A (en) | 1991-02-19 | 1999-02-02 | Hitachi, Ltd. | Method of fabricating an electronic circuit device |
US5686317A (en) | 1991-06-04 | 1997-11-11 | Micron Technology, Inc. | Method for forming an interconnect having a penetration limited contact structure for establishing a temporary electrical connection with a semiconductor die |
JP3225062B2 (ja) | 1991-08-05 | 2001-11-05 | ローム株式会社 | 熱硬化性樹脂シート及びそれを用いた半導体素子の実装方法 |
US5219117A (en) * | 1991-11-01 | 1993-06-15 | Motorola, Inc. | Method of transferring solder balls onto a semiconductor device |
JP2678958B2 (ja) | 1992-03-02 | 1997-11-19 | カシオ計算機株式会社 | フィルム配線基板およびその製造方法 |
US5314651A (en) | 1992-05-29 | 1994-05-24 | Texas Instruments Incorporated | Fine-grain pyroelectric detector material and method |
US5346857A (en) | 1992-09-28 | 1994-09-13 | Motorola, Inc. | Method for forming a flip-chip bond from a gold-tin eutectic |
JP2518508B2 (ja) * | 1993-04-14 | 1996-07-24 | 日本電気株式会社 | 半導体装置 |
US5386624A (en) | 1993-07-06 | 1995-02-07 | Motorola, Inc. | Method for underencapsulating components on circuit supporting substrates |
US5592736A (en) * | 1993-09-03 | 1997-01-14 | Micron Technology, Inc. | Fabricating an interconnect for testing unpackaged semiconductor dice having raised bond pads |
US5508561A (en) | 1993-11-15 | 1996-04-16 | Nec Corporation | Apparatus for forming a double-bump structure used for flip-chip mounting |
JP2664878B2 (ja) | 1994-01-31 | 1997-10-22 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 半導体チップパッケージおよびその製造方法 |
US5802699A (en) * | 1994-06-07 | 1998-09-08 | Tessera, Inc. | Methods of assembling microelectronic assembly with socket for engaging bump leads |
US5519580A (en) | 1994-09-09 | 1996-05-21 | Intel Corporation | Method of controlling solder ball size of BGA IC components |
FR2726397B1 (fr) * | 1994-10-28 | 1996-11-22 | Commissariat Energie Atomique | Film conducteur anisotrope pour la microconnectique |
DE19524739A1 (de) | 1994-11-17 | 1996-05-23 | Fraunhofer Ges Forschung | Kernmetall-Lothöcker für die Flip-Chip-Technik |
JP3353508B2 (ja) | 1994-12-20 | 2002-12-03 | ソニー株式会社 | プリント配線板とこれを用いた電子装置 |
JP3209875B2 (ja) | 1995-03-23 | 2001-09-17 | 株式会社日立製作所 | 基板の製造方法及び基板 |
JP2796070B2 (ja) * | 1995-04-28 | 1998-09-10 | 松下電器産業株式会社 | プローブカードの製造方法 |
US5650595A (en) | 1995-05-25 | 1997-07-22 | International Business Machines Corporation | Electronic module with multiple solder dams in soldermask window |
US5874780A (en) * | 1995-07-27 | 1999-02-23 | Nec Corporation | Method of mounting a semiconductor device to a substrate and a mounted structure |
DE19527661C2 (de) | 1995-07-28 | 1998-02-19 | Optrex Europ Gmbh | Elektrische Leiter aufweisender Träger mit einem elektronischen Bauteil und Verfahen zum Kontaktieren von Leitern eines Substrates mit Kontaktwarzen eines elektronischen Bauteils |
US5872051A (en) * | 1995-08-02 | 1999-02-16 | International Business Machines Corporation | Process for transferring material to semiconductor chip conductive pads using a transfer substrate |
WO1997008749A1 (en) * | 1995-08-29 | 1997-03-06 | Minnesota Mining And Manufacturing Company | Deformable substrate assembly for adhesively bonded electronic device |
US5710071A (en) | 1995-12-04 | 1998-01-20 | Motorola, Inc. | Process for underfilling a flip-chip semiconductor device |
KR0182073B1 (ko) | 1995-12-22 | 1999-03-20 | 황인길 | 반도체 칩 스케일 반도체 패키지 및 그 제조방법 |
US5889326A (en) | 1996-02-27 | 1999-03-30 | Nec Corporation | Structure for bonding semiconductor device to substrate |
JPH09260552A (ja) | 1996-03-22 | 1997-10-03 | Nec Corp | 半導体チップの実装構造 |
KR100216839B1 (ko) | 1996-04-01 | 1999-09-01 | 김규현 | Bga 반도체 패키지의 솔더 볼 랜드 메탈 구조 |
JP2828021B2 (ja) | 1996-04-22 | 1998-11-25 | 日本電気株式会社 | ベアチップ実装構造及び製造方法 |
US5755909A (en) * | 1996-06-26 | 1998-05-26 | Spectra, Inc. | Electroding of ceramic piezoelectric transducers |
US6121689A (en) | 1997-07-21 | 2000-09-19 | Miguel Albert Capote | Semiconductor flip-chip package and method for the fabrication thereof |
US5796590A (en) * | 1996-11-05 | 1998-08-18 | Micron Electronics, Inc. | Assembly aid for mounting packaged integrated circuit devices to printed circuit boards |
JP2924830B2 (ja) * | 1996-11-15 | 1999-07-26 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US5931371A (en) | 1997-01-16 | 1999-08-03 | Ford Motor Company | Standoff controlled interconnection |
JPH10233413A (ja) * | 1997-02-21 | 1998-09-02 | Nec Kansai Ltd | 半導体装置およびその製造方法並びに配線基板 |
JP3500032B2 (ja) | 1997-03-13 | 2004-02-23 | 日本特殊陶業株式会社 | 配線基板及びその製造方法 |
JP3346263B2 (ja) | 1997-04-11 | 2002-11-18 | イビデン株式会社 | プリント配線板及びその製造方法 |
JP3070514B2 (ja) | 1997-04-28 | 2000-07-31 | 日本電気株式会社 | 突起電極を有する半導体装置、半導体装置の実装方法およびその実装構造 |
JPH10303252A (ja) * | 1997-04-28 | 1998-11-13 | Nec Kansai Ltd | 半導体装置 |
DE69835747T2 (de) | 1997-06-26 | 2007-09-13 | Hitachi Chemical Co., Ltd. | Substrat zur montage von halbleiterchips |
JPH1126919A (ja) | 1997-06-30 | 1999-01-29 | Fuji Photo Film Co Ltd | プリント配線板 |
US6337522B1 (en) | 1997-07-10 | 2002-01-08 | International Business Machines Corporation | Structure employing electrically conductive adhesives |
US6335571B1 (en) * | 1997-07-21 | 2002-01-01 | Miguel Albert Capote | Semiconductor flip-chip package and method for the fabrication thereof |
US5985456A (en) | 1997-07-21 | 1999-11-16 | Miguel Albert Capote | Carboxyl-containing polyunsaturated fluxing adhesive for attaching integrated circuits |
JP3028791B2 (ja) * | 1997-08-06 | 2000-04-04 | 日本電気株式会社 | チップ部品の実装方法 |
US6121143A (en) * | 1997-09-19 | 2000-09-19 | 3M Innovative Properties Company | Abrasive articles comprising a fluorochemical agent for wafer surface modification |
US6448665B1 (en) | 1997-10-15 | 2002-09-10 | Kabushiki Kaisha Toshiba | Semiconductor package and manufacturing method thereof |
SG71734A1 (en) | 1997-11-21 | 2000-04-18 | Inst Materials Research & Eng | Area array stud bump flip chip and assembly process |
JP3819576B2 (ja) | 1997-12-25 | 2006-09-13 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
US6200143B1 (en) * | 1998-01-09 | 2001-03-13 | Tessera, Inc. | Low insertion force connector for microelectronic elements |
US6037192A (en) | 1998-01-22 | 2000-03-14 | Nortel Networks Corporation | Process of assembling an integrated circuit and a terminal substrate using solder reflow and adhesive cure |
US6426636B1 (en) * | 1998-02-11 | 2002-07-30 | International Business Machines Corporation | Wafer probe interface arrangement with nonresilient probe elements and support structure |
US5953814A (en) | 1998-02-27 | 1999-09-21 | Delco Electronics Corp. | Process for producing flip chip circuit board assembly exhibiting enhanced reliability |
US6324754B1 (en) | 1998-03-25 | 2001-12-04 | Tessera, Inc. | Method for fabricating microelectronic assemblies |
US6329605B1 (en) | 1998-03-26 | 2001-12-11 | Tessera, Inc. | Components with conductive solder mask layers |
JP2000031204A (ja) | 1998-07-07 | 2000-01-28 | Ricoh Co Ltd | 半導体パッケージの製造方法 |
US6189208B1 (en) * | 1998-09-11 | 2001-02-20 | Polymer Flip Chip Corp. | Flip chip mounting technique |
JP2000133672A (ja) * | 1998-10-28 | 2000-05-12 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP3346320B2 (ja) | 1999-02-03 | 2002-11-18 | カシオ計算機株式会社 | 半導体装置及びその製造方法 |
SG88747A1 (en) | 1999-03-01 | 2002-05-21 | Motorola Inc | A method and machine for underfilling an assembly to form a semiconductor package |
US6483195B1 (en) * | 1999-03-16 | 2002-11-19 | Sumitomo Bakelite Company Limited | Transfer bump street, semiconductor flip chip and method of producing same |
US6173887B1 (en) | 1999-06-24 | 2001-01-16 | International Business Machines Corporation | Method of making electrically conductive contacts on substrates |
JP2001068836A (ja) | 1999-08-27 | 2001-03-16 | Mitsubishi Electric Corp | プリント配線基板及び半導体モジュール並びに半導体モジュールの製造方法 |
TW429492B (en) | 1999-10-21 | 2001-04-11 | Siliconware Precision Industries Co Ltd | Ball grid array package and its fabricating method |
WO2001068311A1 (en) * | 2000-03-10 | 2001-09-20 | Chippac, Inc. | Flip chip interconnection structure |
JP2001339011A (ja) * | 2000-03-24 | 2001-12-07 | Shinko Electric Ind Co Ltd | 半導体装置およびその製造方法 |
US6573610B1 (en) | 2000-06-02 | 2003-06-03 | Siliconware Precision Industries Co., Ltd. | Substrate of semiconductor package for flip chip package |
US6201305B1 (en) | 2000-06-09 | 2001-03-13 | Amkor Technology, Inc. | Making solder ball mounting pads on substrates |
JP3554533B2 (ja) | 2000-10-13 | 2004-08-18 | シャープ株式会社 | チップオンフィルム用テープおよび半導体装置 |
US6818545B2 (en) | 2001-03-05 | 2004-11-16 | Megic Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
US6893901B2 (en) * | 2001-05-14 | 2005-05-17 | Fairchild Semiconductor Corporation | Carrier with metal bumps for semiconductor die packages |
JP4663165B2 (ja) * | 2001-06-27 | 2011-03-30 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP3787295B2 (ja) * | 2001-10-23 | 2006-06-21 | ローム株式会社 | 半導体装置 |
TW507341B (en) | 2001-11-01 | 2002-10-21 | Siliconware Precision Industries Co Ltd | Substrate capable of preventing delamination of chip and semiconductor encapsulation having such a substrate |
JP4114483B2 (ja) | 2003-01-10 | 2008-07-09 | セイコーエプソン株式会社 | 半導体チップの実装方法、半導体実装基板、電子デバイスおよび電子機器 |
US7271497B2 (en) * | 2003-03-10 | 2007-09-18 | Fairchild Semiconductor Corporation | Dual metal stud bumping for flip chip applications |
US7758351B2 (en) * | 2003-04-11 | 2010-07-20 | Neoconix, Inc. | Method and system for batch manufacturing of spring elements |
US7576427B2 (en) * | 2004-05-28 | 2009-08-18 | Stellar Micro Devices | Cold weld hermetic MEMS package and method of manufacture |
JP2007064841A (ja) * | 2005-08-31 | 2007-03-15 | Advantest Corp | 電子部品試験装置用のキャリブレーションボード |
US9599665B2 (en) * | 2013-05-21 | 2017-03-21 | Advantest Corporation | Low overdrive probes with high overdrive substrate |
-
2001
- 2001-03-09 WO PCT/US2001/007580 patent/WO2001068311A1/en active Application Filing
- 2001-03-09 JP JP2001566849A patent/JP4903966B2/ja not_active Expired - Lifetime
- 2001-03-09 DE DE60141391T patent/DE60141391D1/de not_active Expired - Lifetime
- 2001-03-09 AT AT01914779T patent/ATE459099T1/de not_active IP Right Cessation
- 2001-03-09 EP EP01914779A patent/EP1278612B1/en not_active Expired - Lifetime
- 2001-03-09 KR KR1020027011617A patent/KR100817646B1/ko active IP Right Grant
- 2001-03-09 US US09/802,664 patent/US6815252B2/en not_active Expired - Lifetime
- 2001-04-23 TW TW090105528A patent/TW564528B/zh not_active IP Right Cessation
-
2004
- 2004-05-20 US US10/850,093 patent/US7033859B2/en not_active Expired - Lifetime
- 2004-05-20 US US10/849,947 patent/US7994636B2/en not_active Expired - Fee Related
-
2011
- 2011-07-01 US US13/175,694 patent/US8697490B2/en not_active Expired - Fee Related
-
2014
- 2014-01-31 US US14/170,295 patent/US20140145340A1/en not_active Abandoned
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01226160A (ja) * | 1988-03-07 | 1989-09-08 | Nippon Telegr & Teleph Corp <Ntt> | 電子部品接続用の端子装置および端子の製造方法 |
JPH0267742A (ja) * | 1988-07-21 | 1990-03-07 | American Teleph & Telegr Co <Att> | 半導体集積回路チップの組合体及びその接着方法 |
JPH036828A (ja) * | 1989-06-02 | 1991-01-14 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JPH0786346A (ja) * | 1993-09-03 | 1995-03-31 | Micron Semiconductor Inc | 動作可能性について半導体回路を検査する方法及び装置と、当該装置を形成する方法 |
JPH07115097A (ja) * | 1993-10-18 | 1995-05-02 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JPH07142488A (ja) * | 1993-11-15 | 1995-06-02 | Nec Corp | バンプ構造及びその製造方法並びにフリップチップ実装 構造 |
JPH07201917A (ja) * | 1993-12-28 | 1995-08-04 | Matsushita Electric Ind Co Ltd | 回路形成基板とその製造方法 |
JPH07283268A (ja) * | 1994-04-04 | 1995-10-27 | Matsushita Electric Ind Co Ltd | 配線基板とその製造方法 |
JPH0997816A (ja) * | 1995-07-27 | 1997-04-08 | Nec Corp | 半導体装置の実装方法および実装構造 |
JPH09275125A (ja) * | 1996-02-08 | 1997-10-21 | Oki Electric Ind Co Ltd | インナーリード接続方法 |
US5940729A (en) * | 1996-04-17 | 1999-08-17 | International Business Machines Corp. | Method of planarizing a curved substrate and resulting structure |
JPH1050765A (ja) * | 1996-08-01 | 1998-02-20 | Nec Corp | 半導体素子の実装方法および半導体装置 |
JPH11186324A (ja) * | 1997-12-22 | 1999-07-09 | Matsushita Electric Ind Co Ltd | バンプ付電子部品の実装方法 |
JPH11204913A (ja) * | 1998-01-09 | 1999-07-30 | Sony Corp | 回路基板及び実装方法並びにプリント配線板 |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9780057B2 (en) | 2003-11-08 | 2017-10-03 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming pad layout for flipchip semiconductor die |
JP2012148342A (ja) * | 2004-11-04 | 2012-08-09 | Microchips Inc | 冷間圧接封止の方法及び装置 |
JP2007266555A (ja) * | 2006-03-30 | 2007-10-11 | Denso Corp | バンプ接合体の製造方法 |
JP4661657B2 (ja) * | 2006-03-30 | 2011-03-30 | 株式会社デンソー | バンプ接合体の製造方法 |
US8350388B2 (en) | 2007-11-01 | 2013-01-08 | Dai Nippon Printing Co., Ltd. | Component built-in wiring board and manufacturing method of component built-in wiring board |
US8987901B2 (en) | 2007-11-01 | 2015-03-24 | Dai Nippon Printing Co., Ltd. | Component built-in wiring board and manufacturing method of component built-in wiring board |
JP2009130095A (ja) * | 2007-11-22 | 2009-06-11 | Dainippon Printing Co Ltd | 部品内蔵配線板、部品内蔵配線板の製造方法 |
JP2012109507A (ja) * | 2010-11-16 | 2012-06-07 | Stats Chippac Ltd | 半導体素子およびフリップチップ相互接続構造を形成する方法 |
KR101785729B1 (ko) * | 2010-11-16 | 2017-11-06 | 스태츠 칩팩 피티이. 엘티디. | 반도체 소자 및 그 제조 방법 |
JP2012119648A (ja) * | 2010-12-03 | 2012-06-21 | Stats Chippac Ltd | フリップチップ半導体ダイのパッドレイアウトを形成する半導体素子および方法 |
JP2011176368A (ja) * | 2011-06-01 | 2011-09-08 | Fujitsu Ltd | 電極、電子部品及び基板 |
JP2016162913A (ja) * | 2015-03-03 | 2016-09-05 | 三菱電機株式会社 | 半導体モジュールおよびその製造方法 |
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US7033859B2 (en) | 2006-04-25 |
TW564528B (en) | 2003-12-01 |
US20040212101A1 (en) | 2004-10-28 |
EP1278612A4 (en) | 2008-04-16 |
ATE459099T1 (de) | 2010-03-15 |
EP1278612A1 (en) | 2003-01-29 |
US7994636B2 (en) | 2011-08-09 |
JP4903966B2 (ja) | 2012-03-28 |
EP1278612B1 (en) | 2010-02-24 |
WO2001068311A1 (en) | 2001-09-20 |
US20110260321A1 (en) | 2011-10-27 |
KR20020089379A (ko) | 2002-11-29 |
DE60141391D1 (de) | 2010-04-08 |
US6815252B2 (en) | 2004-11-09 |
US20140145340A1 (en) | 2014-05-29 |
US20010055835A1 (en) | 2001-12-27 |
US20040212098A1 (en) | 2004-10-28 |
KR100817646B1 (ko) | 2008-03-27 |
US8697490B2 (en) | 2014-04-15 |
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