JPH036828A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH036828A
JPH036828A JP14168289A JP14168289A JPH036828A JP H036828 A JPH036828 A JP H036828A JP 14168289 A JP14168289 A JP 14168289A JP 14168289 A JP14168289 A JP 14168289A JP H036828 A JPH036828 A JP H036828A
Authority
JP
Japan
Prior art keywords
wiring
resin
semiconductor element
electrode
conductor wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14168289A
Other languages
English (en)
Other versions
JPH0797597B2 (ja
Inventor
Hideji Ida
井田　秀二
Tomohiko Suzuki
知彦 鈴木
Izumi Okamoto
岡本　泉
Shinsuke Nakamoto
中本　伸介
Kenzo Hatada
畑田　賢造
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP14168289A priority Critical patent/JPH0797597B2/ja
Publication of JPH036828A publication Critical patent/JPH036828A/ja
Publication of JPH0797597B2 publication Critical patent/JPH0797597B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、各種電子機器に利用される半導体装置に関す
るものである。
従来の技術 従来の技術を第２図（ａｌ、　ｆｂｌとともに説明する
。
まず第２図（ａｌに示すように、セラミック、ガラス、
ガラスエポキシ等よりなる配線基板１の導体配線２を有
する面に絶縁性の樹脂５を塗布する。
導体配線２はＣｒ−Ａｕ、Ａｌ７．Ｃｕ、ｉｔｏ等であ
り、樹脂５は熱硬化型又は紫外線硬化型のエボ牛シ、シ
リコーン、アクリル等である。
次に半導体素子３の突起電極４と導体配線２とを一致さ
せ、半導体素子３を加圧体６によって加圧し、配線基板
１に押し当てる。突起電極４はＡｌ。
Ａｕ、Ｃｕ等である。
この時、導体配線２上の樹脂５は周囲に押し出され、半
導体素子３の突起電極４と導体配線２は電気的に接触す
る。次に半導体素子３を加圧した状態で上部より紫外線
７を照射することにより、半導体素子３の周縁の樹脂５
を硬化させ仮固定する。更に半導体素子３を加圧しなが
ら加熱することにより樹脂５全体を硬化させる。この時
、第２図＋ｂ＋の様に半導体素子３の突起電極４と導体
配線２は樹脂５の接着力により電気的接続がなされ、同
時に半導体素子３を配線基板１に固着することができる
。
発明が解決しようとする課題 上記のように従来の技術では、半導体素子３の突起電極
４を配線基板１の導体配線２に直接接触させる方法であ
るため、多端子、狭ピッチの半導体素子３の実装に有利
な方法である。しかしながら、加圧を開放した時に突起
電極４の部分的弾性回復の差により半導体素子３の突起
電極４の先端形状が０．１〜０．５μｍ程度凸状となる
。
そしてこれにより、半導体素子３の凸起電極４と配線基
板１の半導体配線２との接触点が減少し、接続の信頼性
が低下する。
課題を解決するための手段 上記課題を解決するために本発明は、配線基板の導体配
線の表面を粗面としたものである。
作用 上記手段によれば、導体配線の表面を粗面としたので、
半導体素子の突起電極の先端形状が凸となっても半導体
素子の突起電極と導体配線との十分な接触点を確保する
ことができ接続に対する信頼性の高いものとなる。
実施例 以下、本発明の一実施例を第１図ｆａｔ、　ｆｂ）とと
もに説明する。
第１図ｔａ＋に示す様に、セラミック、ガラス、エポキ
シ等よりなる配線基板１１上に表面粗さの大きい導体配
線１２を形成し、半導体素子１３を固着する部分に（導
体配線１２上を含んで）絶縁性の樹脂１５を塗布する。
導体配線１２はＣｒ−ＡｕＡ１．Ｃｕ、ｉｔｏ等よりな
りその表面粗さは、ＲＭＡχで０．１〜１．０μｍ程度
にする。絶縁性の樹脂１５は熱硬化型又は紫外線硬化型
のエポキシ、シリコーン、アクリル等である。次に半導
体素子１３の突起電極１４と導体配線１２を一致させる
。突起電極１４はＡ１．Ａｕ、Ｃｕ等である。さらに加
圧体１６により半導体素子１３を配線基板１１に加圧す
る。この時、導体配線１２上の樹脂１５は周囲に押し出
され半導体素子３の突起電極４と導体配線２は電気的に
接触する。次に半導体素子３を加圧した状態で、上部よ
り紫外線１７を照射することによって半導体素子１３の
周縁部の樹脂１５を硬化させ、仮固定する。さらに、こ
れを加熱することによって樹脂１５を完全に硬化させ、
その接着力により、第１図ｆｂ）の様に半導体素子１３
の突起電極１４と導体配線１２との電気的接続と半導体
素子１３の機械的接続が完了される。この時、導体配線
１２は突起電極４の先端形状の５量（０，１〜０．５μ
ｍ程度）よりもその表面が大きく粗ているため、半導体
素子１３の突起電極１４との十分な接触点が確保される
。
なお、導体配線１２の表面粗さが大きいことにより、加
圧後半導体素子１３の突起電極１４と導体配線１２の間
の樹脂を凹部へ流し、両者間に介在するのを防止できる
こととなる。
発明の効果 以上のように本発明は、突起電極の部分的弾性回復の差
による先端形状の５量よりも表面粗さの大きい導体配線
を用いることによって、半導体素子の凸起電極との十分
な接触点を確保し、また、半導体素子の突起電極と導体
配線との間の樹脂の介在を防止できるので、接続の信頼
性を向上させることができる。
【図面の簡単な説明】
第１図（ａｌ、（ｂｌは、本発明の半導体装置の製造方
法の一実施例を示す断面図と要部拡大断面図、第２図（
ａｌ、　ｆｂ）は従来の技術を示す断面図と要部拡大断
面図である。 １１・・・・・・配線基板、１２・・・・・・導体配線
、１３・・・・・・半導体素子、１４・・・・・・突起
電極、１５・・・・・・樹脂。

Claims (1)

    【特許請求の範囲】
  1. 　半導体素子の突起電極を、配線基板に設けた表面を粗
    面とした導体配線に圧接させ、この状態で樹脂により半
    導体素子と配線基板を固着した半導体装置。
JP14168289A 1989-06-02 1989-06-02 半導体装置 Expired - Fee Related JPH0797597B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14168289A JPH0797597B2 (ja) 1989-06-02 1989-06-02 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14168289A JPH0797597B2 (ja) 1989-06-02 1989-06-02 半導体装置

Publications (2)

Publication Number Publication Date
JPH036828A true JPH036828A (ja) 1991-01-14
JPH0797597B2 JPH0797597B2 (ja) 1995-10-18

Family

ID=15297758

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14168289A Expired - Fee Related JPH0797597B2 (ja) 1989-06-02 1989-06-02 半導体装置

Country Status (1)

Country Link
JP (1) JPH0797597B2 (ja)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0567761A (ja) * 1991-09-10 1993-03-19 Matsushita Electric Ind Co Ltd イメージセンサ
JPH0535293U (ja) * 1991-10-09 1993-05-14 アルプス電気株式会社 サ−マルヘツド
US5496769A (en) * 1993-04-30 1996-03-05 Commissariat A L'energie Atomique Process for coating electronic components hybridized by bumps on a substrate
US5545589A (en) * 1993-01-28 1996-08-13 Matsushita Electric Industrial Co., Ltd. Method of forming a bump having a rugged side, a semiconductor device having the bump, and a method of mounting a semiconductor unit and a semiconductor device
WO1998043289A1 (en) * 1997-03-21 1998-10-01 Seiko Epson Corporation Semiconductor device, film carrier tape, and method for manufacturing them
WO1999012197A1 (fr) * 1997-08-29 1999-03-11 Hitachi, Ltd. Dispositif a semi-conducteurs colle par compression et convertisseur de courant faisant appel a ce dispositif
EP1278612A1 (en) * 2000-03-10 2003-01-29 Chippac, Inc. Flip chip interconnection structure
JP2009130095A (ja) * 2007-11-22 2009-06-11 Dainippon Printing Co Ltd 部品内蔵配線板、部品内蔵配線板の製造方法
CN102612265A (zh) * 2007-11-01 2012-07-25 大日本印刷株式会社 内置元件电路板、内置元件电路板的制造方法
JP2016185675A (ja) * 2015-03-27 2016-10-27 京セラ株式会社 サーマルヘッドおよびサーマルプリンタ
CN108493200A (zh) * 2018-05-28 2018-09-04 武汉华星光电半导体显示技术有限公司 一种阵列基板的制作方法、阵列基板及显示装置
US10388626B2 (en) 2000-03-10 2019-08-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming flipchip interconnect structure

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4056424B2 (ja) * 2003-05-16 2008-03-05 シャープ株式会社 半導体装置の製造方法

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0567761A (ja) * 1991-09-10 1993-03-19 Matsushita Electric Ind Co Ltd イメージセンサ
JPH0535293U (ja) * 1991-10-09 1993-05-14 アルプス電気株式会社 サ−マルヘツド
US5545589A (en) * 1993-01-28 1996-08-13 Matsushita Electric Industrial Co., Ltd. Method of forming a bump having a rugged side, a semiconductor device having the bump, and a method of mounting a semiconductor unit and a semiconductor device
US6088236A (en) * 1993-01-28 2000-07-11 Matsushita Electric Industrial Co., Ltd. Semiconductor device having a bump having a rugged side
US5496769A (en) * 1993-04-30 1996-03-05 Commissariat A L'energie Atomique Process for coating electronic components hybridized by bumps on a substrate
US6627994B2 (en) 1997-03-21 2003-09-30 Seiko Epson Corporation Semiconductor device and film carrier tape
WO1998043289A1 (en) * 1997-03-21 1998-10-01 Seiko Epson Corporation Semiconductor device, film carrier tape, and method for manufacturing them
US6316288B1 (en) 1997-03-21 2001-11-13 Seiko Epson Corporation Semiconductor device and methods of manufacturing film camera tape
KR100426883B1 (ko) * 1997-03-21 2004-06-30 세이코 엡슨 가부시키가이샤 반도체장치,필름캐리어테이프및이들의제조방법
WO1999012197A1 (fr) * 1997-08-29 1999-03-11 Hitachi, Ltd. Dispositif a semi-conducteurs colle par compression et convertisseur de courant faisant appel a ce dispositif
US8697490B2 (en) 2000-03-10 2014-04-15 Stats Chippac, Ltd. Flip chip interconnection structure
EP1278612A1 (en) * 2000-03-10 2003-01-29 Chippac, Inc. Flip chip interconnection structure
EP1278612A4 (en) * 2000-03-10 2008-04-16 Chippac Inc BALL INTERCONNECTION STRUCTURE
US10388626B2 (en) 2000-03-10 2019-08-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming flipchip interconnect structure
US7994636B2 (en) 2000-03-10 2011-08-09 Stats Chippac, Ltd. Flip chip interconnection structure
JP4903966B2 (ja) * 2000-03-10 2012-03-28 スタッツ・チップパック・インコーポレイテッド フリップチップ接合構造及びフリップチップ接合構造を形成する方法
JP2003526937A (ja) * 2000-03-10 2003-09-09 チップパック，インク． フリップチップ接合構造
US8987901B2 (en) 2007-11-01 2015-03-24 Dai Nippon Printing Co., Ltd. Component built-in wiring board and manufacturing method of component built-in wiring board
US8350388B2 (en) 2007-11-01 2013-01-08 Dai Nippon Printing Co., Ltd. Component built-in wiring board and manufacturing method of component built-in wiring board
CN102612265A (zh) * 2007-11-01 2012-07-25 大日本印刷株式会社 内置元件电路板、内置元件电路板的制造方法
JP2009130095A (ja) * 2007-11-22 2009-06-11 Dainippon Printing Co Ltd 部品内蔵配線板、部品内蔵配線板の製造方法
JP2016185675A (ja) * 2015-03-27 2016-10-27 京セラ株式会社 サーマルヘッドおよびサーマルプリンタ
CN108493200A (zh) * 2018-05-28 2018-09-04 武汉华星光电半导体显示技术有限公司 一种阵列基板的制作方法、阵列基板及显示装置

Also Published As

Publication number Publication date
JPH0797597B2 (ja) 1995-10-18

Similar Documents

Publication Publication Date Title
JPH036828A (ja) 半導体装置
JPH04301817A (ja) 液晶表示装置とその製造方法
JPH0777227B2 (ja) 半導体装置の製造方法
JP2001308146A (ja) チップキャリアに半導体チップを取り付けるための装置
JPH11103158A (ja) プリント配線板へのフリップチップ実装方法および実装構造
JPH0558660B2 (ja)
JPH07302973A (ja) 電子部品の製造方法
JPH02122531A (ja) 電子部品の実装装置
JPH01160029A (ja) 半導体装置
JPS62281360A (ja) 半導体装置の製造方法
JP2780499B2 (ja) 半導体装置の実装方法
JPS62132331A (ja) 半導体装置の製造方法
JPH02285650A (ja) 半導体装置及びその製造方法
JPH02155257A (ja) 半導体実装装置
KR960001811A (ko) 이방성 도전 접착제를 사용한 집적회로 실장 방법
JPH0429339A (ja) 半導体装置
JP3319269B2 (ja) 電子部品接合方法
JPH0274092A (ja) 実装体の製造方法
JPS62252946A (ja) 半導体装置の製造方法
JPH0519306B2 (ja)
JP3829649B2 (ja) フリップチップ実装方法
JP2712757B2 (ja) ボンディングツール
JPH0212988A (ja) フレキシブルプリント回路の接続方法
JP3031134B2 (ja) 電極の接続方法
JP2841663B2 (ja) 半導体装置の実装構造及び実装方法

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees