DE60141391D1 - Flipchip-Verbindungsstruktur und dessen Herstellungsverfahren - Google Patents
Flipchip-Verbindungsstruktur und dessen HerstellungsverfahrenInfo
- Publication number
- DE60141391D1 DE60141391D1 DE60141391T DE60141391T DE60141391D1 DE 60141391 D1 DE60141391 D1 DE 60141391D1 DE 60141391 T DE60141391 T DE 60141391T DE 60141391 T DE60141391 T DE 60141391T DE 60141391 D1 DE60141391 D1 DE 60141391D1
- Authority
- DE
- Germany
- Prior art keywords
- flip
- manufacturing
- connection structure
- chip connection
- asperities
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
Applications Claiming Priority (3)
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US18857000P | 2000-03-10 | 2000-03-10 | |
PCT/US2001/007580 WO2001068311A1 (en) | 2000-03-10 | 2001-03-09 | Flip chip interconnection structure |
US09/802,664 US6815252B2 (en) | 2000-03-10 | 2001-03-09 | Method of forming flip chip interconnection structure |
Publications (1)
Publication Number | Publication Date |
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DE60141391D1 true DE60141391D1 (de) | 2010-04-08 |
Family
ID=26884225
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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DE60141391T Expired - Lifetime DE60141391D1 (de) | 2000-03-10 | 2001-03-09 | Flipchip-Verbindungsstruktur und dessen Herstellungsverfahren |
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US (5) | US6815252B2 (de) |
EP (1) | EP1278612B1 (de) |
JP (1) | JP4903966B2 (de) |
KR (1) | KR100817646B1 (de) |
AT (1) | ATE459099T1 (de) |
DE (1) | DE60141391D1 (de) |
TW (1) | TW564528B (de) |
WO (1) | WO2001068311A1 (de) |
Families Citing this family (76)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6468638B2 (en) * | 1999-03-16 | 2002-10-22 | Alien Technology Corporation | Web process interconnect in electronic assemblies |
US10388626B2 (en) * | 2000-03-10 | 2019-08-20 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming flipchip interconnect structure |
WO2001068311A1 (en) * | 2000-03-10 | 2001-09-20 | Chippac, Inc. | Flip chip interconnection structure |
US6606247B2 (en) | 2001-05-31 | 2003-08-12 | Alien Technology Corporation | Multi-feature-size electronic structures |
US7214569B2 (en) * | 2002-01-23 | 2007-05-08 | Alien Technology Corporation | Apparatus incorporating small-feature-size and large-feature-size components and method for making same |
US7253735B2 (en) | 2003-03-24 | 2007-08-07 | Alien Technology Corporation | RFID tags and processes for producing RFID tags |
TW200511531A (en) * | 2003-09-08 | 2005-03-16 | Advanced Semiconductor Eng | Package stack module |
US8641913B2 (en) | 2003-10-06 | 2014-02-04 | Tessera, Inc. | Fine pitch microcontacts and method for forming thereof |
US7495179B2 (en) | 2003-10-06 | 2009-02-24 | Tessera, Inc. | Components with posts and pads |
US8853001B2 (en) * | 2003-11-08 | 2014-10-07 | Stats Chippac, Ltd. | Semiconductor device and method of forming pad layout for flipchip semiconductor die |
US7709968B2 (en) | 2003-12-30 | 2010-05-04 | Tessera, Inc. | Micro pin grid array with pin motion isolation |
CN101080359A (zh) * | 2004-11-04 | 2007-11-28 | 微芯片公司 | 压入式冷焊密封方法和装置 |
US7353598B2 (en) * | 2004-11-08 | 2008-04-08 | Alien Technology Corporation | Assembly comprising functional devices and method of making same |
US7452748B1 (en) | 2004-11-08 | 2008-11-18 | Alien Technology Corporation | Strap assembly comprising functional block deposited therein and method of making same |
US7688206B2 (en) | 2004-11-22 | 2010-03-30 | Alien Technology Corporation | Radio frequency identification (RFID) tag for an item having a conductive layer included or attached |
JP2006156544A (ja) * | 2004-11-26 | 2006-06-15 | Denso Corp | 基板の実装構造およびその実装方法 |
US7560813B2 (en) * | 2005-06-14 | 2009-07-14 | John Trezza | Chip-based thermo-stack |
US7781886B2 (en) * | 2005-06-14 | 2010-08-24 | John Trezza | Electronic chip contact structure |
US7851348B2 (en) | 2005-06-14 | 2010-12-14 | Abhay Misra | Routingless chip architecture |
US20060281303A1 (en) * | 2005-06-14 | 2006-12-14 | John Trezza | Tack & fuse chip bonding |
US7687400B2 (en) * | 2005-06-14 | 2010-03-30 | John Trezza | Side stacking apparatus and method |
US7838997B2 (en) * | 2005-06-14 | 2010-11-23 | John Trezza | Remote chip attachment |
US7786592B2 (en) * | 2005-06-14 | 2010-08-31 | John Trezza | Chip capacitive coupling |
US20060278996A1 (en) * | 2005-06-14 | 2006-12-14 | John Trezza | Active packaging |
US7767493B2 (en) | 2005-06-14 | 2010-08-03 | John Trezza | Post & penetration interconnection |
US7946331B2 (en) | 2005-06-14 | 2011-05-24 | Cufer Asset Ltd. L.L.C. | Pin-type chip tooling |
US8456015B2 (en) | 2005-06-14 | 2013-06-04 | Cufer Asset Ltd. L.L.C. | Triaxial through-chip connection |
US7790504B2 (en) * | 2006-03-10 | 2010-09-07 | Stats Chippac Ltd. | Integrated circuit package system |
JP4661657B2 (ja) * | 2006-03-30 | 2011-03-30 | 株式会社デンソー | バンプ接合体の製造方法 |
US20070281460A1 (en) * | 2006-06-06 | 2007-12-06 | Cubic Wafer, Inc. | Front-end processed wafer having through-chip connections |
US7687397B2 (en) * | 2006-06-06 | 2010-03-30 | John Trezza | Front-end processed wafer having through-chip connections |
RU2441298C2 (ru) * | 2006-06-26 | 2012-01-27 | Конинклейке Филипс Электроникс, Н.В. | Межсоединение методом перевернутого кристалла на основе сформированных соединений |
JP4920330B2 (ja) * | 2006-07-18 | 2012-04-18 | ソニー株式会社 | 実装構造体の実装方法、発光ダイオードディスプレイの実装方法、発光ダイオードバックライトの実装方法および電子機器の実装方法 |
US8133762B2 (en) | 2009-03-17 | 2012-03-13 | Stats Chippac, Ltd. | Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core |
US8174119B2 (en) * | 2006-11-10 | 2012-05-08 | Stats Chippac, Ltd. | Semiconductor package with embedded die |
US8193034B2 (en) | 2006-11-10 | 2012-06-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertical interconnect structure using stud bumps |
US7670874B2 (en) * | 2007-02-16 | 2010-03-02 | John Trezza | Plated pillar package formation |
CN101578929A (zh) * | 2007-09-20 | 2009-11-11 | 揖斐电株式会社 | 印刷线路板及其制造方法 |
US8238114B2 (en) * | 2007-09-20 | 2012-08-07 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing same |
KR101388538B1 (ko) * | 2007-09-28 | 2014-04-23 | 테세라, 인코포레이티드 | 이중 포스트를 사용하여 플립칩 상호연결한 마이크로전자 어셈블리 |
JP5176500B2 (ja) * | 2007-11-22 | 2013-04-03 | 大日本印刷株式会社 | 部品内蔵配線板、部品内蔵配線板の製造方法 |
CN102612265B (zh) | 2007-11-01 | 2016-05-11 | 大日本印刷株式会社 | 内置元件电路板、内置元件电路板的制造方法 |
US8201325B2 (en) * | 2007-11-22 | 2012-06-19 | International Business Machines Corporation | Method for producing an integrated device |
JP2009158593A (ja) * | 2007-12-25 | 2009-07-16 | Tessera Interconnect Materials Inc | バンプ構造およびその製造方法 |
TW200941672A (en) * | 2008-03-28 | 2009-10-01 | United Test Ct Inc | Semiconductor device and method of manufacturing the same |
DE102008025833A1 (de) * | 2008-05-29 | 2009-12-17 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verfahren und Vorrichtung zum stoffschlüssigen Fügen metallischer Anschlussstrukturen |
TWI455263B (zh) * | 2009-02-16 | 2014-10-01 | Ind Tech Res Inst | 晶片封裝結構及晶片封裝方法 |
FR2954588B1 (fr) * | 2009-12-23 | 2014-07-25 | Commissariat Energie Atomique | Procede d'assemblage d'au moins une puce avec un element filaire, puce electronique a element de liaison deformable, procede de fabrication d'une pluralite de puces, et assemblage d'au moins une puce avec un element filaire |
US9142533B2 (en) | 2010-05-20 | 2015-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate interconnections having different sizes |
US8330272B2 (en) | 2010-07-08 | 2012-12-11 | Tessera, Inc. | Microelectronic packages with dual or multiple-etched flip-chip connectors |
US8580607B2 (en) | 2010-07-27 | 2013-11-12 | Tessera, Inc. | Microelectronic packages with nanoparticle joining |
US8853558B2 (en) | 2010-12-10 | 2014-10-07 | Tessera, Inc. | Interconnect structure |
US8288871B1 (en) | 2011-04-27 | 2012-10-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduced-stress bump-on-trace (BOT) structures |
US8409979B2 (en) | 2011-05-31 | 2013-04-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties |
JP5234140B2 (ja) * | 2011-06-01 | 2013-07-10 | 富士通株式会社 | 電極、電子部品及び基板 |
US10833033B2 (en) | 2011-07-27 | 2020-11-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bump structure having a side recess and semiconductor structure including the same |
US9105533B2 (en) | 2011-07-27 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structure having a single side recess |
US8643196B2 (en) * | 2011-07-27 | 2014-02-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for bump to landing trace ratio |
US8853853B2 (en) | 2011-07-27 | 2014-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structures |
JP2013093405A (ja) * | 2011-10-25 | 2013-05-16 | Ngk Spark Plug Co Ltd | 配線基板及びその製造方法 |
US9425136B2 (en) | 2012-04-17 | 2016-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conical-shaped or tier-shaped pillar connections |
US9646923B2 (en) | 2012-04-17 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices |
US9299674B2 (en) | 2012-04-18 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump-on-trace interconnect |
US20130320451A1 (en) | 2012-06-01 | 2013-12-05 | Taiwan Semiconductor Manufacturing Company, Ltd., ("Tsmc") | Semiconductor device having non-orthogonal element |
US9111817B2 (en) | 2012-09-18 | 2015-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structure and method of forming same |
JP2015041729A (ja) * | 2013-08-23 | 2015-03-02 | イビデン株式会社 | プリント配線板 |
US20150187719A1 (en) * | 2013-12-30 | 2015-07-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Trace Design for Bump-on-Trace (BOT) Assembly |
US9859200B2 (en) | 2014-12-29 | 2018-01-02 | STATS ChipPAC Pte. Ltd. | Integrated circuit packaging system with interposer support structure mechanism and method of manufacture thereof |
JP6208164B2 (ja) * | 2015-03-03 | 2017-10-04 | 三菱電機株式会社 | 半導体モジュールおよびその製造方法 |
US10886250B2 (en) | 2015-07-10 | 2021-01-05 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
US9633971B2 (en) | 2015-07-10 | 2017-04-25 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
US9842819B2 (en) | 2015-08-21 | 2017-12-12 | Invensas Corporation | Tall and fine pitch interconnects |
KR102423813B1 (ko) | 2015-11-27 | 2022-07-22 | 삼성전자주식회사 | 반도체 소자 |
AU2019449884B8 (en) * | 2019-07-24 | 2022-05-19 | Boe Technology Group Co., Ltd. | Display substrate and method for manufacturing the same |
KR20210138223A (ko) | 2020-05-12 | 2021-11-19 | 삼성전자주식회사 | 반도체 패키지 |
KR20220040138A (ko) * | 2020-09-23 | 2022-03-30 | 삼성전자주식회사 | 반도체 칩의 접속 구조물 및 그의 제조 방법, 및 접속 구조물을 포함하는 반도체 패키지 및 그의 제조 방법 |
Family Cites Families (103)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3665590A (en) * | 1970-01-19 | 1972-05-30 | Ncr Co | Semiconductor flip-chip soldering method |
JPS54105774A (en) | 1978-02-08 | 1979-08-20 | Hitachi Ltd | Method of forming pattern on thin film hybrid integrated circuit |
US4813129A (en) * | 1987-06-19 | 1989-03-21 | Hewlett-Packard Company | Interconnect structure for PC boards and integrated circuits |
JPH01226160A (ja) * | 1988-03-07 | 1989-09-08 | Nippon Telegr & Teleph Corp <Ntt> | 電子部品接続用の端子装置および端子の製造方法 |
US5323035A (en) * | 1992-10-13 | 1994-06-21 | Glenn Leedy | Interconnection structure for integrated circuits and method for making same |
US4937653A (en) * | 1988-07-21 | 1990-06-26 | American Telephone And Telegraph Company | Semiconductor integrated circuit chip-to-chip interconnection scheme |
US5634267A (en) * | 1991-06-04 | 1997-06-03 | Micron Technology, Inc. | Method and apparatus for manufacturing known good semiconductor die |
JPH0797597B2 (ja) * | 1989-06-02 | 1995-10-18 | 松下電器産業株式会社 | 半導体装置 |
JPH0429338A (ja) | 1990-05-24 | 1992-01-31 | Nippon Mektron Ltd | Icの搭載用回路基板及びその搭載方法 |
US5011066A (en) * | 1990-07-27 | 1991-04-30 | Motorola, Inc. | Enhanced collapse solder interconnection |
JPH04355933A (ja) | 1991-02-07 | 1992-12-09 | Nitto Denko Corp | フリツプチツプの実装構造 |
US5865365A (en) | 1991-02-19 | 1999-02-02 | Hitachi, Ltd. | Method of fabricating an electronic circuit device |
US5686317A (en) | 1991-06-04 | 1997-11-11 | Micron Technology, Inc. | Method for forming an interconnect having a penetration limited contact structure for establishing a temporary electrical connection with a semiconductor die |
JP3225062B2 (ja) | 1991-08-05 | 2001-11-05 | ローム株式会社 | 熱硬化性樹脂シート及びそれを用いた半導体素子の実装方法 |
US5219117A (en) * | 1991-11-01 | 1993-06-15 | Motorola, Inc. | Method of transferring solder balls onto a semiconductor device |
JP2678958B2 (ja) | 1992-03-02 | 1997-11-19 | カシオ計算機株式会社 | フィルム配線基板およびその製造方法 |
US5314651A (en) | 1992-05-29 | 1994-05-24 | Texas Instruments Incorporated | Fine-grain pyroelectric detector material and method |
US5346857A (en) | 1992-09-28 | 1994-09-13 | Motorola, Inc. | Method for forming a flip-chip bond from a gold-tin eutectic |
JP2518508B2 (ja) * | 1993-04-14 | 1996-07-24 | 日本電気株式会社 | 半導体装置 |
US5386624A (en) | 1993-07-06 | 1995-02-07 | Motorola, Inc. | Method for underencapsulating components on circuit supporting substrates |
US5592736A (en) * | 1993-09-03 | 1997-01-14 | Micron Technology, Inc. | Fabricating an interconnect for testing unpackaged semiconductor dice having raised bond pads |
US5326428A (en) * | 1993-09-03 | 1994-07-05 | Micron Semiconductor, Inc. | Method for testing semiconductor circuitry for operability and method of forming apparatus for testing semiconductor circuitry for operability |
JP3283977B2 (ja) * | 1993-10-18 | 2002-05-20 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JPH07142488A (ja) * | 1993-11-15 | 1995-06-02 | Nec Corp | バンプ構造及びその製造方法並びにフリップチップ実装 構造 |
US5508561A (en) | 1993-11-15 | 1996-04-16 | Nec Corporation | Apparatus for forming a double-bump structure used for flip-chip mounting |
JPH07201917A (ja) * | 1993-12-28 | 1995-08-04 | Matsushita Electric Ind Co Ltd | 回路形成基板とその製造方法 |
JP2664878B2 (ja) | 1994-01-31 | 1997-10-22 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 半導体チップパッケージおよびその製造方法 |
JP2830734B2 (ja) * | 1994-04-04 | 1998-12-02 | 松下電器産業株式会社 | 配線基板とその製造方法 |
US5802699A (en) * | 1994-06-07 | 1998-09-08 | Tessera, Inc. | Methods of assembling microelectronic assembly with socket for engaging bump leads |
US5519580A (en) | 1994-09-09 | 1996-05-21 | Intel Corporation | Method of controlling solder ball size of BGA IC components |
FR2726397B1 (fr) * | 1994-10-28 | 1996-11-22 | Commissariat Energie Atomique | Film conducteur anisotrope pour la microconnectique |
DE19524739A1 (de) | 1994-11-17 | 1996-05-23 | Fraunhofer Ges Forschung | Kernmetall-Lothöcker für die Flip-Chip-Technik |
JP3353508B2 (ja) | 1994-12-20 | 2002-12-03 | ソニー株式会社 | プリント配線板とこれを用いた電子装置 |
JP3209875B2 (ja) | 1995-03-23 | 2001-09-17 | 株式会社日立製作所 | 基板の製造方法及び基板 |
JP2796070B2 (ja) * | 1995-04-28 | 1998-09-10 | 松下電器産業株式会社 | プローブカードの製造方法 |
US5650595A (en) | 1995-05-25 | 1997-07-22 | International Business Machines Corporation | Electronic module with multiple solder dams in soldermask window |
JP2770821B2 (ja) * | 1995-07-27 | 1998-07-02 | 日本電気株式会社 | 半導体装置の実装方法および実装構造 |
US5874780A (en) * | 1995-07-27 | 1999-02-23 | Nec Corporation | Method of mounting a semiconductor device to a substrate and a mounted structure |
DE19527661C2 (de) | 1995-07-28 | 1998-02-19 | Optrex Europ Gmbh | Elektrische Leiter aufweisender Träger mit einem elektronischen Bauteil und Verfahen zum Kontaktieren von Leitern eines Substrates mit Kontaktwarzen eines elektronischen Bauteils |
US5872051A (en) * | 1995-08-02 | 1999-02-16 | International Business Machines Corporation | Process for transferring material to semiconductor chip conductive pads using a transfer substrate |
WO1997008749A1 (en) * | 1995-08-29 | 1997-03-06 | Minnesota Mining And Manufacturing Company | Deformable substrate assembly for adhesively bonded electronic device |
US5710071A (en) | 1995-12-04 | 1998-01-20 | Motorola, Inc. | Process for underfilling a flip-chip semiconductor device |
KR0182073B1 (ko) | 1995-12-22 | 1999-03-20 | 황인길 | 반도체 칩 스케일 반도체 패키지 및 그 제조방법 |
JP3558459B2 (ja) * | 1996-02-08 | 2004-08-25 | 沖電気工業株式会社 | インナーリード接続方法 |
US5889326A (en) | 1996-02-27 | 1999-03-30 | Nec Corporation | Structure for bonding semiconductor device to substrate |
JPH09260552A (ja) | 1996-03-22 | 1997-10-03 | Nec Corp | 半導体チップの実装構造 |
KR100216839B1 (ko) | 1996-04-01 | 1999-09-01 | 김규현 | Bga 반도체 패키지의 솔더 볼 랜드 메탈 구조 |
US5940729A (en) * | 1996-04-17 | 1999-08-17 | International Business Machines Corp. | Method of planarizing a curved substrate and resulting structure |
JP2828021B2 (ja) | 1996-04-22 | 1998-11-25 | 日本電気株式会社 | ベアチップ実装構造及び製造方法 |
US5755909A (en) * | 1996-06-26 | 1998-05-26 | Spectra, Inc. | Electroding of ceramic piezoelectric transducers |
JP2870497B2 (ja) * | 1996-08-01 | 1999-03-17 | 日本電気株式会社 | 半導体素子の実装方法 |
US6121689A (en) | 1997-07-21 | 2000-09-19 | Miguel Albert Capote | Semiconductor flip-chip package and method for the fabrication thereof |
US5796590A (en) * | 1996-11-05 | 1998-08-18 | Micron Electronics, Inc. | Assembly aid for mounting packaged integrated circuit devices to printed circuit boards |
JP2924830B2 (ja) * | 1996-11-15 | 1999-07-26 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US5931371A (en) | 1997-01-16 | 1999-08-03 | Ford Motor Company | Standoff controlled interconnection |
JPH10233413A (ja) * | 1997-02-21 | 1998-09-02 | Nec Kansai Ltd | 半導体装置およびその製造方法並びに配線基板 |
JP3500032B2 (ja) | 1997-03-13 | 2004-02-23 | 日本特殊陶業株式会社 | 配線基板及びその製造方法 |
JP3346263B2 (ja) | 1997-04-11 | 2002-11-18 | イビデン株式会社 | プリント配線板及びその製造方法 |
JP3070514B2 (ja) | 1997-04-28 | 2000-07-31 | 日本電気株式会社 | 突起電極を有する半導体装置、半導体装置の実装方法およびその実装構造 |
JPH10303252A (ja) * | 1997-04-28 | 1998-11-13 | Nec Kansai Ltd | 半導体装置 |
DE69835747T2 (de) | 1997-06-26 | 2007-09-13 | Hitachi Chemical Co., Ltd. | Substrat zur montage von halbleiterchips |
JPH1126919A (ja) | 1997-06-30 | 1999-01-29 | Fuji Photo Film Co Ltd | プリント配線板 |
US6337522B1 (en) | 1997-07-10 | 2002-01-08 | International Business Machines Corporation | Structure employing electrically conductive adhesives |
US6335571B1 (en) * | 1997-07-21 | 2002-01-01 | Miguel Albert Capote | Semiconductor flip-chip package and method for the fabrication thereof |
US5985456A (en) | 1997-07-21 | 1999-11-16 | Miguel Albert Capote | Carboxyl-containing polyunsaturated fluxing adhesive for attaching integrated circuits |
JP3028791B2 (ja) * | 1997-08-06 | 2000-04-04 | 日本電気株式会社 | チップ部品の実装方法 |
US6121143A (en) * | 1997-09-19 | 2000-09-19 | 3M Innovative Properties Company | Abrasive articles comprising a fluorochemical agent for wafer surface modification |
US6448665B1 (en) | 1997-10-15 | 2002-09-10 | Kabushiki Kaisha Toshiba | Semiconductor package and manufacturing method thereof |
SG71734A1 (en) | 1997-11-21 | 2000-04-18 | Inst Materials Research & Eng | Area array stud bump flip chip and assembly process |
JP3381593B2 (ja) * | 1997-12-22 | 2003-03-04 | 松下電器産業株式会社 | バンプ付電子部品の実装方法 |
JP3819576B2 (ja) | 1997-12-25 | 2006-09-13 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
US6200143B1 (en) * | 1998-01-09 | 2001-03-13 | Tessera, Inc. | Low insertion force connector for microelectronic elements |
JPH11204913A (ja) * | 1998-01-09 | 1999-07-30 | Sony Corp | 回路基板及び実装方法並びにプリント配線板 |
US6037192A (en) | 1998-01-22 | 2000-03-14 | Nortel Networks Corporation | Process of assembling an integrated circuit and a terminal substrate using solder reflow and adhesive cure |
US6426636B1 (en) * | 1998-02-11 | 2002-07-30 | International Business Machines Corporation | Wafer probe interface arrangement with nonresilient probe elements and support structure |
US5953814A (en) | 1998-02-27 | 1999-09-21 | Delco Electronics Corp. | Process for producing flip chip circuit board assembly exhibiting enhanced reliability |
US6324754B1 (en) | 1998-03-25 | 2001-12-04 | Tessera, Inc. | Method for fabricating microelectronic assemblies |
US6329605B1 (en) | 1998-03-26 | 2001-12-11 | Tessera, Inc. | Components with conductive solder mask layers |
JP2000031204A (ja) | 1998-07-07 | 2000-01-28 | Ricoh Co Ltd | 半導体パッケージの製造方法 |
US6189208B1 (en) * | 1998-09-11 | 2001-02-20 | Polymer Flip Chip Corp. | Flip chip mounting technique |
JP2000133672A (ja) * | 1998-10-28 | 2000-05-12 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP3346320B2 (ja) | 1999-02-03 | 2002-11-18 | カシオ計算機株式会社 | 半導体装置及びその製造方法 |
SG88747A1 (en) | 1999-03-01 | 2002-05-21 | Motorola Inc | A method and machine for underfilling an assembly to form a semiconductor package |
US6483195B1 (en) * | 1999-03-16 | 2002-11-19 | Sumitomo Bakelite Company Limited | Transfer bump street, semiconductor flip chip and method of producing same |
US6173887B1 (en) | 1999-06-24 | 2001-01-16 | International Business Machines Corporation | Method of making electrically conductive contacts on substrates |
JP2001068836A (ja) | 1999-08-27 | 2001-03-16 | Mitsubishi Electric Corp | プリント配線基板及び半導体モジュール並びに半導体モジュールの製造方法 |
TW429492B (en) | 1999-10-21 | 2001-04-11 | Siliconware Precision Industries Co Ltd | Ball grid array package and its fabricating method |
WO2001068311A1 (en) * | 2000-03-10 | 2001-09-20 | Chippac, Inc. | Flip chip interconnection structure |
JP2001339011A (ja) * | 2000-03-24 | 2001-12-07 | Shinko Electric Ind Co Ltd | 半導体装置およびその製造方法 |
US6573610B1 (en) | 2000-06-02 | 2003-06-03 | Siliconware Precision Industries Co., Ltd. | Substrate of semiconductor package for flip chip package |
US6201305B1 (en) | 2000-06-09 | 2001-03-13 | Amkor Technology, Inc. | Making solder ball mounting pads on substrates |
JP3554533B2 (ja) | 2000-10-13 | 2004-08-18 | シャープ株式会社 | チップオンフィルム用テープおよび半導体装置 |
US6818545B2 (en) | 2001-03-05 | 2004-11-16 | Megic Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
US6893901B2 (en) * | 2001-05-14 | 2005-05-17 | Fairchild Semiconductor Corporation | Carrier with metal bumps for semiconductor die packages |
JP4663165B2 (ja) * | 2001-06-27 | 2011-03-30 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP3787295B2 (ja) * | 2001-10-23 | 2006-06-21 | ローム株式会社 | 半導体装置 |
TW507341B (en) | 2001-11-01 | 2002-10-21 | Siliconware Precision Industries Co Ltd | Substrate capable of preventing delamination of chip and semiconductor encapsulation having such a substrate |
JP4114483B2 (ja) | 2003-01-10 | 2008-07-09 | セイコーエプソン株式会社 | 半導体チップの実装方法、半導体実装基板、電子デバイスおよび電子機器 |
US7271497B2 (en) * | 2003-03-10 | 2007-09-18 | Fairchild Semiconductor Corporation | Dual metal stud bumping for flip chip applications |
US7758351B2 (en) * | 2003-04-11 | 2010-07-20 | Neoconix, Inc. | Method and system for batch manufacturing of spring elements |
US7576427B2 (en) * | 2004-05-28 | 2009-08-18 | Stellar Micro Devices | Cold weld hermetic MEMS package and method of manufacture |
JP2007064841A (ja) * | 2005-08-31 | 2007-03-15 | Advantest Corp | 電子部品試験装置用のキャリブレーションボード |
US9599665B2 (en) * | 2013-05-21 | 2017-03-21 | Advantest Corporation | Low overdrive probes with high overdrive substrate |
-
2001
- 2001-03-09 WO PCT/US2001/007580 patent/WO2001068311A1/en active Application Filing
- 2001-03-09 JP JP2001566849A patent/JP4903966B2/ja not_active Expired - Lifetime
- 2001-03-09 DE DE60141391T patent/DE60141391D1/de not_active Expired - Lifetime
- 2001-03-09 AT AT01914779T patent/ATE459099T1/de not_active IP Right Cessation
- 2001-03-09 EP EP01914779A patent/EP1278612B1/de not_active Expired - Lifetime
- 2001-03-09 KR KR1020027011617A patent/KR100817646B1/ko active IP Right Grant
- 2001-03-09 US US09/802,664 patent/US6815252B2/en not_active Expired - Lifetime
- 2001-04-23 TW TW090105528A patent/TW564528B/zh not_active IP Right Cessation
-
2004
- 2004-05-20 US US10/850,093 patent/US7033859B2/en not_active Expired - Lifetime
- 2004-05-20 US US10/849,947 patent/US7994636B2/en not_active Expired - Fee Related
-
2011
- 2011-07-01 US US13/175,694 patent/US8697490B2/en not_active Expired - Fee Related
-
2014
- 2014-01-31 US US14/170,295 patent/US20140145340A1/en not_active Abandoned
Also Published As
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US7033859B2 (en) | 2006-04-25 |
TW564528B (en) | 2003-12-01 |
US20040212101A1 (en) | 2004-10-28 |
EP1278612A4 (de) | 2008-04-16 |
ATE459099T1 (de) | 2010-03-15 |
EP1278612A1 (de) | 2003-01-29 |
US7994636B2 (en) | 2011-08-09 |
JP4903966B2 (ja) | 2012-03-28 |
EP1278612B1 (de) | 2010-02-24 |
WO2001068311A1 (en) | 2001-09-20 |
US20110260321A1 (en) | 2011-10-27 |
KR20020089379A (ko) | 2002-11-29 |
US6815252B2 (en) | 2004-11-09 |
US20140145340A1 (en) | 2014-05-29 |
US20010055835A1 (en) | 2001-12-27 |
US20040212098A1 (en) | 2004-10-28 |
JP2003526937A (ja) | 2003-09-09 |
KR100817646B1 (ko) | 2008-03-27 |
US8697490B2 (en) | 2014-04-15 |
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