TWI590400B - 形成嵌入式封裝上矽扇出封裝的半導體裝置及方法 - Google Patents

形成嵌入式封裝上矽扇出封裝的半導體裝置及方法 Download PDF

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TWI590400B
TWI590400B TW102113031A TW102113031A TWI590400B TW I590400 B TWI590400 B TW I590400B TW 102113031 A TW102113031 A TW 102113031A TW 102113031 A TW102113031 A TW 102113031A TW I590400 B TWI590400 B TW I590400B
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package
semiconductor
encapsulant
bumps
semiconductor die
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TW102113031A
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TW201401466A (zh
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林耀劍
陳康
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史達晶片有限公司
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Description

形成嵌入式封裝上矽扇出封裝的半導體裝置及方法
本發明係大致有關於半導體裝置，並且更具體而言係有關於一種形成一薄的嵌入式封裝上矽(SoP)扇出封裝之半導體裝置及方法。
半導體裝置係常見於現代的電子產品中。半導體裝置係在電氣構件的數目及密度上變化。離散的半導體裝置一般包含一類型的電氣構件，例如，發光二極體、小信號電晶體、電阻器、電容器、電感器、以及功率金屬氧化物半導體場效電晶體(MOSFET)。集積的半導體裝置通常包含數百到數百萬個電氣構件。集積的半導體裝置的例子係包含微控制器、微處理器、電荷耦合裝置(CCD)、太陽能電池、以及數位微鏡裝置(DMD)。
半導體裝置係執行廣範圍的功能，例如，信號處理、高速的計算、傳送及接收電磁信號、控制電子裝置、轉換太陽光成為電力、以及產生用於電視顯示器的視覺投影。半導體裝置係見於娛樂、通訊、電力轉換、網路、電腦以及消費者產品的領域中。半導體裝置亦見於軍事的應用、航空、汽車、工業用的控制器、以及辦公室設備。
半導體裝置係利用半導體材料的電氣特性。半導體材料的原子結構係容許其導電度能夠藉由一電場或基極電流的施加或是透過摻雜的 製程加以操縱。摻雜係將雜質帶入半導體材料中，以操縱及控制半導體裝置的導電度。
一半導體裝置係包含主動及被動的電性結構。包含雙載子及場效電晶體的主動結構係控制電流的流動。藉由改變摻雜的程度以及一電場或基極電流的施加，該電晶體不是提升、就是限制電流的流動。包含電阻器、電容器及電感器的被動結構係在電壓及電流之間產生執行各種電氣功能所必要的一種關係。該被動及主動結構係電連接以形成電路，此係使得該半導體裝置能夠執行高速的計算及其它有用的功能。
半導體裝置一般是利用兩個複雜的製程，亦即，前端製造及後端製造來加以製造，每個製造潛在涉及數百道步驟。前端製造係牽涉到複數個晶粒在一半導體晶圓的表面上的形成。每個半導體晶粒通常是相同的，並且包含藉由電連接主動及被動構件所形成的電路。後端製造係牽涉到從完成的晶圓單粒化(singulating)個別的半導體晶粒並且封裝該晶粒以提供結構的支撐以及環境的隔離。如同在此所用的術語“半導體晶粒”係指該字的單數與複數形兩者，並且於是可以指稱單一半導體裝置及多個半導體裝置兩者。
半導體製造的一目標是產出較小的半導體裝置。較小的裝置通常消耗較低的功率，具有較高的效能，並且可以更有效率地加以生產。此外，較小的半導體裝置具有一較小的覆蓋區，此係較小的終端產品所期望的。較小的晶粒尺寸可藉由在產生具有較小且較高密度的主動及被動構件之半導體晶粒的前端製程中的改良來達成。後端製程可以藉由在電氣互連及囊封體上的改良來產生具有較小覆蓋區的半導體裝置封裝。
較小半導體裝置的製造係依賴對於在多個高度上(三維裝置的集積度)的多個半導體裝置之間的水平及垂直的電互連實施改良而定。水平的電互連係包含形成為扇出晶圓級晶片尺寸封裝(fo-WLCSP)或是嵌入式晶圓級球柵陣列(eWLB)的部分之重新分配層(RDL)，其係提供在一半導體晶粒與在該封裝外部的點之間的電連接。垂直的互連可以利用導電的穿透矽貫孔(TSV)或是穿透孔洞貫孔(THV)而被達成。然而，TSV及THV的使用通常牽涉到相當多的時間及設備，此係降低每小時單位(UPH)的製造並且增加成本。再者，貫孔的形成可能包含空孔(void)的形成，該空孔係降低裝置可靠度，並且可能會呈現有關半導體晶粒設置的正確性以及翹曲控制的問題。如同在習知技術中已知的，一種解決用於三維裝置的集積度的水平及垂直的互連的問題之方法係被展示在圖1a及1b中。
圖1a係展示eWLB-模製雷射封裝(MLP)的封裝10，其係使用一包含RDL的互連結構12以提供扇出的水平電連接給半導體晶粒14。eWLB-MLP封裝10亦包含藉由雷射鑽孔而形成在囊封體20內的開口18。垂直的互連或導電的凸塊22係被設置在開口18之內，以在不使用TSV或THV下提供在互連結構12以及eWLB-MLP封裝10相對於該互連結構的一表面之間的垂直互連。於是，eWLB-MLP封裝10係提供水平及垂直的電互連，其中一垂直的互連22之互連I/O陣列係形成在半導體晶粒14的覆蓋區之外，以用於額外的半導體裝置或封裝之後續的安裝以形成一個三維的eWLB-MLP封裝。
圖1b係展示一球柵陣列(BGA)封裝或是凸塊的半導體裝置24係被設置在來自圖1a的eWLB-MLP封裝10之上，其中凸塊26係設置在 凸塊22之上並且被定向為朝向凸塊22。在圖1c中，BGA封裝24係利用表面安裝技術(SMT)而被安裝至eWLB-MLP封裝10，以形成一個三維的eWLB-MLP封裝28。在安裝BGA封裝24至eWLB-MLP封裝10之後，三維的eWLB-MLP封裝28係被加熱以回焊來自BGA封裝24的凸塊26以及垂直的互連22，以形成凸塊或互連結構30。因此，三維的eWLB-MLP封裝28係被形成，並且提供水平及垂直的互連以作為一個三維集積的半導體裝置。然而，三維的eWLB-MLP封裝28的形成需要一複雜的處理流程，此係產生高的製程成本。該用於三維的eWLB-MLP封裝28的處理流程是因為利用雷射鑽孔來形成開口18以及使用兩個凸塊接合(bumping)製程而被複雜化。一第一凸塊接合製程係被用來形成作為BGA封裝24的部分之凸塊26，並且一第二凸塊接合製程係被用來形成如在圖1a中所示的開口18中之凸塊22，該些凸塊係接著加以結合以形成凸塊30。三維的eWLB-MLP封裝28的形成亦提出一項對於在背面雷射鑽孔以及開口18與凸塊30的形成期間處理該封裝的挑戰。利用SMT來將BGA 24安裝至eWLB-MLP封裝10係帶來額外的挑戰，例如處理的問題以及可能的晶圓損壞，此係降低裝置可靠度以及封裝良率。最後，三維的eWLB-MLP封裝28係在控制該封裝的一整體高度上提供有限的彈性。
對於一種提供用於封裝之有效率的水平及垂直的互連之三維的半導體封裝係存在著需求。於是，在一實施例中，本發明是一種製造一半導體裝置之方法，其係包括以下步驟：提供一包含複數個第一凸塊的BGA封裝，在該些第一凸塊之間將一第一半導體晶粒設置在該BGA封裝之 上，在該BGA封裝以及第一半導體晶粒之上沉積一第一囊封體，以及在該些第一凸塊以及第一半導體晶粒之上形成一扇出互連結構。
在另一實施例中，本發明是一種製造一半導體裝置之方法，其係包括以下步驟：提供一包含複數個第一互連結構的半導體封裝，在該些第一互連結構之間將一第一半導體晶粒設置在該半導體封裝之上，在該半導體封裝以及第一半導體晶粒之上沉積一第一囊封體，以及在該第一互連結構以及第一半導體晶粒之上形成一第二互連結構。
在另一實施例中，本發明是一種半導體裝置，其係包含一包括複數個第一互連結構的半導體封裝。一第一半導體晶粒係在該些第一互連結構之間被設置在該半導體封裝之上。一第二互連結構係形成在該些第一互連結構以及第一半導體晶粒之上，並且電連接至該些第一互連結構以及第一半導體晶粒。
10‧‧‧eWLB-MLP封裝
12‧‧‧互連結構
14‧‧‧半導體晶粒
18‧‧‧開口
20‧‧‧囊封體
22‧‧‧互連(凸塊)
24‧‧‧半導體裝置(BGA封裝)
26‧‧‧凸塊
28‧‧‧三維的eWLB-MLP封裝
30‧‧‧凸塊(互連結構)
50‧‧‧電子裝置
52‧‧‧PCB
54‧‧‧信號線路
56‧‧‧接合線封裝
58‧‧‧覆晶
60‧‧‧BGA
62‧‧‧凸塊晶片載體(BCC)
64‧‧‧雙排型封裝(DIP)
66‧‧‧平台柵格陣列(LGA)
68‧‧‧多晶片模組(MCM)
70‧‧‧四邊扁平無引腳封裝(QFN)
72‧‧‧四邊扁平封裝
74‧‧‧半導體晶粒
76‧‧‧接觸墊
78‧‧‧中間載體
80‧‧‧導線
82‧‧‧接合線
84‧‧‧囊封體
88‧‧‧半導體晶粒
90‧‧‧載體
92‧‧‧底膠填充(環氧樹脂黏著材料)
94‧‧‧接合線
96、98‧‧‧接觸墊
100‧‧‧模製化合物(囊封體)
102‧‧‧接觸墊
104‧‧‧凸塊
106‧‧‧中間載體
108‧‧‧主動區
110、112‧‧‧凸塊
114‧‧‧信號線
116‧‧‧模製化合物(囊封體)
120‧‧‧晶圓
122‧‧‧主體基板材料
124‧‧‧半導體晶粒(構件)
126‧‧‧切割道
128‧‧‧背表面
130‧‧‧主動表面
132‧‧‧導電層
136‧‧‧鋸刀(雷射切割工具)
144‧‧‧基板(PCB)
146‧‧‧第一表面
148‧‧‧第二表面
150‧‧‧基底材料
154‧‧‧導電層(RDL)
154a‧‧‧部分
154b‧‧‧部分(接觸墊、線路)
154c‧‧‧部分(接觸墊)
158‧‧‧接合線
160‧‧‧囊封體
164‧‧‧凸塊(球)
166‧‧‧BGA封裝
170‧‧‧半導體晶粒
172‧‧‧背表面
174‧‧‧主動表面
176‧‧‧接觸墊
178‧‧‧晶粒附接帶(黏著劑)
180‧‧‧絕緣(保護)層
181‧‧‧雷射
182‧‧‧開口
190‧‧‧晶粒附接黏著劑
196‧‧‧SoP封裝
198‧‧‧鋸刀(雷射切割工具)
200‧‧‧臨時的基板(載體)
202‧‧‧介面層(載體帶)
204‧‧‧熱剝離層
206‧‧‧空間(間隙)
208‧‧‧交叉點
210‧‧‧囊封體(模製化合物)
214‧‧‧重組晶圓(扇出基板)
218‧‧‧模具
222‧‧‧背表面
224‧‧‧表面
226‧‧‧研磨機
228‧‧‧表面
229‧‧‧雷射
230‧‧‧絕緣(保護)層
232‧‧‧導電層
234‧‧‧翹曲平衡層
236‧‧‧絕緣層
238‧‧‧導電層
242‧‧‧絕緣(保護)層
244‧‧‧凸塊(球)
246‧‧‧扇出的多互連RDL
248‧‧‧重組晶圓
250‧‧‧鋸刀(雷射切割工具)
252‧‧‧嵌入式SoP扇出封裝
253、254‧‧‧邊緣
256‧‧‧嵌入式SoP扇出封裝
258‧‧‧翹曲平衡層
262‧‧‧嵌入式SoP扇出封裝
266‧‧‧嵌入式SoP扇出封裝
270‧‧‧嵌入式SoP扇出封裝
272‧‧‧BGA封裝
274‧‧‧側表面
278‧‧‧囊封體模製化合物(底膠填充)
280‧‧‧BGA封裝
282‧‧‧鋸刀(雷射切割工具)
286‧‧‧嵌入式SoP扇出封裝
290‧‧‧半導體晶粒
292‧‧‧背表面
294‧‧‧主動表面
296‧‧‧接觸墊
298‧‧‧絕緣(保護層)
300‧‧‧開口
304‧‧‧導電層
306‧‧‧鋸刀(雷射切割工具)
308‧‧‧SoP封裝
312‧‧‧載體
314‧‧‧載體帶
316‧‧‧熱剝離層
320‧‧‧囊封體(模製化合物)
322‧‧‧底表面
324‧‧‧底表面
328‧‧‧嵌入式SoP扇出封裝
330‧‧‧互連結構
331‧‧‧絕緣層
332‧‧‧導電層
334‧‧‧半導體晶粒
336‧‧‧背表面
338‧‧‧主動表面
340‧‧‧接觸墊
342‧‧‧絕緣(保護)層
344‧‧‧絕緣(保護)層
346‧‧‧導電層
350‧‧‧鋸刀(雷射切割工具)
354‧‧‧SoP封裝
358‧‧‧載體
360‧‧‧載體帶
362‧‧‧熱剝離層
366‧‧‧囊封體(模製化合物)
368‧‧‧底表面
370‧‧‧底表面
372‧‧‧底表面
374‧‧‧雷射
376‧‧‧嵌入式SoP扇出封裝
378‧‧‧互連結構
379‧‧‧絕緣層
380‧‧‧導電層
382‧‧‧嵌入式SoP扇出封裝
384‧‧‧銅凸塊
386‧‧‧SoP封裝
388‧‧‧互連結構
400‧‧‧導電層
404‧‧‧嵌入式SoP扇出封裝
406‧‧‧金屬膜
408‧‧‧黏著劑
412‧‧‧嵌入式SoP扇出封裝
414、414a、414b‧‧‧開口
416‧‧‧雷射
420‧‧‧嵌入式SoP扇出封裝
422‧‧‧凸塊(球)
430‧‧‧嵌入式SoP扇出封裝
432‧‧‧柱形凸塊(接合線)
434‧‧‧SoP封裝
436‧‧‧互連結構
438‧‧‧導電層
450‧‧‧SoP封裝
452‧‧‧絕緣(保護層)
452a‧‧‧永久的絕緣層
452b‧‧‧臨時的保護層
454‧‧‧SoP封裝面板
458‧‧‧囊封體(模製化合物)
460‧‧‧中央位置
462‧‧‧重組晶圓(扇出基板)
464‧‧‧模具
468‧‧‧表面
470‧‧‧研磨機
472‧‧‧表面
476‧‧‧雷射
478‧‧‧開口
482‧‧‧開口
486‧‧‧絕緣(保護層)
488‧‧‧導電層
490‧‧‧絕緣(保護層)
492‧‧‧導電層
494‧‧‧絕緣(保護層)
496‧‧‧凸塊(球)
498‧‧‧互連結構(扇出的多互連RDL)
500‧‧‧鋸刀(雷射切割工具)
502‧‧‧嵌入式SoP扇出封裝
504‧‧‧嵌入式SoP扇出封裝
506‧‧‧互連結構
508‧‧‧絕緣層
510‧‧‧導電層
圖1a-1c係描繪一種eWLB-MLP半導體封裝；圖2係描繪一具有不同類型的封裝安裝到其表面的印刷電路板(PCB)；圖3a-3c係描繪安裝到該PCB之代表性的半導體封裝的進一步細節；圖4a-4c係描繪一具有複數個藉由切割道分開的半導體晶粒之半導體晶圓；圖5a-5q係描繪一形成嵌入式SOP扇出封裝的製程；圖6a-6b係描繪一具有一翹曲平衡層的嵌入式SOP扇出封裝；圖7係描繪一具有一翹曲平衡層的嵌入式SOP扇出封裝的另一實施例； 圖8係描繪一嵌入式SOP扇出封裝的另一實施例；圖9係描繪一具有一晶粒附接黏著劑之嵌入式SOP扇出封裝；圖10係描繪一包含一BGA封裝的嵌入式SOP扇出封裝的一實施例；圖11a-11b係描繪一包含多種囊封體的嵌入式SOP扇出封裝的一實施例；圖12a-12c係描繪一包含一設置在一BGA封裝之上的導電層的嵌入式SOP扇出封裝的一實施例；圖13a-13d係描繪一包含一設置在一BGA封裝之上的導電層的嵌入式SOP扇出封裝的另一實施例；圖14係描繪一包含銅凸塊的嵌入式SOP扇出封裝的一實施例；圖15係描繪一包含一附接在該封裝之上的金屬膜的嵌入式SOP扇出封裝的一實施例；圖16係描繪一包含形成在該封裝中以提供應力消除的開口的嵌入式SOP扇出封裝的一實施例；圖17係描繪一包含微凸塊的嵌入式SOP扇出封裝的另一實施例；圖18係描繪一包含柱形凸塊的嵌入式SOP扇出封裝的另一實施例；圖19a-19i係描繪另一種形成一嵌入式SOP扇出封裝的製程；以及圖20係描繪一包含一凹處的嵌入式SOP扇出封裝的另一實施例。
本發明係在以下參考該些圖式的說明中，以一或多個實施例來加以描述，其中相同的元件符號係代表相同或類似的元件。儘管本發明係以用於達成本發明之目的之最佳模式來加以描述，但熟習此項技術者將 會體認到的是，其係欲涵蓋可內含在藉由所附的申請專利範圍及其由以下的揭露內容及圖式所支持的等同項所界定的本發明的精神與範疇內的替換物、修改以及等同物。
半導體裝置一般是利用兩個複雜的製程：前端製造及後端製造來加以製造。前端製造係牽涉到複數個晶粒在一半導體晶圓的表面上的形成。在該晶圓上的每個晶粒係包含電連接以形成功能電路的主動及被動電氣構件。例如是電晶體及二極體的主動電氣構件係具有控制電流的流動之能力。例如是電容器、電感器、電阻器及變壓器的被動電氣構件係產生執行電路功能所必要的電壓及電流之間的一種關係。
被動及主動構件係藉由一系列的製程步驟而形成在半導體晶圓的表面之上，該些製程步驟包含摻雜、沉積、微影、蝕刻及平坦化。摻雜係藉由例如是離子植入或熱擴散的技術以將雜質帶入半導體材料中。該摻雜製程係修改主動元件中的半導體材料的導電度，其係轉換該半導體材料成為絕緣體、導體、或是響應於一電場或基極電流來動態地改變該半導體材料的導電度。電晶體係包含具有不同類型及程度的摻雜的區域，該些區域係以使得該電晶體在電場或基極電流的施加時提升或限制電流的流動所必要的來加以配置。
主動及被動構件係藉由具有不同電氣特性的材料層來加以形成。該些層可藉由各種沉積技術來形成，該技術部分是由被沉積的材料類型來決定的。例如，薄膜沉積可能牽涉到化學氣相沉積(CVD)、物理氣相沉積(PVD)、電解的電鍍以及無電的電鍍製程。每個層一般是被圖案化，以形成主動構件、被動構件或是構件間的電連接的部分。
該些層可利用微影而被圖案化，微影係牽涉到光敏材料(例如，光阻)在待被圖案化的層之上的沉積。一圖案係利用光而從一光罩轉印至光阻。在一實施例中，該光阻圖案遭受到光的部分係利用一溶劑來移除，此係露出下面待被圖案化的層的部分。在另一實施例中，該光阻圖案未遭受到光的部分(負光阻)係利用一溶劑來移除，此係露出下面待被圖案化的層的部分。該光阻的剩餘部分係被移除，此係留下一圖案化的層。或者是，某些類型的材料係藉由利用例如是無電的電鍍及電解的電鍍的技術來直接將該材料沉積到該些區域或是沉積到由一先前的沉積/蝕刻製程所形成的空孔中而被圖案化。
圖案化是在半導體晶圓表面上的頂端層的部分被移除所藉由的基本操作。半導體晶圓的部分可利用微影技術、光罩技術、遮罩技術、氧化物或金屬移除技術、照相及製版技術、以及顯微蝕刻技術來加以移除。微影技術係包含用標線片或是一光罩來形成一圖案，並且將該圖案轉印到半導體晶圓的表面層。微影技術係以一種兩個步驟的製程，在半導體晶圓的表面上形成主動及被動構件的水平尺寸。首先，在該標線片或是遮罩上的圖案係被轉印成為一光阻層。光阻是一種當暴露到光時會在結構及性質上進行變化之光敏的材料。改變該光阻的結構及性質的過程不是以負作用光阻、就是以正作用光阻來發生。其次，該光阻層係被轉移到該晶圓表面中。該轉移係發生在蝕刻移除半導體晶圓的頂端層未被該光阻覆蓋的部分時。光阻的化學性質是使得該光阻維持實質完整並且抵抗藉由化學蝕刻溶液的移除，而半導體晶圓的頂端層未被該光阻覆蓋的部分係被移除。形成、曝光及移除該光阻的製程以及移除半導體晶圓的一部分的製程可以根據所 用的特定光阻以及所要的結果來加以修改。
在負作用光阻中，光阻係暴露到光，並且在一個以聚合作用著稱的過程中從一可溶的狀態變化到一不可溶的狀態。在聚合作用中，未聚合的材料係暴露到光或是能量源，並且聚合物係形成一種抗蝕刻的交聯材料。在大多數的負光阻中，該聚合物是聚異戊二烯(polyisopreme)。利用化學溶劑或顯影劑來移除可溶的部分(亦即，未暴露到光的部分)係在光阻層中留下孔洞，該孔洞係對應於標線片上的不透明的圖案。其中圖案是存在於不透明的區域之光罩係稱為透明場光罩。
在正作用光阻中，光阻係被暴露到光，並且在一以光溶解化著稱的過程中從相對非可溶的狀態變化到更為可溶的狀態。在光溶解化中，該相對不可溶的光阻係暴露到適當的光能量，並且被轉換到一更為可溶的狀態。該光阻被光溶解化的部分可在顯影製程中藉由一溶劑來加以移除。該基本的正光阻聚合物是苯酚-甲醛聚合物，亦稱為苯酚-甲醛的酚醛樹脂。利用化學溶劑或顯影劑來移除該可溶的部分(亦即，暴露到光的部分)係在該光阻層中留下孔洞，該孔洞係對應於該標線片上之透明的圖案。其中圖案是存在於透明的區域中的光罩係稱為暗場光罩。
在移除半導體晶圓未被該光阻覆蓋的頂端部分之後，該光阻的剩餘部分係被移除，留下一圖案化的層。或者是，某些類型的材料係藉由利用例如是無電的電鍍及電解的電鍍的技術來直接將該材料沉積到該些區域或是沉積到由一先前的沉積/蝕刻製程所形成的空孔中而被圖案化。
在一現有的圖案之上沉積一材料薄膜可能會擴大下面的圖案並且產生一非均勻平坦的表面。一均勻平坦的表面是產生較小且更緊密 聚集的主動及被動構件所需的。平坦化可被利用來從晶圓的表面移除材料並且產生一均勻平坦的表面。平坦化係牽涉到利用一拋光墊來拋光晶圓的表面。一研磨劑材料及腐蝕性化學品係在拋光期間被加到晶圓的表面。該研磨劑的機械性作用以及該化學品的腐蝕性作用的組合係移除任何不規則的表面構形，產生一均勻平坦的表面。
後端製造係指切割或單粒化完成的晶圓成為個別的半導體晶粒並且接著為了結構的支撐及環境的隔離來封裝該半導體晶粒。為了單粒化該半導體晶粒，晶圓係沿著該晶圓的非功能區域(稱為切割道或劃線)來被劃線且截斷。該晶圓係利用一雷射切割工具或鋸刀而被單粒化。在單粒化之後，該個別的半導體晶粒係被安裝到一封裝基板，該封裝基板係包含用於和其它系統構件互連的接腳或接觸墊。形成在半導體晶粒之上的接觸墊係接著連接至該封裝內的接觸墊。該些電連接可以利用焊料凸塊、柱形凸塊、導電膏、或是接合線來做成。一囊封體或是其它模製材料係沉積在該封裝之上，以提供實體支撐及電氣隔離。該完成的封裝係接著被插入一電氣系統中，並且使得該半導體裝置的功能為可供其它系統構件利用的。
圖2係描繪具有複數個安裝於其表面上之半導體封裝的晶片載體基板或PCB 52之電子裝置50。視應用而定，電子裝置50可具有一種類型之半導體封裝或多種類型之半導體封裝。不同類型之半導體封裝係為了說明之目的而展示於圖2中。
電子裝置50可以是一使用該些半導體封裝以執行一或多種電功能之獨立的系統。或者，電子裝置50可以是一較大系統之子構件。舉例而言，電子裝置50可以是行動電話、個人數位助理(PDA)、數位視訊攝 影機(DVC)、或是其它電子通訊裝置的一部份。或者是，電子裝置50可以是一可插入電腦中之顯示卡、網路介面卡或其它信號處理卡。該半導體封裝可包括微處理器、記憶體、特殊應用積體電路(ASIC)、邏輯電路、類比電路、RF電路、離散裝置或其它半導體晶粒或電氣構件。小型化及重量減輕是這些產品能夠被市場接受所不可少的。在半導體裝置間的距離必須縮短以達到更高的密度。
在圖2中，PCB 52係提供一般的基板以供安裝在該PCB上之半導體封裝的結構支撐及電氣互連。導電的信號線路54係利用蒸鍍、電解的電鍍、無電的電鍍、網版印刷、或其它適合的金屬沉積製程而被形成在PCB 52的一表面之上或是在層內。信號線路54係提供在半導體封裝、安裝的構件、以及其它外部的系統構件的每一個之間的電通訊。線路54亦提供電源及接地連接給每個半導體封裝。
在某些實施例中，一半導體裝置具有兩個封裝層級。第一層級的封裝是一種用於將半導體晶粒機械及電氣地附接至一中間載體的技術。第二層級的封裝係牽涉到將該中間載體機械及電氣地附接至PCB。在其它實施例中，一半導體裝置可以只有該第一層級的封裝，其中晶粒是直接機械及電氣地安裝到PCB上。
為了說明之目的，包含接合線封裝56及覆晶58之數種類型的第一層級的封裝係被展示在PCB 52上。此外，包含BGA 60、凸塊晶片載體(BCC)62、雙排型封裝(DIP)64、平台柵格陣列(LGA)66、多晶片模組(MCM)68、四邊扁平無引腳封裝(QFN)70及四邊扁平封裝72之數種類型的第二層級的封裝係被展示安裝在PCB 52上。視系統需求而定，以第一及第 二層級的封裝類型的任意組合來組態的半導體封裝的任何組合及其它電子構件都可連接至PCB 52。在某些實施例中，電子裝置50係包含單一附接的半導體封裝，而其它實施例需要多個互連的封裝。藉由在單一基板之上組合一或多個半導體封裝，製造商可將預製的構件納入電子裝置及系統中。由於半導體封裝包括複雜的功能，因此可使用較便宜構件及流線化製程來製造電子裝置。所產生的裝置不太可能發生故障且製造費用較低，從而降低消費者成本。
圖3a-3c係展示範例的半導體封裝。圖3a係描繪安裝在PCB 52上的DIP 64之進一步的細節。半導體晶粒74係包括一含有類比或數位電路的主動區，該些類比或數位電路係被實施為形成在晶粒內之主動元件、被動元件、導電層及介電層並且根據該晶粒的電設計而電互連。例如，該電路可包含形成在半導體晶粒74的主動區內之一或多個電晶體、二極體、電感器、電容器、電阻器、以及其它電路元件。接觸墊76是一或多層的導電材料，例如鋁(Al)、Cu、錫(Sn)、鎳(Ni)、金(Au)或銀(Ag)，並且電連接至形成在半導體晶粒74內之電路元件。在DIP 64的組裝期間，半導體晶粒74係利用一金矽共晶層或例如是熱環氧樹脂的黏著材料而被安裝到一中間載體78。該封裝主體係包含一種例如是聚合物或陶瓷的絕緣囊封體。導線80及接合線82係在半導體晶粒74及PCB 52之間提供電互連。囊封體84係為了環境保護而沉積在該封裝之上，以防止濕氣及微粒進入該封裝且污染晶粒74或接合線82。
圖3b係描繪安裝在PCB 52上之BCC 62的進一步細節。半導體晶粒88係利用一種底膠填充(underfill)或是環氧樹脂黏著材料92而被安 裝在載體90之上。接合線94係在接觸墊96及98之間提供第一層級的封裝互連。模製化合物或囊封體100係沉積在半導體晶粒88及接合線94之上以提供實體支撐及電氣隔離給該裝置。接觸墊102係利用一例如是電解的電鍍或無電的電鍍之合適的金屬沉積製程而被形成在PCB 52的一表面之上以避免氧化。接觸墊102係電連接至PCB 52中的一或多個導電信號線路54。凸塊104係形成在BCC 62的接觸墊98以及PCB 52的接觸墊102之間。
在圖3c中，半導體晶粒58係以覆晶型第一層級的封裝方式面向下安裝到中間載體106。半導體晶粒58的主動區108係包含類比或數位電路，該些類比或數位電路係被實施為根據該晶粒的電設計所形成的主動元件、被動元件、導電層及介電層。例如，該電路可包含一或多個電晶體、二極體、電感器、電容器、電阻器以及主動區108內之其它電路元件。半導體晶粒58係透過凸塊110電氣及機械地連接至載體106。
BGA 60係以BGA型第二層級的封裝方式利用凸塊112電氣及機械地連接至PCB 52。半導體晶粒58係透過凸塊110、信號線114及凸塊112而電連接至PCB 52中的導電信號線路54。一種模製化合物或囊封體116係沉積在半導體晶粒58及載體106之上以提供實體支撐及電氣隔離給該裝置。該覆晶半導體裝置係提供從半導體晶粒58上的主動元件到PCB 52上的導電跡線之短的導電路徑，以便縮短信號傳遞距離、降低電容以及改善整體電路效能。在另一實施例中，半導體晶粒58可在無中間載體106的情況下，利用覆晶型第一層級的封裝直接機械及電連接至PCB 52。
圖4a係展示一具有一種例如是矽、鍺、砷化鎵、磷化銦或矽碳化物的主體基板材料122以供結構支撐的半導體晶圓120。如上所述， 複數個半導體晶粒或構件124係形成在晶圓120上，且藉由非主動的晶粒間的晶圓區域或切割道126加以分開。切割道126係提供切割區域以單粒化半導體晶圓120成為半導體晶粒的條帶或是個別的半導體晶粒124。
圖4b係展示半導體晶圓120的一部份的橫截面圖。每個半導體晶粒124係具有一背表面128以及包含類比或數位電路的主動表面130，該些類比或數位電路被實施為形成在該晶粒內且根據該晶粒的電設計及功能電互連的主動元件、被動元件、導電層以及介電層。例如，該電路可包含一或多個電晶體、二極體以及其它形成在主動表面130內之電路元件以實施類比電路或數位電路，例如數位信號處理器(DSP)、ASIC、記憶體或是其它信號處理電路。半導體晶粒124亦可包含整合被動裝置(IPD)，例如電感器、電容器及電阻器，以供RF信號處理使用。在一實施例中，半導體晶粒124是一覆晶型裝置。
一導電層132係利用PVD、CVD、電解的電鍍、無電的電鍍製程、或是其它合適的金屬沉積製程而形成在主動表面130之上。導電層132可以是一或多層的Al、Cu、Sn、Ni、Au、Ag、或是其它合適的導電材料。導電層132係運作為接觸墊，該些接觸墊係電連接至主動表面130上的電路。如同圖4b中所示，導電層132可形成為接觸墊，該些接觸墊係和半導體晶粒124的邊緣隔一第一距離而並排地加以設置。或者是，導電層132可形成為接觸墊，該些接觸墊是呈多個列，使得一第一列的接觸墊係和該晶粒的邊緣隔一第一距離地加以設置，並且一和該第一列交錯的第二列的接觸墊係和該晶粒的邊緣隔一第二距離地加以設置。
在圖4c中，半導體晶圓120係利用一鋸刀或雷射切割工具 136透過切割道126而被單粒化成為半導體晶粒的條帶或是個別的半導體晶粒124。
圖5a-5q係相關於圖2及3a-3c來描繪一種有效率地形成一個包含水平及垂直的互連之三維的SOP扇出封裝的製程。圖5a係展示一基板或PCB 144的一部分的橫截面圖，其係包含一第一表面146以及一相對於該第一表面的第二表面148。基板144係包含結構或基底材料150，其係包括一或多個積層的絕緣或介電層，例如矽、鍺、砷化鎵、磷化銦、矽碳化物、聚合物、聚合物複合材料、陶瓷、玻璃、玻璃環氧樹脂、鈹氧化物、或是其它合適的低成本剛性材料或基體半導體材料，以用於結構的支撐。基板144亦可以是一多層的撓性層板、陶瓷或是引線架。
一導電層或是RDL 154係被形成為基板144的部分並且包含一或多層的Al、Cu、Sn、Ni、Au、Ag或是其它合適的導電材料。導電層154係包含形成在基板144內且穿過基板144的部分154a，以提供遍及整個基板的電互連，其包含分別在相對的第一及第二表面146及148之間的垂直電互連。導電層154進一步包含形成在第一表面146上、或是在第一表面146處的部分154b，其係運作為接觸墊或是線路，以用於在導電層154以及接著被安裝的半導體裝置之間的電互連。類似地，導電層154亦包含形成在第二表面148上或是在第二表面148處的部分154c，其係運作為接觸墊或是線路，以用於在導電層154以及接著被安裝的半導體裝置之間的電互連。基板144係根據接著被安裝的半導體晶粒的配置及設計來透過導電層154提供橫跨該基板的垂直及橫向電互連。導電層154的部分係根據接著被安裝的半導體裝置的設計及功能而為電性共通的、或是電性隔離的。
在圖5b中，來自圖4c的半導體晶粒124係以背表面128被定向為朝向基板144的第一表面146而被安裝到基板144。一晶粒附接黏著劑或是其它合適的材料係被用來將背表面128附接到該基板的第一表面146。半導體晶粒124係被安裝到基板144，其中複數個接觸墊154b係被橫向地偏置且設置在該半導體晶粒的周邊，以用於後續的電互連。
在圖5c中，複數個接合線158係形成在半導體晶粒124的導電層132以及接觸墊或線路154b之間。一囊封體160係利用一種焊膏印刷、壓縮模製、轉移模製、液體囊封體模製、真空疊層、或是其它合適的施加器而沉積在半導體晶粒124之上及周圍、在基板144之上、並且在接合線158的周圍。囊封體160可以是聚合物複合材料，例如具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯、或是具有適合的填充物的聚合物。在一實施例中，內含在囊封體160內之填充物係包含處於任一液體、粉末或是顆粒相之具有一尺寸小於或等於約100微米(μm)的微粒。囊封體160是非導電的、提供實體支撐並且在環境上保護該半導體裝置免於外部的元素及污染物。在一實施例中，囊封體160係利用膜輔助的模製製程來加以沉積。
在圖5d中，一種導電的凸塊材料係利用一種蒸鍍、電解的電鍍、無電的電鍍、球式滴落或是網版印刷製程而被沉積在接觸墊154c之上。該凸塊材料可以是具有一選配的助熔溶劑之Al、Sn，Ni、Au、Ag、Pb、Bi、Cu、焊料以及其之組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料或是無鉛的焊料。該凸塊材料係利用一適當的安裝或是接合製程而被接合到導電層154c。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來加以回焊，以形成球或凸塊164。在某些應用中，凸塊164係被回焊 第二次，以改善至接觸墊154c的電性接觸。凸塊164亦可被壓縮接合或是熱壓接合到接觸墊154c。凸塊164係代表一種可被形成在接觸墊154c之上的互連結構的類型。該互連結構亦可以使用柱形凸塊、微凸塊、導電柱、複合的互連或是其它電互連。凸塊164的一高度係由所要的最終封裝高度以及其它因素來加以決定。半導體晶粒124、基板144、囊封體160以及凸塊164係一起構成BGA封裝或是半導體封裝166。
圖5e係展示類似於來自圖4c的半導體晶粒124之半導體晶粒170，其係包含一背表面172以及一相對於該背表面的主動表面174。主動表面174係包含接觸墊176以及一利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、燒結或是熱氧化而被保形地施加在該主動表面之上的絕緣或保護層180。絕緣層180係包含一或多層二氧化矽(SiO2)、矽氮化物(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、鋁氧化物(Al2O3)或是其它具有類似絕緣及結構的性質之材料。絕緣層180的一部分係藉由利用雷射181的雷射直接剝蝕(LDA)、蝕刻或是其它製程來加以移除，以在絕緣層180中形成開口182來露出接觸墊176。半導體晶粒170係以背表面172被定向為朝向基板144的第二表面148並且以主動表面174被定向為背對基板144之下被安裝到基板144。
在半導體晶粒170被安裝到基板144之前，該半導體晶粒係選配地進行一具有拋光的背面研磨製程，以從背表面172移除基體半導體材料來降低該半導體晶粒的厚度。在背面研磨以及選配的拋光之後，一晶粒附接帶或黏著劑178係在該半導體晶粒被單粒化之前被設置在半導體晶粒170的背表面172之上。或者是，晶粒附接帶或黏著劑178是在該半導體 晶粒被單粒化之後被設置在半導體晶粒170的背表面172之上。半導體晶粒170係利用一拾放操作而被安裝到基板144，其中該半導體晶粒在該基板上的適當的對準係藉由在BGA封裝166的基板上之基準對準標記的存在而變得容易。半導體晶粒170係個別地安裝到基板144、或者是以一條帶的層級來安裝至該基板。在複數個凸塊164被橫向地偏置並且設置在被安裝的半導體晶粒170的周邊之下，半導體晶粒170係被安裝到基板144的第二表面148。在一實施例中，半導體晶粒170係具有一面積或覆蓋區大於半導體晶粒124的一面積或覆蓋區，使得半導體晶粒124係在基板144的第二表面148之上被設置在半導體晶粒170的一覆蓋區之內。或者是，半導體晶粒170係具有一面積或覆蓋區等於或小於半導體晶粒124的一面積或是覆蓋區。
在半導體晶粒170被安裝到基板144之後，B階段的固化可被施加至半導體晶粒170以及BGA封裝166以進一步固化晶粒附接帶或黏著劑178。此外，一最佳化的退火製程可以在該半導體晶粒已經安裝到基板144之後施加至半導體晶粒170，以便於控制翹曲並且維持BGA封裝166之可接受的平面性。
類似於圖5e，圖5f係展示半導體晶粒170係以背表面172被定向為朝向基板144的第二表面148而被安裝到基板144。其並非如圖5e中所示的晶粒附接帶或黏著劑178最初被設置在半導體晶粒170的背表面172之上，圖5f係展示晶粒附接黏著劑190最初在和半導體晶粒170分開時是設置在基板144之上並且接觸基板144。當一裸半導體晶粒170(亦即，在無晶粒附接黏著劑下)被安裝到基板144時，黏著劑190係接觸到該半導體晶粒的背表面172以及該半導體晶粒的背表面172及主動表面174之間延伸 的側表面。
圖5g係展示半導體晶粒170被安裝到BGA封裝166以形成SoP封裝196。SoP封裝196係利用一鋸刀或雷射切割工具198，在BGA封裝166的凸塊164、半導體晶粒124及半導體晶粒170之間穿過基板144、穿過囊封體160，以形成個別的SoP封裝196而被單粒化。
類似於圖5e-5g，圖5h係展示半導體晶粒170是以背表面172被定向為朝向基板144的第二表面148而安裝到基板144。其並非如圖5e及5f所示的半導體晶粒170安裝到未單粒化的基板144，圖5h係展示半導體晶粒170是在凸塊164已經安裝到該基板並且該基板已經如上在圖5g中所述地被單粒化之後，相對於半導體晶粒124而被安裝到基板144。半導體晶粒170係以如同在圖5e中所示的最初設置在半導體晶粒170的背表面172之上的晶粒附接帶或黏著劑178、或是以如同在圖5f中所示的最初設置在基板144之上並且接觸基板144的晶粒附接黏著劑190中之任一種，而被安裝到單粒化的BGA封裝166。藉由安裝半導體晶粒170到單粒化的BGA封裝166，該些BGA封裝可以在該半導體晶粒的安裝之前先被測試，使得該半導體晶粒只安裝到已知良好的BGA封裝166，藉此增加SoP封裝196的良率。
圖5i係展示臨時的基板或載體200的一部分的橫截面圖，其係包含犧牲或是可回收的基底材料，例如矽、鋼、聚合物、鈹氧化物或是其它合適的低成本剛性材料，以用於結構的支撐。一介面層或是載體帶202係形成或積層在載體200之上，以作為一臨時的黏著劑接合膜及支撐層。一熱剝離層204係形成或積層在載體帶202上，並且是在載體200之上。 熱剝離層204係被配置以接收稍後安裝的SoP封裝196，並且在一囊封體沉積到該SoP封裝周圍之後加以移除。或者是，單一層的載體帶或黏著劑係形成在載體200之上，而不是利用載體帶202及熱剝離層204的兩層結構。
來自圖5g或5h的SoP封裝196係被設置在載體200、載體帶202以及熱剝離層204之上，其中半導體晶粒170的主動表面174被定向為朝向該載體。SoP封裝196係利用一具有精確及正確的對準的拾放操作而被安裝到載體200、載體帶202以及熱剝離層204，其係在該些SoP封裝之間提供一空間或間隙206以使得後續在該些SoP封裝之上形成一扇出互連結構或基板變得容易。凸塊164的高度係小於或等於半導體晶粒170以及晶粒附接帶178或晶粒附接黏著劑190之一組合的高度。換言之，半導體晶粒170的高度係大約等於在凸塊164的高度與晶粒附接帶178或晶粒附接黏著劑190之間的一差值。或者是，凸塊164的高度係稍微大於半導體晶粒170以及晶粒附接帶178或晶粒附接黏著劑190之一組合的高度。在一實施例中，凸塊164的高度是大於半導體晶粒170以及晶粒附接帶178或晶粒附接黏著劑190之一組合的高度10μm，凸塊164的高度係隨著晶粒附接帶178或晶粒附接黏著劑190的厚度而變化。於是，凸塊164的一部分係沉入在熱剝離層204的一厚度之內，並且由熱剝離層204的一部分所圍繞。類似地，半導體晶粒170的一部分(包含例如是絕緣層180及接觸墊176)亦沉入在剝離層204或是單一層的載體帶或黏著劑之一厚度內並且由其所圍繞。
圖5j係展示利用如圖5i中所敘述的熱剝離層204而安裝到載體200的SoP封裝196的平面或俯視圖。間隙206係被設置在SoP封裝196的周邊，並且被設置在相鄰的SoP封裝之間。圖5j亦展示在兩個間隙 206之間的一交叉點208，其係形成在四個相鄰的SoP封裝196的角落處。
圖5k係展示一囊封體或模製化合物210係預分配或是積層在載體200、載體帶202、熱剝離層204之上並且在SoP封裝196之上及周圍。或者是，轉移模製或是其它合適的製程可被用來施加模製化合物210。囊封體210可以是聚合物複合材料，例如具有填充物或纖維的環氧樹脂、具有填充物或纖維的環氧丙烯酸酯、或是具有適合的填充物或纖維的聚合物。在一實施例中，囊封體210內的填充物係包含處於任一液體、粉末或顆粒相的具有一小於或等於約100μm的尺寸的微粒，並且其係被選擇成具有一含量及特徵是促進間隙206的填充，並且用於填充在BGA封裝166與載體200之間的凸塊164周圍之區域。在囊封體210內的填充物係進一步被選擇成控制翹曲並且改善封裝的可靠度。囊封體210係被分配在熱剝離層204上，並且在一實施例中係被分配在載體200上的一中央位置，例如，在四個相鄰的SoP封裝196的角落處的間隙206之交叉點208。因此，一重組晶圓或扇出基板214係被形成為包含嵌入式SoP封裝196及囊封體210。SoP封裝196係一起被嵌入在囊封體210中，該囊封體210是非導電的，並且在環境上保護該SoP封裝免於外部的元素及污染物。
圖5l係展示模具218係和載體200、載體帶202以及熱剝離層204組合在一起，以將重組晶圓214封入在該模具內以用於封裝。模具218係藉由移動模具218到SoP封裝196及囊封體210周圍、或者是藉由移動該些SoP封裝及囊封體到該模具中，以和載體200、載體帶202以及熱剝離層204組合在一起。在一實施例中，模具218僅包含一和載體200、載體帶202以及熱剝離層204組合在一起的第一或頂端部分，而無第二或底部模 具部分。載體200、載體帶202以及熱剝離層204係作為該封裝製程的底部模具部分。或者是，半導體晶粒SoP封裝196、載體200、載體帶202以及熱剝離層204可被設置在一包含例如是頂端及底部部分的多個部分的模具內。在SoP封裝196及囊封體210被設置在模具218內之後，該囊封體可以部分或完全固化。在SoP封裝196被嵌入囊封體210內以形成重組晶圓214之後，該重組晶圓係從模具218中移除。
圖5m係展示重組晶圓214從模具218中移除。載體200、載體帶202以及熱剝離層204係藉由活化熱剝離層204而從凸塊164、半導體晶粒170以及囊封體210完全地脫黏並且被移除。或者是，脫黏係藉由化學蝕刻、機械式剝離、CMP、機械式研磨、熱烘烤、UV光、雷射掃描、或是濕式剝除來加以達成。載體200、載體帶202以及熱剝離層204的移除係露出囊封體210的一表面，並且進一步露出凸塊164、絕緣層180以及接觸墊176。
在一實施例中，一所要的厚度之囊封體係形成在SoP封裝196的背表面222之上，因而背面研磨是不需要的。或者是，囊封體210的表面224係利用研磨機226以進行一研磨操作，以平坦化該表面並且降低該囊封體的厚度來協助控制SoP封裝196的翹曲。該研磨操作係移除囊封體210以露出該囊封體的一表面228。在一實施例中，表面228係相對SoP封裝196的背表面222垂直地偏置。或者是，表面228是相對SoP封裝196的背表面222為共面的。一化學蝕刻亦可被利用以移除且平坦化囊封體210。儘管圖5m係展示囊封體210的背面研磨是發生在一連接凸塊164及接觸墊176的互連結構的形成之前，但是該囊封體的背面研磨亦可以發生在例如是 圖5o-5q之互連結構的形成期間或是之後。囊封體210的背面研磨係使得根據最終的封裝的設計來調整一整體的封裝高度變得容易。
在載體200、載體帶202以及熱剝離層204的移除之後，淺雷射鑽孔或清潔係被施加在凸塊164上，以清潔凸塊164的一表面並且改善該凸塊的接觸電阻。利用具有雷射229的LDA、RF蝕刻、電漿清潔或是濕式清潔，凸塊164亦被清潔，並且氧化物的積聚係被移除。在一實施例中，凸塊164是Cu，並且形成在銅凸塊164上之自然產生的氧化物是藉由RF蝕刻來加以移除。
圖5n係展示一選配的翹曲平衡層234形成在囊封體210的表面224或228之上並且與之接觸。翹曲平衡層234係利用印刷、旋轉塗覆、噴霧塗覆、網版印刷、疊層、焊膏印刷、壓縮模製、轉移模製、液體囊封體模製、真空疊層、或是其它合適的施加器來加以形成。翹曲平衡層234可以是一或多層具有或無填充物之光敏的聚合物介電膜、非光敏的聚合物介電膜、環氧樹脂、聚合材料、例如是具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯之聚合物複合材料、或是具有適合的填充物的聚合物、熱固性塑膠層板、或是其它具有類似絕緣及結構的性質之材料。翹曲平衡層234是在囊封體210的最終移除或背面研磨之後形成及固化。翹曲平衡層234係提供結構的支撐給SoP封裝196，平衡在該封裝上的應力，並且在後續的處理及製程期間降低該封裝的翹曲或裂開。翹曲平衡層234的翹曲特徵(包含該翹曲平衡層的厚度以及材料性質)係根據整體封裝配置及設計而被調整。在一實施例中，翹曲平衡層234係具有一在10到60μm的範圍內的厚度以及一在10到150ppm/℃的範圍內的CTE。
圖5o係展示一扇出的多互連RDL的一第一部分係在載體200、載體帶202以及熱剝離層204的移除之後，藉由絕緣或保護層230的沉積及圖案化以及導電層232的沉積及圖案化而形成在重組晶圓214之上。絕緣層230係保形地施加至囊封體210、絕緣層180、開口182、接觸墊176以及凸塊164，並且具有一依循其輪廓的第一表面。絕緣層230係具有一相對於該第一表面的第二平的表面。絕緣層230係包含一或多層光敏的低固化溫度介電阻劑、光敏的複合阻劑、液晶聚合物(LCP)、疊層化合物膜、具有填充物的絕緣膏、焊料光罩阻劑膜、液體模製化合物、顆粒模製化合物、聚醯亞胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是其它具有類似絕緣及結構的性質之材料。絕緣層230係利用印刷、旋轉塗覆、噴霧塗覆、疊層或是其它合適的製程來加以沉積。絕緣層230係接著利用UV曝光且接著是顯影、或是其它合適的製程而被圖案化及固化。絕緣層230的一部分係藉由LDA、蝕刻或是其它合適的製程而被移除，以形成露出半導體晶粒170的接觸墊176以及凸塊164的開口。如同先前有關圖5m中的凸塊164所敘述的，凸塊164及接觸墊176亦可以在絕緣層230的部分的移除期間或是之後來加以清潔。
一導電層232係被圖案化及沉積在囊封體210、半導體晶粒170以及絕緣層230之上。導電層232可以是一或多層的Al、Cu、Sn、Ni、Au、Ag或是其它不會在凸塊164及導電層232之間造成脫層之合適的導電材料或合金。在一實施例中，例如，當凸塊164是焊料時，導電層232係包含一黏著劑層及阻障層，其係為一種焊料可濕性材料，例如，鉻銅(CrCu)、Au、鈦銅(TiCu)合金、Ni或是鎳釩(NiV)合金。導電層232的沉積係使用PVD、 CVD、電解的電鍍、無電的電鍍、或是其它合適的製程。導電層232係沉積在絕緣層230中的開口內，並且完全延伸穿過該絕緣層以接觸凸塊164及接觸墊176。於是，導電層232係在不回焊該凸塊之下被接合到凸塊164，以用於後續的電互連。導電層232亦可以利用LDA或是其它合適的製程來加以圖案化，並且運作為一RDL以從半導體晶粒124及170延伸電連接到半導體晶粒124及170外部的點。
圖5p係展示絕緣或保護層236保形地施加並且依循絕緣層230及導電層232的輪廓。絕緣層236係包含一或多層的光敏的低固化溫度介電阻劑、光敏的複合阻劑、LCP、疊層化合物膜、具有填充物的絕緣膏、焊料光罩阻劑膜、液體模製化合物、顆粒模製化合物、聚醯亞胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3或是其它具有類似絕緣及結構的性質之材料。絕緣層236係利用印刷、旋轉塗覆、噴霧塗覆、疊層或是其它合適的製程來加以沉積。絕緣層236係接著利用UV曝光接著是顯影、或是其它合適的製程而被圖案化及固化。絕緣層236的一部分係藉由LDA、蝕刻或是其它合適的製程而被移除，以露出導電層232的部分。在一實施例中，翹曲平衡層234係如同在圖5n中所述在絕緣層236的形成之後加以形成。
一導電層238係被圖案化且沉積在導電層232、絕緣層236、SoP封裝196以及囊封體210之上。導電層238可以是一或多層的Al、Cu、Sn、Ni、Au、Ag或是其它合適的導電材料。導電層238的沉積係使用PVD、CVD、電解的電鍍、無電的電鍍或是其它合適的製程。導電層238係被設置在絕緣層236中的開口內，並且完全延伸穿過該絕緣層以接觸導電層232。 導電層238亦可以利用LDA或是其它合適的製程而被圖案化，並且運作為一RDL以從半導體晶粒124及170，穿過導電層232而延伸電連接至半導體晶粒124及170外部的點。根據電氣信號完整性的需求以及半導體晶粒124及176的一般配置及設計，額外的導電或RDL層係被加到導電層232及238。
圖5q係展示絕緣或保護層242係保形地施加並且依循絕緣層236以及導電層238的輪廓。絕緣層242係包含一或多層的光敏的低溫度固化介電阻劑、光敏的複合阻劑、LCP、疊層化合物膜、具有填充物的絕緣膏、焊料光罩阻劑膜、液體模製化合物、顆粒模製化合物、聚醯亞胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3或是其它具有類似絕緣及結構的性質之材料。絕緣層242係利用印刷、旋轉塗覆、噴霧塗覆、疊層或是其它合適的製程來加以沉積。絕緣層242係接著利用UV曝光接著是顯影、或是其它合適的製程而被圖案化及固化。絕緣層242的一部分係藉由LDA、蝕刻或是其它合適的製程而被移除以露出導電層238的部分。
一種導電的凸塊材料係利用一種蒸鍍、電解的電鍍、無電的電鍍、球式滴落或是網版印刷製程而沉積在導電層238以及絕緣層242之上。該凸塊材料可以是具有一選配的助熔溶劑之Al、Sn，Ni、Au、Ag、Pb、Bi、Cu、焊料以及其之組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料、或是無鉛的焊料。該凸塊材料係利用一適當的安裝或接合製程而被接合到導電層238。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點而被回焊，以形成球狀的球或凸塊244。在某些應用中，凸塊244係被回焊第二次以改善至導電層238的電性接觸。在一實施例中，凸塊244係形成在一具有一潤濕層、阻障層及黏著劑層的UBM之上。該凸塊亦可以被壓縮 接合或是熱壓接合到導電層238。凸塊244係代表一種可被形成在導電層238之上的互連結構的類型。該互連結構亦可以使用導電膏、柱形凸塊、微凸塊、導電柱、複合的互連、或是其它電互連。絕緣層230、236與242、以及導電層232、238與凸塊244係一起構成互連結構、或是扇出的多互連RDL246。
重組晶圓214、翹曲平衡層234以及互連結構246係一起構成重組晶圓248。重組晶圓248係利用鋸刀或雷射切割工具250，在凸塊244之間、在SoP封裝196之間、並且穿過囊封體210及互連結構246而被單粒化。在互連結構246的完成之後，SoP封裝196並不需要任何額外的雷射鑽孔或是其它用於三維的垂直互連的形成之處理。
圖6a係展示一產生自圖5q中所示之重組晶圓248的單粒化之個別的嵌入式SoP扇出封裝252。嵌入式SoP扇出封裝252係提供水平及垂直的電互連給半導體晶粒170以及包含半導體晶粒124的BGA封裝166，並且提供一些優於在例如是圖1c中所示之三維的eWLB-MLP封裝28的習知技術中已知的封裝之優點。例如，嵌入式SoP扇出封裝252並不需要利用一例如是如同相關於圖1a對於eWLB-MLP封裝10所述的雷射，來在半導體晶粒170的覆蓋區之外的一週邊區域中穿過囊封體210以形成開口。藉由形成凸塊164作為BGA封裝166的部分，並且接著在該些凸塊周圍形成囊封體210，而不是穿過該囊封體來形成例如是雷射形成的開口18之開口，製造嵌入式SoP扇出封裝252的成本係被降低。再者，藉由利用單一凸塊接合製程以形成凸塊164來在BGA封裝166以及半導體晶粒170之間提供垂直的互連，而不是利用如同相關於圖1b及1c所敘述的一第一及第二凸塊 接合製程，處理時間及成本係被降低。因為重組晶圓248是在互連結構246的完成之後被單粒化，使得嵌入式SoP扇出封裝252並不需要任何額外的雷射鑽孔或是其它用於三維的垂直的互連結構的形成之處理，處理時間及成本係額外被降低。藉由在沉積囊封體210之前並且在形成互連結構246之前安裝半導體晶粒170在BGA封裝166之上，在處理期間以及當利用例如相關於圖1c所論述的SMT來安裝半導體晶粒170到BGA封裝166時損壞晶圓的風險係被降低。
相對於如同相關於圖1c所論述之控制三維的eWLB-MLP封裝28的一整體高度之有限的彈性，嵌入式SoP扇出封裝252的一總高度可以輕易地加以控制。嵌入式SoP扇出封裝252的總高度係藉由調整BGA封裝166、半導體晶粒170、囊封體210以及互連結構246的一高度或厚度來加以控制。在一實施例中，嵌入式SoP扇出封裝252的一總厚度或高度係小於或等於約1毫米(mm)、或是小於或等於約800μm、或是小於約600μm。
圖6b係展示嵌入式SoP扇出封裝252的俯視或平面圖，其係如同先前在圖6a的橫截面圖中展示的包含內嵌在扇出封裝252內之SoP封裝196。SoP封裝196的一整體寬度W1係小於嵌入式SoP扇出封裝252的一整體寬度W2。類似地，SoP封裝196的一整體長度L1係小於嵌入式SoP扇出封裝252的一整體長度L2。於是，SoP封裝196的邊緣253係相對於嵌入式SoP扇出封裝252的邊緣254而被偏置，並且凹陷在該封裝之內而且藉由囊封體210加以覆蓋。在一實施例中，SoP封裝196的寬度W1及長度L1都至少分別比於嵌入式SoP扇出封裝252的寬度W2及長度L2小50μm。
圖7係展示一類似於來自圖6a的嵌入式SoP扇出封裝252之個別的嵌入式SoP扇出封裝256。圖7係包含類似於來自圖6a的翹曲平衡層234之翹曲平衡層258。嵌入式SoP扇出封裝256與嵌入式SoP扇出封裝252不同在於安裝翹曲平衡層258到SoP封裝196的背表面222，而不是安裝該翹曲平衡層到設置在該翹曲平衡層與該SoP封裝之間的囊封體210的一部分。翹曲平衡層258係形成在囊封體210的表面224或228以及SoP封裝196的背表面222之上，並且與之接觸。翹曲平衡層258係提供結構的支撐給嵌入式SoP扇出封裝252，平衡在該封裝上的應力，並且降低在後續的處理及製程期間該封裝的翹曲或裂開。翹曲平衡層258的翹曲特徵(包含該翹曲平衡層的厚度以及材料性質)係根據整體封裝配置及設計而被調整。在一實施例中，翹曲平衡層258係具有一在10到60μm的範圍內的厚度以及一在10到150ppm/℃的範圍內的CTE。翹曲平衡層258是在囊封體210以及囊封體160中露出處之最終的背面研磨之後才形成的。翹曲平衡層258是在互連結構246的形成之前、期間或是之後形成的。
於是，嵌入式SoP扇出封裝256係有效率地提供水平及垂直的電互連給內嵌在一個三維的扇出半導體封裝內之複數個半導體晶粒。嵌入式SoP扇出封裝256亦提供在控制整體封裝高度上的彈性。因為嵌入式SoP扇出封裝256在一RDL互連結構的完成之後並不需要額外的雷射鑽孔或是其它用於三維的垂直互連的形成之處理，所以處理時間以及在用於額外製程的處理期間損壞晶圓的風險係被降低。再者，藉由在單一凸塊接合製程中形成凸塊為一BGA封裝的部分並且接著在該些凸塊周圍形成囊封體，封裝的形成係被簡化，並且相對於包含利用多個凸塊接合製程而在穿 過先前提供的囊封體所形成的開口中形成的凸塊之封裝而言是做成較不昂貴的。
圖8係展示一類似於來自圖7的嵌入式SoP扇出封裝256之個別的嵌入式SoP扇出封裝262。嵌入式SoP扇出封裝262與嵌入式SoP扇出封裝256不同是在於包含囊封體160之一露出的背表面222以作為最終的嵌入式SoP扇出封裝262的部分。囊封體160的背表面222係藉由背面研磨囊封體210以及囊封體160而露出，此係發生在互連結構246的形成之前、期間或是之後。
於是，嵌入式SoP扇出封裝262係有效率地提供水平及垂直的電互連給複數個內嵌在一個三維的扇出半導體封裝之內的半導體晶粒。嵌入式SoP扇出封裝262亦提供在控制整體封裝高度上的彈性。因為嵌入式SoP扇出封裝262在一RDL互連結構的完成之後並不需要額外的雷射鑽孔或是其它用於三維的垂直的互連的形成的處理，因此處理時間以及在處理額外的製程期間損壞晶圓的風險係被降低。再者，藉由在單一凸塊接合製程中形成凸塊為一BGA封裝的部分並且接著在該些凸塊周圍形成囊封體，封裝的形成係被簡化，並且相對於包含利用多個凸塊接合製程而在穿過先前提供的囊封體所形成的開口中形成的凸塊之封裝而言是做成較不昂貴的。
圖9係展示一類似於來自圖8的嵌入式SoP扇出封裝262之個別的嵌入式SoP扇出封裝266。在嵌入式SoP扇出封裝266中，囊封體160的背表面222係被露出以作為最終的嵌入式SoP扇出封裝266的部分。囊封體160的背表面222係藉由在互連結構246的形成之前、期間或是之後背面 研磨囊封體210以及囊封體160而被露出。
嵌入式SoP扇出封裝266與嵌入式SoP扇出封裝262不同是在於包含晶粒附接黏著劑190。晶粒附接黏著劑190最初是在基板144與半導體晶粒170分開時，被設置在基板144之上並且與之接觸。晶粒附接黏著劑190並非像是在圖5e中所示以及內含在圖8中的晶粒附接帶或黏著劑178最初是被設置在半導體晶粒170的背表面172之上。當半導體晶粒170被安裝到基板144時，黏著劑190係接觸到該半導體晶粒的背表面172以及該半導體晶粒的側表面以接觸在背表面172及主動表面174之間的半導體晶粒。
於是，嵌入式SoP扇出封裝266係有效率地提供水平及垂直的電互連給複數個內嵌在一個三維的扇出半導體封裝之內的半導體晶粒。嵌入式SoP扇出封裝266亦提供在控制整體封裝高度上的彈性。因為嵌入式SoP扇出封裝266在一RDL互連結構的完成之後並不需要額外的雷射鑽孔或是其它用於三維的垂直的互連的形成的處理，因此處理時間以及在處理額外的製程期間損壞晶圓的風險係被降低。再者，藉由在單一凸塊接合製程中形成凸塊為一BGA封裝的部分並且接著在該些凸塊周圍形成囊封體，封裝的形成係被簡化，並且相對於包含利用多個凸塊接合製程而在穿過先前提供的囊封體所形成的開口中形成的凸塊之封裝而言是做成較不昂貴的。
圖10係展示一類似於來自圖6a的嵌入式SoP扇出封裝252之個別的嵌入式SoP扇出封裝270。在嵌入式SoP扇出封裝270中，囊封體160的背表面222係被囊封體210覆蓋以作為最終的嵌入式SoP扇出封裝270的部分。或者是，背表面222可以相對於囊封體210而被露出。嵌入式SoP 扇出封裝270係包含一類似於圖5d中所示的BGA封裝166之BGA封裝272。BGA封裝272與BGA封裝166或SoP封裝196不同是在於具有一寬度實質等於嵌入式SoP扇出封裝270的一整體寬度。就此而論，BGA封裝272的側表面274係和嵌入式SoP扇出封裝270的一表面的一部分共同延伸且相接的。側表面274並未利用囊封體210來加以覆蓋，並且相對於嵌入式SoP扇出封裝270而露出，這是因為BGA封裝272係具有一面積或覆蓋區實質等於嵌入式SoP扇出封裝270的一面積或覆蓋區。
於是，嵌入式SoP扇出封裝270係有效率地提供水平及垂直的電互連給複數個內嵌在一個三維的扇出半導體封裝之內的半導體晶粒。嵌入式SoP扇出封裝270亦提供在控制整體封裝高度上的彈性。因為嵌入式SoP扇出封裝270在一RDL互連結構的完成之後並不需要額外的雷射鑽孔或是其它用於三維的垂直的互連的形成的處理，因此處理時間以及在處理額外的製程期間損壞晶圓的風險係被降低。再者，藉由在單一凸塊接合製程中形成凸塊為一BGA封裝的部分並且接著在該些凸塊周圍形成囊封體，封裝的形成係被簡化，並且相對於包含利用多個凸塊接合製程而在穿過先前提供的囊封體所形成的開口中形成的凸塊之封裝而言是做成較不昂貴的。
圖11a是從圖5e或5f繼續來展示類似於BGA封裝166的BGA封裝280，其中半導體晶粒170是以背表面172被定向為朝向基板144的第二表面148而安裝到基板144。一囊封體模製化合物或底膠填充278係利用一焊膏印刷、壓縮模製、轉移模製、液體囊封體模製、真空疊層或是其它合適的施加器而沉積在半導體晶粒170周圍、在基板144之上、以及在 凸塊164周圍。囊封體278可以是聚合物複合材料，例如具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯、或是具有適合的填充物的聚合物。在一實施例中，內含在囊封體278內之填充物係包含具有一小於或等於約100μm尺寸的處於任一液體、粉末或顆粒相的微粒。囊封體278是非導電的，提供實體支撐，並且在環境上保護該半導體裝置免於外部的元素及污染物。在一實施例中，囊封體278係利用膜輔助的模製製程來加以沉積。囊封體278是在半導體晶粒170被安裝到BGA封裝280之後加以沉積，並且不覆蓋主動表面174、接觸墊176或是絕緣層180的一頂表面。在囊封體278的回焊或固化之後，單粒化係利用一鋸刀或雷射切割工具282而發生在穿過基板144、囊封體160以及囊封體278，並且亦發生在凸塊164、半導體晶粒124以及半導體晶粒170之間，而成為個別的BGA封裝280。
圖11b係展示一來自圖11a的BGA封裝280內含作為嵌入式SoP扇出封裝286的部分。在如同圖11a中所示的BGA封裝280的單粒化之後，該些BGA封裝係根據該些對於如同在圖5i-5q中敘述的SoP封裝252所概述的製程而被形成為嵌入式SoP扇出封裝286。嵌入式SoP扇出封裝286可以利用或是不利用一類似於圖6a中所示的翹曲平衡層234之翹曲平衡層來加以做成。於是，嵌入式SoP扇出封裝280係有效率地提供水平及垂直的電互連給複數個內嵌在一個三維的扇出半導體封裝之內的半導體晶粒。嵌入式SoP扇出封裝280亦提供在控制整體封裝高度上的彈性。因為嵌入式SoP扇出封裝280在一RDL互連結構的完成之後並不需要額外的雷射鑽孔或是其它用於三維的垂直的互連的形成的處理，因此處理時間以及在處理額外的製程期間損壞晶圓的風險係被降低。再者，藉由在單一凸 塊接合製程中形成凸塊為一BGA封裝的部分並且接著在該些凸塊周圍形成囊封體，封裝的形成係被簡化，並且相對於包含利用多個凸塊接合製程而在穿過先前提供的囊封體所形成的開口中形成的凸塊之封裝而言是做成較不昂貴的。
類似於圖5g，圖12a係展示類似於SoP封裝196的SoP封裝308，其中半導體晶粒290係以該半導體晶粒的一背表面292被定向為朝向基板144的第二表面148而安裝到基板144。半導體晶粒290係類似於來自圖5e的半導體晶粒170，並且包含一相對於背表面292的主動表面294。主動表面294係包含接觸墊296以及一被保形地施加在該主動表面之上的絕緣或保護層298。絕緣層298的一部分係藉由LDA、蝕刻或是其它製程來加以移除，以在絕緣層298中形成開口300來露出接觸墊296。
一導電層304係被圖案化且沉積在主動半導體晶粒290、絕緣層298以及接觸墊296之上。導電層304可以是一或多層的Al、Cu、Sn、Ni、Au、Ag或是其它合適的導電材料。導電層304的沉積係使用PVD、CVD、電解的電鍍、無電的電鍍或是其它合適的製程。導電層304係沉積在絕緣層298之上以及在絕緣層298中的開口300內，並且連接至接觸墊296以運作為一RDL並且從半導體晶粒290延伸電連接至半導體晶粒290外部的點。不同於接觸墊296，導電層304並未被絕緣層298覆蓋，並且因此在半導體晶粒290被安裝到基板144時係相對於該絕緣層而露出。
在半導體晶粒290於一類似於圖5e及5f中所述的製程之製程中被安裝到基板144之後，基板144以及囊封體160係利用一鋸刀或雷射切割工具306而在凸塊164、半導體晶粒124以及半導體晶粒290之間被單 粒化，以形成個別的SoP封裝308。
在圖12b中，SoP封裝308係被展示進行類似於圖5i-5l中的SoP封裝196所進行的步驟之額外的封裝。圖12b係展示SoP封裝308係被安裝到分別類似於圖5i中所示的載體200、載體帶202以及熱剝離層204之載體312、載體帶314以及熱剝離層316。SoP封裝308係利用一拾放操作而被安裝在載體312之上，使得凸塊164的一部分係沉積在熱剝離層316的一部分的一厚度之內，並且由其所圍繞。類似地，半導體晶粒290的包含絕緣層298及導電層304之一部分亦沉積在熱剝離層316的一厚度或是單一層的載體帶或黏著劑之內，並且由其所圍繞。
圖12b係進一步展示一類似於囊封體或模製化合物210的囊封體或模製化合物320，其係類似於在圖5k及5l中所示的製程而形成在載體312之上以及在SoP封裝308之上及周圍。在一實施例中，如同在一類似於圖5k及5l的製程中所述，囊封體320係預分配或是積層在載體312之上，並且接著利用壓縮模製來加以固化。在SoP封裝308的封裝之後，囊封體320的一底表面322係被形成，並且沿著在該囊封體以及熱剝離層316之間的一介面延伸。囊封體320的底表面322係相對於導電層304的一底表面324凹陷或是垂直地偏置，以在底表面322以及底表面324之間產生一安全避開(stand-off)距離。載體312、載體帶314以及熱剝離層316係以一種類似於如同相關圖5m所述的載體200、載體帶202以及熱剝離層204的移除之方式而被移除，使得包含底表面324的導電層304被露出，以用於後續和一稍後形成的互連結構互連。
圖12c係展示一來自圖12b的封裝的SoP封裝308嵌入以作 為嵌入式SoP扇出封裝328的部分。在如上所述的囊封體320的形成以及載體312、載體帶314以及熱剝離層316的移除之後，嵌入式SoP扇出封裝328係根據該些對於如同在圖5m-5q中敘述的SoP封裝2S2所概述的製程來加以形成。在嵌入式SoP扇出封裝328中，互連結構330係在一類似於互連結構246的形成的製程中加以形成。如同在圖12c中所示，互連結構330係包含類似於來自圖5o的絕緣層230之絕緣層331，其係保形地被施加至囊封體320、絕緣層298、導電層304以及凸塊164，並且具有一依循囊封體320、絕緣層298、導電層304以及凸塊164的輪廓之第一表面。絕緣層331係具有一相對於該第一表面的第二平的表面。互連結構330亦包含類似於來自圖5o的導電層232之導電層332，其係透過導電層304而電連接至半導體晶粒290的接觸墊296。互連結構330係操作以從半導體晶粒124及290延伸電連接至嵌入式SoP扇出封裝328外部的點。再者，嵌入式SoP扇出封裝328可以在有或無類似於圖6a中所示的層234之翹曲平衡層下加以做成。
於是，嵌入式SoP扇出封裝328係有效率地提供水平及垂直的電互連給複數個內嵌在一個三維的扇出半導體封裝之內的半導體晶粒。嵌入式SoP扇出封裝328亦提供在控制整體封裝高度上的彈性。因為嵌入式SoP扇出封裝328在一RDL互連結構的完成之後並不需要額外的雷射鑽孔或是其它用於三維的垂直的互連的形成的處理，因此處理時間以及在處理額外的製程期間損壞晶圓的風險係被降低。再者，藉由在單一凸塊接合製程中形成凸塊為一BGA封裝的部分並且接著在該些凸塊周圍形成囊封體，封裝的形成係被簡化，並且相對於包含利用多個凸塊接合製程而在穿過先前提供的囊封體所形成的開口中形成的凸塊之封裝而言是做成較不昂 貴的。
類似於圖5g及12a，圖13a係展示BGA陣列封裝166，其中半導體晶粒334係以該半導體晶粒的一背表面336被定向為朝向基板144的第二表面148而安裝到基板144。半導體晶粒334係類似於來自圖5e的半導體晶粒170以及來自圖12a的半導體晶粒290，並且包含一相對於背表面336的主動表面338。主動表面338係包含接觸墊340以及一被保形地施加在該主動表面之上的絕緣或保護層342。絕緣層342的一部分係藉由LDA、蝕刻或是其它製程而被移除，以在絕緣層342中形成開口來露出接觸墊340。
一絕緣或保護層344係形成在半導體晶粒334的主動表面338之上，並且具有一保形地被施加至絕緣層342及接觸墊340並且依循其輪廓的第一表面。絕緣層344係具有一相對於該第一表面的第二平的表面。絕緣層344係包含一或多層的光敏的低固化溫度介電阻劑、光敏的複合阻劑、焊料光罩阻劑膜、液體模製化合物、SiO2、Si3N4、SiON、Ta2O5、Al2O3或是其它具有類似絕緣及結構的性質之材料。絕緣層344係利用印刷、旋轉塗覆、噴霧塗覆、疊層或是其它合適的製程來加以沉積。絕緣層344係接著利用UV曝光接著是顯影、或是其它合適的製程而被圖案化及固化。絕緣層344的一部分係藉由LDA、蝕刻或是其它合適的製程而被移除，以形成露出半導體晶粒334的接觸墊340以及絕緣層342的部分之開口，以包含一接著沉積的導電材料。
一導電層346係被圖案化且沉積在絕緣層344中的開口內以及在絕緣層342及接觸墊340之上。導電層346可以是一或多層的Al、Cu、Sn、Ni、Au、Ag或是其它合適的導電材料。導電層346的沉積係使用PVD、 CVD、電解的電鍍、無電的電鍍或是其它合適的製程。在一實施例中，導電層346係藉由Cu電鍍來加以形成，並且包含一電鍍晶種層。導電層346係運作為一RDL，並且從半導體晶粒334延伸電連接至半導體晶粒334外部的點。不同於接觸墊340，導電層346的一頂表面並未被絕緣層342或絕緣層344覆蓋，並且因此在半導體晶粒334被安裝到BGA封裝166時會相對於絕緣層342及344而露出。
在半導體晶粒334在一類似於圖5e及5f所述的製程之製程中被安裝到基板144之後，基板144以及囊封體160係利用一鋸刀或雷射切割工具350而在凸塊164、半導體晶粒124以及半導體晶粒334之間被單粒化，以分開被安裝到BGA封裝166的半導體晶粒334以形成個別的SoP封裝354。
在圖13b中，SoP封裝354係被展示進行類似於圖5i-5l中的SoP封裝196所進行的步驟之額外的封裝。圖13b係展示SoP封裝354被安裝到分別類似於圖5i中所示的載體200、載體帶202以及熱剝離層204之載體358、載體帶360以及熱剝離層362。SoP封裝354係利用一拾放操作而被安裝在載體358之上，使得凸塊164的一部分係沉積在熱剝離層362的一部分的一厚度內，並且由其所圍繞。絕緣層344以及導電層346係被安裝成和熱剝離層362的一表面為水平的，並且在一實施例中並不延伸在熱剝離層362的一部分或是單一層的載體帶或黏著劑的一厚度內並且不被其所圍繞。或者是，絕緣層344以及導電層346的一部分確實延伸在熱剝離層362或是單一層的載體帶或黏著劑的一厚度內，並且由其所圍繞。
圖13b進一步展示一類似於來自圖5k的囊封體或模製化合 物210之囊封體或模製化合物366是類似於在圖5k及5l中所示的製程而形成在載體358之上、以及在SoP封裝354之上及周圍。在一實施例中，囊封體366係在一類似於相關圖5k及5l所述的製程之製程中被預分配或積層在載體358之上，並且接著利用壓縮模製來加以固化。在SoP封裝354的封裝之後，囊封體366的一底表面368係被形成，並且沿著在該囊封體以及熱剝離層362之間的一介面延伸。囊封體366的底表面368係相對於導電層346的一底表面370以及絕緣層344的底表面372為共面的。在一實施例中，絕緣層344的底表面372以及導電層346的底表面370係相對於囊封體366的底表面368垂直地偏置。
在圖13c中，類似於相關圖5m所述的載體200、載體帶202以及熱剝離層204的移除，載體358、載體帶360以及熱剝離層362係被移除。包含底表面370的導電層346以及包含底表面372的絕緣層344係在載體358、載體帶360以及熱剝離層362的移除下被露出。在載體358、載體帶360以及熱剝離層362的移除之後，絕緣層344係藉由利用一溶劑及電漿的剝除或是其它合適的製程來加以移除，並且導電層346的晶種層係藉由蝕刻或是其它合適的製程來加以移除。在一實施例中，絕緣層344以及導電層346的晶種層係藉由利用雷射374的LDA而被移除。在絕緣層344的移除以及導電層346的晶種層的移除下，一淺凹洞或凹處可以相對於囊封體366的底表面368來加以形成。該凹處係在一互連結構在SoP封裝354之上的後續形成之前被做成。
圖13d係展示一來自圖13c的封裝的SoP封裝354內含作為嵌入式SoP扇出封裝376的部分。在如上所述的囊封體366的形成以及載體 358、載體帶360、熱剝離層362及絕緣層344的移除之後，嵌入式SoP扇出封裝376係根據該些對於如同在圖5m-5q中敘述的嵌入式SoP封裝252所概述的製程來加以形成。在嵌入式SoP扇出封裝376中，互連結構378係在一類似於互連結構246的形成的製程中加以形成。如同在圖13d中所示，互連結構378係包含類似於來自圖5o的絕緣層230之絕緣層379，其係保形地被施加至囊封體366、絕緣層342、導電層346以及凸塊164，並且具有一依循囊封體366、絕緣層342、導電層346以及凸塊164的輪廓之第一表面。絕緣層379係具有一相對於該第一表面的第二平的表面。互連結構378亦包含類似於來自圖5o的導電層232之導電層380，其係透過導電層346而電連接至半導體晶粒334的接觸墊340。互連結構378係操作以從半導體晶粒124及334延伸電連接至嵌入式SoP扇出封裝376外部的點。再者，嵌入式SoP扇出封裝376可以在有或無類似於圖6a中所示的層234之翹曲平衡層下加以做成。
於是，嵌入式SoP扇出封裝376係有效率地提供水平及垂直的電互連給複數個內嵌在一個三維的扇出半導體封裝之內的半導體晶粒。嵌入式SoP扇出封裝376亦提供在控制整體封裝高度上的彈性。因為嵌入式SoP扇出封裝376在一RDL互連結構的完成之後並不需要額外的雷射鑽孔或是其它用於三維的垂直的互連的形成的處理，因此處理時間以及在處理額外的製程期間損壞晶圓的風險係被降低。再者，藉由在單一凸塊接合製程中形成凸塊為一BGA封裝的部分並且接著在該些凸塊周圍形成囊封體，封裝的形成係被簡化，並且相對於包含利用多個凸塊接合製程而在穿過先前提供的囊封體所形成的開口中形成的凸塊之封裝而言是做成較不昂 貴的。
圖14係展示一類似於來自圖6a的嵌入式SoP扇出封裝252之個別的嵌入式SoP扇出封裝382。嵌入式SoP扇出封裝382與SoP扇出封裝252不同係在於包含銅凸塊384，該些銅凸塊384是SoP封裝386的部分並且類似於來自如同參考圖6a所述的SoP封裝196之凸塊164。銅凸塊384係被接合到互連結構388，該互連結構388係類似於圖6a中的互連結構246。互連結構388係在載體200、載體帶202以及熱剝離層204的移除之後形成在半導體晶粒170之上、在囊封體210之上、以及在銅凸塊384之上。在載體200、載體帶202以及熱剝離層204的移除之後，但是在互連結構388的形成之前，淺雷射鑽孔或清潔係被施加在凸塊384上，以清潔凸塊384的表面並且改善該些凸塊的接觸電阻。凸塊384係藉由利用RF蝕刻、LDA、電漿清潔、濕式清潔或是其它合適的製程以從銅凸塊384移除自然產生的氧化物來加以清潔。
互連結構388係形成在半導體晶粒170之上、在囊封體210之上、以及在銅凸塊384之上。互連結構388係包含一類似於在互連結構246中的導電層232之導電層400。導電層400是一或多層的Al、Cu、Sn、Ni、Au、Ag或是其它不會在凸塊384及導電層400之間造成脫層之合適的導電材料或合金。在一實施例中，導電層400係包含一黏著劑層及阻障層，其係TiW、Ti、CrCu、Al或是其它合適的金屬或金屬合金。藉由形成與銅凸塊384接觸的導電層400，銅凸塊384可以在不回焊該些凸塊下被接合到導電層400，以用於後續的電互連。
於是，嵌入式SoP扇出封裝382係有效率地提供水平及垂直 的電互連給複數個內嵌在一個三維的扇出半導體封裝之內的半導體晶粒。嵌入式SoP扇出封裝382亦提供在控制整體封裝高度上的彈性。因為嵌入式SoP扇出封裝382在一RDL互連結構的完成之後並不需要額外的雷射鑽孔或是其它用於三維的垂直的互連的形成的處理，因此處理時間以及在處理額外的製程期間損壞晶圓的風險係被降低。再者，藉由在單一凸塊接合製程中形成凸塊為一BGA封裝的部分並且接著在該些凸塊周圍形成囊封體，封裝的形成係被簡化，並且相對於包含利用多個凸塊接合製程而在穿過先前提供的囊封體所形成的開口中形成的凸塊之封裝而言是做成較不昂貴的。
圖15係展示一類似於來自圖8的嵌入式SoP扇出封裝262之個別的嵌入式SoP扇出封裝404。在嵌入式SoP扇出封裝404中，囊封體160的背表面222係從囊封體210露出。囊封體160的背表面222例如是藉由背面研磨來從囊封體160之上移除囊封體210而露出。背面研磨以露出背表面222係發生在互連結構246的形成之前、期間或是之後。或者是，在無囊封體210覆蓋囊封體160的背表面222下，囊封體160的背表面222係藉由形成囊封體210在SoP封裝196周圍而相對於囊封體210露出。
一金屬膜406係利用一黏著劑408而附接至囊封體210以及囊封體160的背表面222。金屬膜406係藉由疊層或是其它合適的製程來加以形成，以增進熱效能、或是提供有關嵌入式SoP扇出封裝404的電磁干擾之屏蔽。
在一實施例中，黏著劑408是一種熱介面材料(TIM)，例如熱環氧樹脂、熱導電膏、鋁氧化物、鋅氧化物、硼氮化物、粉末銀、或是 熱油脂，其係形成在囊封體210上以及在囊封體160的背表面222上。金屬膜406係作用為一散熱片，其係熱連接至黏著劑或TIM 408，並且被安裝在囊封體210以及囊封體160的背表面222之上。金屬膜或散熱片406可以是Cu、Al或是其它具有高導熱度的材料。金屬膜或散熱片406以及黏著劑或TIM 408係一起構成一導熱的路徑，其係有助於由半導體晶粒124及170所產生的熱的分布及耗散，以增加嵌入式SoP扇出封裝404的熱效能。
金屬膜406亦可以作用為一屏蔽層，並且可以是Al、鐵氧體或羰基鐵、不銹鋼、鎳銀、低碳鋼、矽鐵鋼、箔、導電的樹脂、以及其它能夠阻擋或吸收電磁干擾(EMI)、射頻干擾(RFI)、諧波失真、以及其它裝置間的干擾之金屬及合成物。金屬膜406係利用一電解的電鍍、無電的電鍍、濺鍍、PVD、CVD或是其它合適的金屬沉積製程而被圖案化且保形地沉積。金屬膜406亦可以是一種例如是碳黑或鋁薄片的非金屬材料，以降低EMI及RFI的影響。對於非金屬材料而言，金屬膜406可以藉由疊層、噴塗或是塗刷來施加。
於是，嵌入式SoP扇出封裝404係有效率地提供水平及垂直的電互連給複數個內嵌在一個三維的扇出半導體封裝之內的半導體晶粒。嵌入式SoP扇出封裝404亦提供在控制整體封裝高度上的彈性。因為嵌入式SoP扇出封裝404在一RDL互連結構的完成之後並不需要額外的雷射鑽孔或是其它用於三維的垂直的互連的形成的處理，因此處理時間以及在處理額外的製程期間損壞晶圓的風險係被降低。再者，藉由在單一凸塊接合製程中形成凸塊為一BGA封裝的部分並且接著在該些凸塊周圍形成囊封體，封裝的形成係被簡化，並且相對於包含利用多個凸塊接合製程而在穿 過先前提供的囊封體所形成的開口中形成的凸塊之封裝而言是做成較不昂貴的。
圖16係展示一類似於來自圖8的嵌入式SoP扇出封裝262之個別的嵌入式SoP扇出封裝412。在嵌入式SoP扇出封裝412中，囊封體160的背表面222係從囊封體210露出。囊封體160的背表面222例如是藉由背面研磨以從囊封體160之上移除囊封體210而露出。背面研磨以露出背表面222係發生在互連結構246的形成之前、期間或是之後。或者是，在囊封體210並不覆蓋囊封體160的背表面222下，囊封體160的背表面222係藉由在SoP封裝196周圍形成囊封體210而相對於囊封體210露出。
一些開口414係形成在囊封體160或210中，其係從背表面222或是嵌入式SoP扇出封裝412的一外表面延伸，部分但非完全穿過該囊封體。或者是，一些開口414係完全延伸穿過囊封體160以露出基板144。開口414係藉由利用雷射416的LDA或淺雷射鑽孔來加以形成。開口414係包含一些形成在半導體晶粒124及接合線158周圍之一週邊區域中的開口414a、以及一些形成在半導體晶粒124及接合線158之上的囊封體160的一中央區域中的開口414b。開口414包含漸縮或垂直的側壁，並且包含具有圓形、方形、矩形或是任意幾何形狀的橫截面區域。在一實施例中，開口414a係具有一深度大於開口414b的一深度、或者是開口414a及414b係具有相等的深度。在另一實施例中，開口414b係具有一大於開口414a的深度。開口414提供應力消除，並且降低嵌入式SoP扇出封裝412的一有效的厚度並且提供在電路板上溫度循環(TCoB)測試之潛在的改良。
於是，嵌入式SoP扇出封裝412係有效率地提供水平及垂直 的電互連給複數個內嵌在一個三維的扇出半導體封裝之內的半導體晶粒。嵌入式SoP扇出封裝412亦提供在控制整體封裝高度上的彈性。因為嵌入式SoP扇出封裝412在一RDL互連結構的完成之後並不需要額外的雷射鑽孔或是其它用於三維的垂直的互連的形成的處理，因此處理時間以及在處理額外的製程期間損壞晶圓的風險係被降低。再者，藉由在單一凸塊接合製程中形成凸塊為一BGA封裝的部分並且接著在該些凸塊周圍形成囊封體，封裝的形成係被簡化，並且相對於包含利用多個凸塊接合製程而在穿過先前提供的囊封體所形成的開口中形成的凸塊之封裝而言是做成較不昂貴的。
圖17係展示一類似於來自圖8的嵌入式SoP扇出封裝262之個別的嵌入式SoP扇出封裝420。在嵌入式SoP扇出封裝420中，囊封體160的背表面222係從囊封體210露出。囊封體160的背表面222例如是藉由背面研磨以從囊封體160之上移除囊封體210而露出。背面研磨以露出背表面222係發生在互連結構246的形成之前、期間或是之後。或者是，在囊封體210並不覆蓋囊封體160的背表面222下，囊封體160的背表面222係藉由在SoP封裝421周圍形成囊封體210而相對於囊封體210露出。
圖17的嵌入式SoP扇出封裝420與圖8的嵌入式SoP扇出封裝262不同是在於利用凸塊422來安裝半導體晶粒124至基板144，而不是利用接合線158。凸塊422係藉由利用一種蒸鍍、電解的電鍍、無電的電鍍、球式滴落或是網版印刷製程以沉積一種導電的凸塊材料在接觸墊132之上來加以形成。該凸塊材料可以是具有一選配的助熔溶劑之Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及其之組合。例如，該凸塊材料可以是共晶 Sn/Pb、高鉛的焊料或是無鉛的焊料。該凸塊材料係利用一適當的安裝或接合製程而被接合到接觸墊132。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來加以回焊，以形成球或凸塊422。在某些應用中，凸塊422係被回焊第二次以改善至接觸墊132的電性接觸。凸塊422亦可以被壓縮接合或是熱壓接合到接觸墊132。在一實施例中，凸塊422是銅微凸塊。半導體晶粒124係利用凸塊422並且是在該半導體晶粒的主動表面130被定向為朝向該基板下被安裝到基板144。
於是，嵌入式SoP扇出封裝420係有效率地提供水平及垂直的電互連給複數個內嵌在一個三維的扇出半導體封裝之內的半導體晶粒。嵌入式SoP扇出封裝420亦提供在控制整體封裝高度上的彈性。因為嵌入式SoP扇出封裝420在一RDL互連結構的完成之後並不需要額外的雷射鑽孔或是其它用於三維的垂直的互連的形成的處理，因此處理時間以及在處理額外的製程期間損壞晶圓的風險係被降低。再者，藉由在單一凸塊接合製程中形成凸塊為一BGA封裝的部分並且接著在該些凸塊周圍形成囊封體，封裝的形成係被簡化，並且相對於包含利用多個凸塊接合製程而在穿過先前提供的囊封體所形成的開口中形成的凸塊之封裝而言是做成較不昂貴的。
圖18係展示，一類似於來自圖6a的嵌入式SoP扇出封裝252之個別的嵌入式SoP扇出封裝430。嵌入式SoP扇出封裝430與SoP扇出封裝252不同是在於包含柱形導線凸塊或是切半的楔形接合線432以作為SoP封裝434的部分。柱形凸塊432係包含Cu或Au的柱形導線凸塊、切半的楔形Cu接合線、或是具有其它合適的導電材料的柱形凸塊或接合線。類 似於來自圖6a中敘述的SoP封裝196之凸塊164，柱形凸塊432係提供在嵌入式SoP扇出封裝430內之垂直的互連。柱形凸塊432係被接合到類似於圖6a中的互連結構246之互連結構436。互連結構436係在如同相關於圖5m所述的載體、載體帶以及一熱剝離層的移除之後，形成在半導體晶粒170之上、在囊封體210之上、以及在柱形凸塊432之上。在該載體、載體帶以及熱剝離層的移除之後，但是在互連結構436的形成之前，淺雷射鑽孔或清潔可被施加在柱形凸塊432上以清潔該些柱形凸塊的一表面並且改善該些柱形凸塊的接觸電阻。柱形凸塊432係藉由利用RF蝕刻、LDA、電漿清潔、濕式清潔或是其它合適的製程來移除自然產生的氧化物而被清潔。
互連結構436係形成在半導體晶粒170之上、在囊封體210之上、以及在柱形凸塊432之上。互連結構436係包含一類似於互連結構246中的導電層232之導電層438。導電層438是一或多層的Al、Cu、Sn、Ni、Au、Ag或是其它不會在柱形凸塊432以及導電層438之間造成脫層之合適的導電材料或合金。在一實施例中，導電層438係包含一黏著劑層及阻障層，其係TiW、Ti、CrCu、Al或是其它合適的金屬或金屬合金。藉由將導電層438形成為接觸柱形凸塊432，柱形凸塊432係在無回焊步驟下被接合到導電層438，以用於後續的電互連。
於是，嵌入式SoP扇出封裝430係有效率地提供水平及垂直的電互連給複數個內嵌在一個三維的扇出半導體封裝之內的半導體晶粒。嵌入式SoP扇出封裝430亦提供在控制整體封裝高度上的彈性，其包含小於1mm的整體封裝高度。SoP封裝434的整體寬度及長度係小於嵌入式SoP扇出封裝430的整體寬度及長度。在一實施例中，類似於圖6b中所示的SoP 封裝196的配置，SoP封裝434的寬度及長度分別小於嵌入式SoP扇出封裝430的寬度及長度至少50μm。柱形凸塊432的一高度係小於或等於半導體晶粒170以及晶粒附接帶178或晶粒附接黏著劑190之一組合的高度。或者是，柱形凸塊432的一高度係稍大於半導體晶粒170以及晶粒附接帶178或晶粒附接黏著劑190之一組合的高度，例如，大10μm。因為嵌入式SoP扇出封裝430在一RDL互連結構的完成之後並不需要額外的雷射鑽孔或是其它用於三維的垂直的互連的形成的處理，因此處理時間以及在處理額外的製程期間損壞晶圓的風險係被降低。再者，藉由形成柱形凸塊作為一BGA封裝的部分並且接著在該些柱形凸塊周圍形成囊封體，封裝的形成係被簡化，並且相對於包含利用多個凸塊接合製程而在穿過先前提供的囊封體所形成的開口中形成的凸塊之封裝而言是做成較不昂貴的。
在圖19a-19i中，另一種有效率地形成一個包含水平及垂直的互連之三維的SOP扇出封裝之製程係被描繪。圖19a係展示類似於來自圖5g的SoP封裝196的SoP封裝450，其中半導體晶粒170係以該半導體晶粒的一背表面172被定向為朝向基板144的第二表面148而安裝到基板144。半導體晶粒170係包含一相對於背表面172的主動表面174。主動表面174係包含接觸墊176以及一被保形地施加在該主動表面之上的絕緣或保護層180。絕緣層180的一部分係藉由LDA、蝕刻或是其它製程而被移除，以在絕緣層180中形成開口以露出接觸墊176。
一絕緣或保護層452係形成在絕緣層180以及半導體晶粒170的主動表面174之上。絕緣層452係具有一保形地施加至絕緣層180以及接觸墊176並且依循其輪廓的第一表面。絕緣層452係具有一相對於該第 一表面的第二平的表面。絕緣層452係包含一或多層的光敏的低固化溫度介電阻劑、光敏的複合阻劑、焊料光罩阻劑膜、液體模製化合物、SiO2、Si3N4、SiaN、Ta2O5、Al2O3或是其它具有類似絕緣及結構的性質之材料。絕緣層452係利用印刷、旋轉塗覆、噴霧塗覆、疊層或是其它合適的製程來加以沉積。絕緣層452是一非圖案化的永久絕緣層、或者是一臨時的保護層。
半導體晶粒170係被安裝到基板144，其中凸塊164被設置在該半導體晶粒的一週邊區域周圍，而且是在其覆蓋區之外。如上相關圖5d所述，凸塊164係被安裝到基板144，以形成一個由一些球柵陣列封裝450所構成的SoP封裝面板454。凸塊164的一高度係由一最終的整體封裝高度以及其它考量來決定。在一實施例中，在半導體晶粒170被安裝到基板144之後，在一類似於圖5e及5f所敘述的製程之製程中，基板144以及囊封體160係如同在圖5g中所示地利用一鋸刀或雷射切割工具，以在凸塊164、半導體晶粒124以及半導體晶粒170之間被單粒化。如同在圖5i中所示，單粒化的SoP封裝450係接著利用一拾放操作而被安裝到一具有載體帶以及一熱剝離層之臨時的載體，以用於如同在圖5k-5q中所示之後續的處理。或者是，SoP封裝面板454並未在半導體晶粒170的安裝之後立即被單粒化，而是如以下更詳細所述地維持完整的，以用於在面板或晶圓層級的後續處理。藉由在晶圓層級以未單粒化的面板454來處理SoP封裝450，對於一臨時的載體之需求係減輕，藉此簡化處理。SoP封裝面板454亦包含基準對準標記，其係使得形成SoP封裝450以作為一最終的嵌入式SoP扇出封裝的部分所需的額外處理變得容易。
圖19b係展示一囊封體或模製化合物458被預分配或積層在SoP封裝面板454之上、在凸塊164周圍以及在半導體晶粒170周圍。或者是，轉移模製或其它合適的製程可被用來施加囊封體458。囊封體458可以是聚合物複合材料，例如具有填充物或纖維的環氧樹脂、具有填充物或纖維的環氧丙烯酸酯、或是具有適合的填充物或纖維的聚合物。在一實施例中，在囊封體458中的填充物係包含處於任一液體、粉末或顆粒相的具有一小於或等於約100μm的尺寸的微粒，並且被選擇成具有一含量及特徵是促進該囊封體在凸塊164周圍以及在半導體晶粒170周圍的形成。在囊封體458中的填充物係進一步被選擇成控制翹曲並且改善封裝可靠度。囊封體458係被分配在SoP封裝面板454上，並且在一實施例中係被分配在該面板上的一中央位置460，例如是在四個相鄰的SoP封裝450的角落處，類似於圖5j中所示的交叉點208。囊封體458係被設置在SoP封裝面板454之上、在絕緣層452之上以及在半導體晶粒170的主動表面174之上，該主動表面係被定向為背對基板144，使得該囊封體係朝向絕緣層452及主動表面174來加以分配。因此，一重組晶圓或是扇出基板462係被形成，其係包含嵌入式SoP封裝450以及囊封體458。SoP封裝450係一起被嵌入在囊封體458中，該囊封體458是非導電的，並且在環境上保護該SoP封裝免於外部的元素及污染物。
圖19c係展示重組晶圓462被載入模具464中。模具464係藉由將模具464移動到重組晶圓462及囊封體458的周圍、或者是藉由將重組晶圓462移動到該模具中，以和重組晶圓462組合在一起。在一實施例中，模具464僅包含一第一或頂端部分和重組晶圓462組合在一起，而無第二或 底部模具部分。或者是，重組晶圓462以及囊封體458係被設置在一包含例如是頂端及底部部分的多個部分之模具內。如同在圖19c中所示，重組晶圓462係在無臨時的載體、載體帶或是熱剝離層之下，被設置在模具464之內。在SoP封裝面板454以及囊封體458被設置在模具464內之後，該囊封體可以部分或完全地固化。在囊封體458部分或完全地固化之後，重組晶圓462係從模具464移除。
圖19d係展示重組晶圓462從模具464移除。在一實施例中，囊封體458之一所要的厚度係形成在SoP封裝面板454之上，使得該囊封體並不覆蓋半導體晶粒170的主動表面174以及凸塊164的一表面。例如，一膜輔助的囊封體製程可被利用以避免囊封體458覆蓋半導體晶粒170的主動表面174以及凸塊164的一表面，因而後續的囊封體458的移除是不必要的。或者是，囊封體458係包含一被設置在絕緣層452、半導體晶粒170的主動表面174以及凸塊164的一表面之上並且覆蓋其之表面468。囊封體458的表面468係利用研磨機470以進行一研磨操作，以平坦化該表面並且降低該囊封體的一厚度，以有助於控制重組晶圓462以及SoP封裝450的翹曲。或者是，一化學蝕刻、LDA或是其它合適的製程係被用來移除及平坦化囊封體458，並且露出凸塊164的一表面、該囊封體的表面472以及絕緣層452的一表面。凸塊164之露出的表面可以是漸縮或是平的。囊封體458的一部分的移除係使得根據最終的封裝的一設計來調整一整體封裝高度變得容易。一包含淺雷射鑽孔之額外的清潔係被施加在凸塊164以及絕緣層452上以清潔該些凸塊及絕緣層的表面，以更完全地露出該些凸塊及絕緣層，並且改善該些凸塊的接觸電阻。此外，凸塊164亦可以利用具有一雷射的 LDA、RF蝕刻、電漿清潔或是濕式清潔來加以清潔，並且氧化物積聚係被移除。在一實施例中，凸塊164是Cu，並且在銅凸塊164上形成之自然產生的氧化物係藉由RF蝕刻來加以移除。
從圖19d繼續，圖19e係展示非圖案化的絕緣層452，其係形成作為一非圖案化的永久的絕緣層452a。永久的絕緣層452a的一部分係藉由利用雷射476的LDA來加以移除，以形成開口478。開口478亦藉由蝕刻或是其它合適的製程來加以形成。開口478係完全延伸穿過永久的絕緣層452a以露出半導體晶粒170的接觸墊176，並且藉由一互連結構的後續形成來提供和該些接觸墊之後續的電連接。
同樣從圖19d繼續，圖19f係展示非圖案化的絕緣層452，其係形成作為一臨時的保護層452b。臨時的保護層452b係藉由利用雷射480的LDA而被移除，以形成開口、凹洞或是凹處482。開口482亦藉由利用一溶劑、蝕刻、濕式化學蝕刻或是其它合適的製程來移除或剝除臨時的保護層452b而形成。開口482係露出包含絕緣層180及接觸墊176的半導體晶粒170，並且提供在半導體晶粒170的一覆蓋區內的絕緣層180以及囊封體458的表面472之間的垂直偏置。臨時的保護層452b的移除亦容許藉由一互連結構的形成之後續在凸塊164及接觸墊176之間的電連接。
從圖19e或19f的任一圖繼續，圖19g-19i係展示一類似於相關圖5q所述的互連結構246之互連結構或扇出的多互連RDL的形成。圖19g-19i的互連結構係透過凸塊164以及接觸墊176來提供在半導體晶粒124、半導體晶粒170以及該半導體晶粒外部的點之間的電互連。在移除絕緣層452(例如，不是永久的絕緣層452a、就是臨時的保護層452b)的至少一 部分之後，圖19g係展示該互連結構的一第一部分是藉由絕緣或保護層486的沉積及圖案化以及導電層488的沉積及圖案化而形成在重組晶圓462之上。
一絕緣層486係保形地施加至囊封體458、絕緣層452、絕緣層180、開口478、接觸墊176以及凸塊164，並且具有一依循其輪廓的第一表面。絕緣層486係具有一相對於該第一表面的第二平的表面。絕緣層486係包含一或多層的光敏的低固化溫度介電阻劑、光敏的複合阻劑、LCP、疊層化合物膜、具有填充物的絕緣膏、焊料光罩阻劑膜、液體模製化合物、顆粒模製化合物、聚醯亞胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3或是其它具有類似絕緣及結構的性質之材料。絕緣層486係利用印刷、旋轉塗覆、噴霧塗覆、疊層或是其它合適的製程來加以沉積。絕緣層486係接著利用UV曝光接著是顯影、或是其它合適的製程來加以圖案化及固化。絕緣層486的一部分係藉由LDA、蝕刻或是其它合適的製程來加以移除，以形成露出半導體晶粒170的接觸墊176以及凸塊164的開口。如同先前有關在圖5m或19d中的凸塊164所敘述的，凸塊164以及接觸墊176亦可以在絕緣層486的一部分的移除期間或是之後來加以清潔。
一導電層488係被圖案化且沉積在囊封體458、半導體晶粒170、絕緣層180以及絕緣層486之上。導電層488可以是一或多層的Al、Cu、Sn、Ni、Au、Ag或是其它不會在凸塊164以及導電層488之間造成脫層之合適的導電材料或合金。在一實施例中，導電層488係包含一黏著劑層及阻障層，其係一種焊料可濕性材料，例如CrCu、Au、TiCu合金、Ni或是NiV合金。導電層488的沉積係使用PVD、CVD、電解的電鍍、無電 的電鍍或是其它合適的製程。導電層488係沉積在絕緣層486中的開口內，並且完全延伸穿過該絕緣層以接觸凸塊164及接觸墊176。於是，導電層488係在不回焊該些凸塊下被接合到凸塊164，以用於後續的電互連。導電層488亦可以利用LDA或是其它合適的製程來加以圖案化，並且運作為一RDL以從半導體晶粒124及170延伸電連接到該半導體晶粒外部的點。
圖19h係展示絕緣或保護層490被保形地施加至絕緣層486以及導電層488，並且依循其輪廓。絕緣層490係包含一或多層的光敏的低固化溫度介電阻劑、光敏的複合阻劑、LCP、疊層化合物膜、具有填充物的絕緣膏、焊料光罩阻劑膜、液體模製化合物、顆粒模製化合物、聚醯亞胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3或是其它具有類似絕緣及結構的性質之材料。絕緣層490係利用印刷、旋轉塗覆、噴霧塗覆、疊層或是其它合適的製程來加以沉積。絕緣層490係接著利用UV曝光接著是顯影、或是其它合適的製程而被圖案化及固化。絕緣層490的一部分係藉由LDA、蝕刻或是其它合適的製程而被移除，以露出導電層488的部分。
一導電層492係被圖案化且沉積在導電層488、絕緣層490、SoP封裝450以及囊封體458之上。導電層492可以是一或多層的Al、Cu、Sn、Ni、Au、Ag或是其它合適的導電材料。導電層492的沉積係使用PVD、CVD、電解的電鍍、無電的電鍍或是其它合適的製程。導電層492係被設置在絕緣層490中的開口內，並且完全延伸穿過該絕緣層以接觸導電層488。導電層492亦可以利用LDA或是其它合適的製程來加以圖案化，並且運作為一RDL以從半導體晶粒124及170，穿過導電層488，延伸電連接至半導體晶粒124及170外部的點。額外的導電或RDL層係根據電氣信號完整性 的需求以及半導體晶粒124及176的一般配置及設計而被加到導電層488及492。
圖19i係展示絕緣或保護層494被保形地施加至絕緣層490以及導電層492，並且依循其輪廓。絕緣層494係包含一或多層的光敏的低溫度固化介電阻劑、光敏的複合阻劑、LCP、疊層化合物膜、具有填充物的絕緣膏、焊料光罩阻劑膜、液體模製化合物、顆粒模製化合物、聚醯亞胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3或是其它具有類似絕緣及結構的性質之材料。絕緣層494係利用印刷、旋轉塗覆、噴霧塗覆、疊層或是其它合適的製程來加以沉積。絕緣層494係接著利用UV曝光接著是顯影、或是其它合適的製程而被圖案化及固化。絕緣層494的一部分係藉由LDA、蝕刻或是其它合適的製程而被移除，以露出導電層492的部分。
一種導電的凸塊材料係利用一種蒸鍍、電解的電鍍、無電的電鍍、球式滴落或是網版印刷製程而沉積在導電層492以及絕緣層494之上。該凸塊材料可以是具有一選配的助熔溶劑之Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及其之組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料、或是無鉛的焊料。該凸塊材料係利用一適當的安裝或接合製程而被接合到導電層492。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來加以回焊，以形成球狀的球或凸塊496。在某些應用中，凸塊496係被回焊第二次，以改善至導電層492的電性接觸。在一實施例中，凸塊496係形成在一具有一潤濕層、阻障層以及黏著劑層的UBM之上。該些凸塊亦可以被壓縮接合或是熱壓接合到導電層492。凸塊496係代表一種可被形成在導電層492之上的互連結構類型。該互連結構亦可以使用導電膏、柱形 凸塊、微凸塊、導電柱、複合的互連或是其它電互連。絕緣層486、490及494與導電層488、492以及凸塊496係一起構成互連結構或是扇出的多互連RDL 498。
重組晶圓462以及互連結構498係利用鋸刀或雷射切割工具500，在凸塊496之間、在SoP封裝450之間以及穿過囊封體458及互連結構498而被單粒化，以形成嵌入式SoP扇出封裝502。在互連結構498的完成之後，SoP封裝450並不需要任何額外的雷射鑽孔或是其它用於三維的垂直的互連的形成的處理。在互連結構498及單粒化的完成之後，嵌入式SoP扇出封裝502係進行對於品質控制及品質保證的最後檢查，並且接著備妥於下一個層級的組裝。
於是，嵌入式SoP扇出封裝502係有效率地提供水平及垂直的電互連給複數個內嵌在一個三維的扇出半導體封裝之內的半導體晶粒。嵌入式SoP扇出封裝502亦提供在控制整體封裝高度上的彈性。因為嵌入式SoP扇出封裝502在一RDL互連結構的完成之後並不需要額外的雷射鑽孔或是其它用於三維的垂直的互連的形成的處理，因此處理時間以及在處理額外的製程期間損壞晶圓的風險係被降低。再者，藉由在單一凸塊接合製程中形成凸塊為一BGA封裝的部分並且接著在該些凸塊周圍形成囊封體，封裝的形成係被簡化，並且相對於包含利用多個凸塊接合製程而在穿過先前提供的囊封體所形成的開口中形成的凸塊之封裝而言是做成較不昂貴的。
圖20係展示一來自圖19f的封裝後的SoP封裝450被嵌入作為嵌入式SoP扇出封裝504的部分。如上相關於圖19f所述，在囊封體 458的形成以及臨時的保護層452b的移除之後，嵌入式SoP扇出封裝504係根據該些對於如同在圖19g-19i敘述的SoP封裝502所概述的製程來加以形成。在嵌入式SoP扇出封裝504中，互連結構506係在一類似於互連結構498的形成的製程中加以形成。如同在圖20中所示，互連結構506係包含類似於來自圖19g的絕緣層486之絕緣層508，其係保形地施加至囊封體458、絕緣層180、導電層176以及凸塊164，並且具有一依循其輪廓的第一表面。絕緣層508係具有一相對於該第一表面的第二平的表面。互連結構506亦包含類似於來自圖19g的導電層488之導電層510，其係電連接至半導體晶粒170的接觸墊176。互連結構506係操作以從半導體晶粒124及170延伸電連接至嵌入式SoP扇出封裝504外部的點。
於是，嵌入式SoP扇出封裝504係有效率地提供水平及垂直的電互連給複數個內嵌在一個三維的扇出半導體封裝之內的半導體晶粒。嵌入式SoP扇出封裝504亦提供在控制整體封裝高度上的彈性。因為嵌入式SoP扇出封裝504在一RDL互連結構的完成之後並不需要額外的雷射鑽孔或是其它用於三維的垂直的互連的形成的處理，因此處理時間以及在處理額外的製程期間損壞晶圓的風險係被降低。再者，藉由在單一凸塊接合製程中形成凸塊為一BGA封裝的部分並且接著在該些凸塊周圍形成囊封體，封裝的形成係被簡化，並且相對於包含利用多個凸塊接合製程而在穿過先前提供的囊封體所形成的開口中形成的凸塊之封裝而言是做成較不昂貴的。
儘管本發明的一或多個實施例已經詳細地描述，但本領域技術人員將會體認到對於那些實施例的修改及調適可以在不脫離如同在以下 的申請專利範圍中所闡述的本發明的範疇下加以完成。
124‧‧‧半導體晶粒(構件)
128‧‧‧背表面
130‧‧‧主動表面
132‧‧‧導電層
148‧‧‧第二表面
150‧‧‧基底材料
158‧‧‧接合線
160‧‧‧囊封體
164‧‧‧凸塊(球)
166‧‧‧BGA封裝
170‧‧‧半導體晶粒
172‧‧‧背表面
174‧‧‧主動表面
176‧‧‧接觸墊
178‧‧‧晶粒附接帶(黏著劑)
180‧‧‧絕緣(保護)層
196‧‧‧SoP封裝
210‧‧‧囊封體(模製化合物)
222‧‧‧背表面
228‧‧‧表面
230‧‧‧絕緣(保護)層
232‧‧‧導電層
234‧‧‧翹曲平衡層
236‧‧‧絕緣層
238‧‧‧導電層
242‧‧‧絕緣(保護)層
244‧‧‧凸塊(球)
246‧‧‧扇出的多互連RDL
252‧‧‧嵌入式SoP扇出封裝

Claims (15)

  1. 一種製造半導體裝置之方法，其係包括：提供一半導體封裝，進一步包含：(a)提供一基板；(b)設置一第一半導體晶粒於該基板的一第一表面之上；(c)沉積一第一囊封體於該第一半導體晶粒之上且完全地覆蓋該基板的該第一表面；以及(d)將複數個第一凸塊直接地設置在該基板的與該第一表面相對的一第二表面上；將一第二半導體晶粒設置在該些第一凸塊之間的該基板的該第二表面之上；在該基板、該第一半導體晶粒、該第一囊封體、該第一凸塊和該第二半導體晶粒之上與該基板、該第一半導體晶粒、該第一囊封體、該第一凸塊和該第二半導體晶粒周圍沉積一第二囊封體；以及在該些第一凸塊以及該第二半導體晶粒之上形成一互連結構。
  2. 如申請專利範圍第1項之方法，其進一步包含在該半導體封裝之上形成一翹曲平衡層。
  3. 如申請專利範圍第1項之方法，其進一步包含從該第二囊封體露出該半導體封裝的一表面。
  4. 如申請專利範圍第1項之方法，其進一步包含在該第一囊封體中形成一開口以提供應力消除。
  5. 一種半導體裝置，其係包括： 一半導體封裝，包含：(a)一基板；(b)一第一半導體晶粒，設置在該基板的一第一表面之上；(c)一第一囊封體，沉積在該第一半導體晶粒之上且完全地覆蓋該基板的該第一表面；以及(d)複數個第一凸塊，直接設置在該基板的與該第一表面相對的一第二表面上；一第二半導體晶粒，其係設置在該些第一凸塊之間的該基板的該第二表面之上；一第二囊封體，沉積在該基板、該第一半導體晶粒、該第一囊封體、該第一凸塊和該第二半導體晶粒之上與該基板、該第一半導體晶粒、該第一囊封體、該第一凸塊和該第二半導體晶粒周圍；以及一互連結構，其係形成在該些第一凸塊以及該第二半導體晶粒之上，並且電連接至該些第一凸塊以及該第二半導體晶粒。
  6. 如申請專利範圍第5項之半導體裝置，其中該第一半導體晶粒係包含一高度為小於該些第一凸塊的一高度。
  7. 如申請專利範圍第5項之半導體裝置，其進一步包含形成在該半導體封裝之上的一翹曲平衡層。
  8. 如申請專利範圍第5項之半導體裝置，其進一步包含形成在該半導體封裝之上的一屏蔽層或散熱器。
  9. 如申請專利範圍第5項之半導體裝置，其進一步包含在該半導體裝置的一外表面之該第二囊封體中的開口，以提供應力消除。
  10. 一種製造半導體裝置的方法，其係包括：提供一基板；設置一第一半導體晶粒於該基板的一第一表面之上；沉積一第一囊封體於該第一半導體晶粒和該基板之上；設置一第二半導體晶粒於該基板的一第二表面之上；以及形成複數個凸塊於該基板的該第二表面之上，且在該第二半導體晶粒周圍；以及沉積一第二囊封體於該基板、該第一半導體晶粒、該第一囊封體、該些凸塊和該第二半導體晶粒之上。
  11. 如申請專利範圍第10項之方法，其進一步包含：在該第一囊封體中形成一開口以提供應力消除。
  12. 如申請專利範圍第10項之方法，其中該第二半導體晶粒包括一高度為少於該些凸塊的一高度。
  13. 如申請專利範圍第10項之方法，其進一步包含在該第一半導體晶粒之上形成一翹曲平衡層。
  14. 如申請專利範圍第10項之方法，其進一步包含在該第一半導體晶粒之上設置一屏蔽層或散熱器。
  15. 如申請專利範圍第10項之方法，其進一步包含沉積該第二囊封體於該基板的一側表面周圍。
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