CN108666214A - 半导体器件以及用于形成低廓形嵌入式晶圆级球栅阵列模塑激光封装的方法 - Google Patents

半导体器件以及用于形成低廓形嵌入式晶圆级球栅阵列模塑激光封装的方法 Download PDF

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CN108666214A
CN108666214A CN201810430430.5A CN201810430430A CN108666214A CN 108666214 A CN108666214 A CN 108666214A CN 201810430430 A CN201810430430 A CN 201810430430A CN 108666214 A CN108666214 A CN 108666214A
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semiconductor
sealant
semiconductor devices
semiconductor element
opening
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CN108666214B (zh
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尹胜煜
J.A.卡帕拉斯
林耀剑
P.C.马里穆图
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Changdian Integrated Circuit Shaoxing Co ltd
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Stats Chippac Pte Ltd
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Abstract

本申请涉及半导体器件以及用于形成低廓形嵌入式晶圆级球栅阵列模塑激光封装的方法。一种半导体器件，具有半导体管芯，其具有沉积在半导体管芯之上和周围的密封剂。在密封剂的第一表面之上形成互连结构。形成从密封剂的第二表面到密封剂的第一表面的开口以暴露互连结构的表面。凸块形成为在开口内凹进并被设置在互连结构的表面之上。提供一种半导体封装。半导体封装被设置在密封剂的第二表面之上并且被电连接到凸块。在半导体封装之上形成多个互连结构以将半导体封装电连接到凸块。半导体封装包括存储器件。半导体器件包括小于1毫米的高度。开口包括通过激光直接烧蚀形成的锥形侧壁。

Description

半导体器件以及用于形成低廓形嵌入式晶圆级球栅阵列模塑 激光封装的方法
本申请是国家申请号为201310145987.1的发明专利申请的分案申请，该发明专利申请的申请日为2013年3月1日，发明名称为“半导体器件以及用于形成低廓形嵌入式晶圆级球栅阵列模塑激光封装的方法”。
国内优先权声明
本申请要求2012年3月2日提交的美国临时申请61/606,327的权益，该临时申请通过引用结合于本文。
技术领域
本发明一般涉及半导体器件，以及具体地涉及半导体器件以及形成扇出型嵌入式晶圆级球栅阵列（Fo-eWLB）的方法。
背景技术
半导体器件普遍存在于现代电子产品中。半导体器件在电子元件的数量和密度方面变化。分立半导体器件一般包含一种类型的电子元件，如发光二极管（LED）、小信号晶体管、电阻、电容、电感和功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件典型地包含数百至数百万个电子元件。集成半导体器件的例子包括微控制器、微处理器、电荷耦合器件（CCD）、太阳能电池和数字微镜器件（DMD）。
半导体器件执行范围广泛的功能，如信号处理、高速计算、传送和接收电磁信号、控制电子器件、将阳光转换成电力以及创建电视显示的可视投影。半导体器件存在于以下领域：娱乐、通信、功率转换、网络、计算机和消费产品。半导体器件也存在于军事应用、航空、汽车、工业控制器以及办公设备。
半导体器件利用半导体材料的电特性。半导体材料的原子结构允许通过施加电场或基电流或通过掺杂工艺来操纵其电导率。掺杂向半导体材料中引入杂质以操纵和控制半导体器件的导电率。
半导体器件包含有源和无源电气结构。包括双极和场效应晶体管的有源结构控制电流的流动。通过改变掺杂的程度和电场或基电流的施加，晶体管提升或限制电流的流动。包括电阻、电容、和电感的无源结构建立电压和电流之间必要的关系以执行多种电功能。将无源和有源结构电连接以来形成电路，这使得半导体器件能够执行高速计算和其它有用功能。
半导体器件一般使用两种复杂的制造工艺来制造，即前端制造和后端制造，每个制造工艺潜在地涉及的数百个步骤。前端制造涉及在半导体晶圆的表面上形成多个管芯（die）。典型地每个半导体管芯是相同的并包含通过电连接有源和无源器件来形成的电路。后端制造涉及使来自完成的晶圆的单独半导体管芯单片化并封装管芯以提供结构支撑和环境隔离。本文中使用的术语“半导体管芯”指词语的单数和复数形式，并且因此可以指单个半导体器件和多个半导体器件。
半导体制造的一个目的是制造更小的半导体器件。更小的器件典型地消耗更少的功耗，具有更高的性能，并且可以被更有效地制造。另外，更小的半导体器件具有更小的脚印(footprint)，这是更小的最终产品所期望的。可以通过前端工艺的改进得到具有更小，更高密度的有源和无源元件来实现更小的半导体管芯尺寸。后端工艺可以通过改进电互连和封装材料来得到具有更小脚印的半导体器件封装。
普通半导体器件布置包括将上部半导体封装层叠在下部半导体封装之上，即元件堆叠封装(PoP)。典型的，上部半导体封装利用凸块电连接到下部半导体封装。将互连凸块接合到下部半导体封装上的互连结构。互连凸块增加了PoP布置的高度而且可以导致半导体器件的翘曲。
发明内容
存在对稳健的互连结构以及具有降低的封装高度和更好的翘曲控制的PoP器件的需求。因此，在一个实施例中，本发明为制造半导体器件的方法，包括步骤：提供半导体管芯，在半导体管芯之上和周围沉积密封剂，在密封剂的第一表面之上形成互连结构，形成从密封剂的第二表面到密封剂的第一表面的开口以暴露互连结构的表面，以及形成在开口内凹进并被设置在互连结构的表面之上的凸块。
在另一个实施例中，本发明为制造半导体器件的方法，包括步骤：提供半导体管芯，在半导体管芯之上沉积密封剂，在密封剂之上形成第一互连结构，在密封剂中形成一开口以暴露第一互连结构，以及形成在第一互连结构之上并且在开口内凹进的第二互连结构。
在另一个实施例中，本发明为制造半导体器件的方法，包括步骤：提供第一半导体封装，以及在第一半导体封装中形成包括锥形的侧壁的开口和在开口内的第一互连结构。
在另一个实施例中，本发明为包括第一半导体封装的半导体器件。在第一半导体封装表面形成开口，开口包括锥形侧壁和在开口内的第一互连结构。
附图说明
图1示出了具有安装于其表面的不同类型的封装的印刷电路板(PCB)；
图2a-2c示出了安装于PCB的代表性半导体封装的进一步细节；
图3a-3c示出了具有通过切割道（saw street）分离的多个半导体管芯的半导体晶圆；
图4a-4n示出了形成包括薄膜互连结构以及具有锥形侧壁的凹进的垂直互连的扇出型嵌入式晶圆级球栅阵列(Fo-eWLB)的工艺；
图5示出了包括具有围绕半导体管芯形成的锥形通孔的Fo-eWLB封装元件堆叠封装器件；以及
图6示出了包括安装于印刷电路板的Fo-eWLB模塑激光封装(MLP)的元件堆叠封装器件。
具体实施方式
在下面关于附图的描述中，以一个或多个实施例的方式描述本发明，其中相似的数字表示相同或类似的元件。虽然本发明以实现本发明目标的最佳模式的方式进行描述，但本领域技术人员应该意识到的是，本发明意图涵盖可以包括在如所附的权利要求定义的本发明的精神和范围内的替代、变型和等效物，以及如下述公开和附图支持的它们的等效物。
半导体器件一般使用两种复杂的制造工艺来制造：前端制造和后端制造。前端制造涉及在半导体晶圆的表面上的多个管芯的形成。晶圆上的每个管芯包含有源和无源电元件，它们被电连接以形成功能电路。有源电元件（如晶体管和二极管）具有控制电流的流动的能力。无源电子元件（如电容、电感、电阻和变压器）建立在电压和电流之间的必要关系以执行电路功能。
通过一系列工艺步骤在半导体晶圆的表面之上形成无源和有源元件，一系列工艺步骤包括掺杂、沉积、光刻、刻蚀和平面化。掺杂通过如离子注入或热扩散的技术，将杂质引入到半导体材料中。掺杂工艺更改有源器件中半导体材料电导率以将半导体材料转换成绝缘体、导体，或响应电场或基电流而动态改变半导体材料导电率。晶体管包含根据需要设置的改变掺杂的类型和程度的区域以使得晶体管能够根据施加的电场或基电流来促进或抑制电流的流动。
有源和无源元件由具有不同电特性的材料层形成。该层可以通过部分由被沉积的材料的类型确定的多种沉积技术来形成。例如：薄膜沉积可以涉及化学气相沉积(CVD)、物理气相沉积(PVD)、电镀以及无电镀工艺。一般将每层图案化以形成有源元件、无源元件或元件间电连接的部分。
可以使用光刻来使该层图案化，光刻涉及在待图案化的层之上沉积光敏感材料，如光刻胶。使用光来将图案从光掩模转移到光刻胶上。在一个实施例中，使用溶剂将受光的光刻胶图案的部分去除，暴露待图案化的下面层部分。在另一个实施例中，使用溶剂将未受光的光刻胶图案部分（负光刻胶）去除，暴露待图案化的下面层部分。去除残余的光刻胶，留下图案化的层。备选地，通过使用如无电镀或电镀技术来将材料直接沉积到由先前沉积/刻蚀工艺形成的区域或空隙上来使一些类型的材料图案化。
图案化是基本操作，通过图案化，半导体晶圆表面上的顶层部分被去除。半导体晶圆的一部分可以使用光刻、光掩模、掩模、氧化物或金属去除、照相和制版以及微光刻来去除。光刻包括在中间掩模或光掩模中形成图案并将图案转移到半导体晶圆的表面层中。光刻以两步骤工艺在半导体晶圆的表面上形成有源和无源元件的水平维度。第一，将中间掩模或掩模上的图案转移到光刻胶层中。光刻胶是光敏材料，当暴露于光时光刻胶在结构和特性上经历变化。改变光刻胶的结构和特性的工艺作为负性光刻胶或正性光刻胶发生。第二，将光刻胶层转移到晶圆表面中。转移发生在刻蚀去除半导体晶圆的顶层没有被光刻胶覆盖的顶层部分时。光刻胶的化学性质是，使得光刻胶维持基本完整，并且当去除半导体晶圆的顶层未被光刻胶覆盖的部分时，抵抗被化学刻蚀溶液去除。形成、暴露和去除光刻胶的工艺，以及去除半导体晶圆的一部分的工艺，可以根据使用的特定抗蚀剂以及想要的结果进行修改。
在负性光刻胶中，在被称为的聚合的工艺中，光刻胶被暴露于光并且从可溶情况变成为不可溶情况。在聚合中，未聚合材料被暴露于光或能量源中，并且聚合物形成抗刻蚀性的交联材料。在多数负性抗蚀剂中，聚合物是聚异戊二烯。利用化学溶剂或显影剂去除可溶部分（即，未暴露于光的部分）在抗蚀剂层中留下对应于中间掩模上的不透明图案的孔。其图案存在于不透明区域上的掩模被称为亮场掩模(clear-field mask)。
在正性光刻胶中，在被称为光溶解的工艺中，光刻胶被暴露于光并且从相对不可溶情况变成为可溶得多的情况。在光溶解中，相对不可溶抗蚀剂被暴露于适当光能并且被转化为较可溶状态。抗蚀剂的光溶解部分可以在显影工艺中通过溶剂来去除。基本的正性光刻胶聚合物是酚醛聚合物(phenol-formaldehyde polymer)，又称为酚醛清漆树脂(phenol-formaldehyde novolak resin)。利用化学溶剂或显影剂来去除可溶部分（即，暴露于光的部分）在抗蚀剂层中留下对应于中间掩模上的透明图案的孔。其图案存在于透明区域中的掩模被称为暗场掩模(dark-field mask)。
去除未被光刻胶覆盖的半导体晶圆的顶层部分后，去除光刻胶的残余物，留下图案化的层。备选地，通过使用如无电镀或电镀的技术来将材料直接沉积到由先前沉积/刻蚀工艺形成的区域或空隙中来使一些类型的材料图案化。
在现有的图案之上沉积材料的薄膜可以使在下面的图案增大并造成不均匀平坦表面。需要均匀平坦表面来制造更小并且更密集组装的有源和无源元件。平面化可以用来从晶圆的表面去除材料并产生均匀平坦表面。平面化涉及利用抛光垫来抛光晶圆的表面。在抛光期间，向晶圆的表面添加研磨剂材料和腐蚀性的化学品。研磨剂的机械作用结合化学品的腐蚀性作用去除任何不规则表面形貌，得到均匀平坦表面。
后端制造指的是将完成的晶圆切割或单片化成单独的半导体管芯以及然后封装半导体管芯以用于结构支撑和环境隔离。为了单片化半导体管芯，沿被称为切割道或划线(scribe)的晶圆的非功能区域对晶圆进行刻痕并切断。使用激光切割工具或锯片来使晶圆单片化。在单片化后，将单独的半导体管芯安装到包括用于与其它系统元件互连的引脚或接触焊垫的封装衬底上。然后将在半导体管芯之上形成的接触焊垫连接到封装内的接触焊垫。可以利用焊料凸块、钉头凸块、导电胶或焊线来构成电连接。将密封剂或其它模制材料沉积在封装之上以提供物理支撑和电绝缘。随后将完成的封装插入电子系统并且使半导体器件的功能性对于其它系统元件是可用的。
图1示出了具有芯片承载衬底的电子器件50或具有安装在其表面上的多个半导体封装的印刷电路板(PCB)52。取决于应用，电子器件50可以具有一种类型的半导体封装或多种类型的半导体封装。出于说明的目的，图1中示出不同类型的半导体封装。
电子器件50可以为使用半导体封装来执行一个或多个电功能的单机系统。备选地，电子器件50可以是更大系统的子元件。例如，电子器件50可以是蜂窝式电话、个人数字助理(PDA)、数字视频摄录机(DVC)或其它电子通信器件的部分。备选地，电子器件50可以是图形卡、网络接口卡或其它可以被插入到计算机中的信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路(ASIC)、逻辑电路、模拟电路、RF电路、分立器件，或其它半导体管芯或电元件。小型化和降低重量对于产品被市场接受是必要的。必须减小半导体器件之间的距离以实现更高的密度。
图1中，PCB 52提供用于结构支撑和安装在PCB上的半导体封装的电互接的普通基板。使用蒸发、电镀、无电镀、丝网印刷或其它合适的金属沉积工艺来在PCB 52的表面上或层内形成导电信号迹线54。信号迹线54提供半导体封装的每个、安装的元件以及其它外部系统元件之间的电通信。迹线54还提供至半导体封装的每个的电源和接地连接。
在一些实施例中，半导体器件具有两个封装级。第一级封装是用于将半导体管芯机械地和电气地附着到中间载体的技术。第二级封装涉及将中间载板机械地和电气地附着到PCB。在另外的实施例中，半导体器件可以仅具有第一级封装，其中将管芯被直接机械地和电气地安装到PCB上。
出于说明的目的，在PCB 52上示出包括焊线封装56和倒装管芯58的若干种类型的第一级封装。此外，示出安装在PCB 52上的若干种类型的第二级封装，包括球栅阵列(BGA)60、凸块芯片载板(BCC)62、双列直插封装(DIP)64、触点阵列封装(LGA)66、多管芯模块(MCM)68、四侧扁平无引线封装(QFN)70以及四侧扁平封装72。取决于系统需求，利用第一和第二级封装样式的任意组合配置的半导体封装以及其它电子元件的任意组合可以被连接到PCB 52上。在一些实施例中，电子器件50包括单配附（single attached）半导体封装，而另外的实施例要求多个互连的封装。通过在单个衬底之上组合一个或多个半导体封装，制造商可以将预制的元件结合成电子器件和系统。因为半导体封装包括复杂的功能性，所以可以使用较便宜的元件和最新型的制造工艺来制造电子器件。所得到的器件较不易失效并且制造较便宜而导致对于消费者的较低成本。
图2a-2c示出示范的半导体封装。图2a示出安装在PCB 52上的DIP 64的进一步细节。半导体管芯74包括有源区域，该有源区域包含形成在管芯内作为有源器件、无源器件、导电层和介电层实现的模拟或数字电路，并且根据管芯的电气设计进行电互连。例如，电路可以包括在半导体管芯74的有源区域内形成的一个或多个晶体管、二极管、电感、电容、电阻以及其它电路元件。接触焊垫76是一层或多层导电材料，如铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)或银(Ag)，并且被电连接到在半导体管芯74内的电路元件上。在DIP 64的装配期间，使用金-硅共熔层或如热性环氧树脂（thermal epoxy）或环氧树脂的粘接材料将半导体管芯74安装在中间载板78上。封装体包括如聚合物或陶瓷的绝缘封装材料。导体引线80和焊线82提供半导体管芯74和PCB 52之间的电互连。将密封剂84沉积在封装体之上以用于通过防止水分和微粒进入封装并污染半导体管芯74或焊线82来进行环境保护。
图2b示出安装在PCB 52上的BCC 62的进一步细节。使用底充胶（underfill）或环氧树脂粘接材料92来将半导体管芯88安装在载板90上。接合线94提供接触焊垫96和98之间的第一级封装互连。将模制化合物或密封剂100沉积在半导体管芯88和接合线94之上以提供器件的物理支撑和电隔离。使用如电镀或无电镀的合适的金属沉积工艺来在PCB 52的表面之上形成接触焊垫102以防止氧化。将接触焊垫102电连接到PCB 52中的一个或多个导电信号迹线(signal traces)54。在BCC 62的接触焊垫98和PCB 52的接触焊垫102之间形成凸块104。
图2c中，利用倒装样式的第一级封装将半导体管芯58面朝下地安装在的中间载板106上。半导体管芯58的有源区域108包含根据管芯的电气设计形成的作为有源器件、无源器件、导电层和介电层实现的模拟或数字电路。例如，电路可以包括在有源区域108内形成的一个或多个晶体管、二极管、电感、电容、电阻以及其它电路元件。通过凸块110将半导体管芯58电气地和机械地连接到载板106。
使用凸块112利用BGA样式的第二级封装来将BGA 60电气地和机械地连接到PCB52。通过凸块110、信号线114和凸块112将半导体管芯58电气地连接到PCB 52中的导电信号迹线54。将模制化合物或密封剂116沉积在半导体管芯58和载板106之上以提供器件的物理支撑和电隔离。倒装半导体管芯提供从半导体管芯58上的有源器件到PCB 52上的导电迹线的短的导电路径，以便降低信号传播距离、降低电容并提高整体电路性能。在另一个实施例中，在没有中间载板106的情况下，可以使用倒装形式的第一级封装来将半导体管芯58机械地和电气地直接连接到PCB 52。
图3a示出半导体晶圆120，该半导体晶圆120具有如硅、锗、砷化镓、磷化铟或碳化硅的基板材料122以用于结构支撑。在通过非有源（non-active）、管芯内(inter-die)晶圆区域或如前所述的切割道126分离的晶圆120上形成多个半导体管芯或元件124。切割道126提供切割区域来将半导体晶圆120单片化成单独半导体管芯124。
图3b示出半导体晶圆120的一部分的截面图。每个半导体管芯124具有背面128和包含模拟和数字电路的有源表面130，模拟和数字电路实现为在管芯内形成并且根据管芯的电气设计和功能电互连的有源器件、无源器件、导电层和介电层。例如，电路可以包括在有源表面130内形成的一个或多个晶体管、二极管和其它电路元件以实现模拟电路和数字电路，如数字信号处理器（DSP）、ASIC、存储器或其它信号处理电路。半导体管芯124还可以包含集成无源器件(IPD)，如用于RF信号处理的电感、电容和电阻。在一个实施例中，半导体管芯124为倒装类型器件。
使用PVD、CVD、电镀、无电镀或其它合适的金属沉积工艺在有源表面130之上形成电气导电层132。导电层132可以是一层或多层Al、Cu、Sn、Ni、Au、Ag或其它适合的电气导电材料。导电层132操作为电连接到有源表面130上的电路的接触焊垫。如图3b所示，可以将导电层132形成为被并排布置在离半导体管芯124的边缘第一距离处的接触焊垫。备选地，可以将导电层132形成为在多排中偏移的接触焊垫，以使得第一排接触焊垫被布置在距离管芯的边缘的第一距离处，并且与第一排焊垫相间的第二排接触焊垫被布置在距离管芯的边缘的第二距离处。
图3c中，使用锯片或激光切割工具134通过切割道126来将半导体晶圆120单片化成单独倒装类型半导体管芯124。备选地，半导体晶圆120的单片化可以使用水力喷射(water jet)来去除切割道126内的材料来完成。
图4a-4m示出形成具有带精细的I/O间距（pitch）和低高度的嵌入式eWLB-MLP的低廓形(profile)PoP器件的工艺。图4a示出衬底或载板150的一部分，包含临时或牺牲基材，如硅、锗、砷化镓、磷化铟、碳化硅、树脂、氧化铍、玻璃或其它用于结构支撑的合适的低成本、刚性材料。界面层或双面胶带152在载板150之上形成作为临时粘接接合膜、刻蚀阻挡层或剥离层。
图4b中，例如，使用拾取和放置操作将来自图3c的半导体管芯124安装到界面层152和载板150上，其中，有源表面130朝向所述载板。
使用拾取和放置操作将来自图3a-3c的半导体管芯124放置并安装到载板150上，其中，接触焊垫132朝向载板。图4b示出安装到载板150上的半导体管芯124。载板150具有足够的面积作为重组晶圆（reconsitituted wafer）156来保持许多半导体管芯124。图4c示出重组晶圆156的平面图，其中多个半导体管芯124被安装到载板150上并以一距离分离。
图4d中，使用焊膏印刷(paste printing)、压缩模塑(compressive molding)、传递模塑、液封模塑(liquid encapsulant molding)、真空压合(vacuum lamination)、薄膜辅助模塑(film-assisted molding)、旋涂或其它敷料器来将密封剂或模塑化合物154沉积在界面层152和载板150之上，以及半导体管芯124之上和周围。密封剂154在半导体管芯124的背面128之上形成，并且可以在随后的背研磨步骤中减薄。还可以沉积密封剂154以使得密封剂与背面128共面，而不覆盖背面。密封剂154可以是聚合物复合材料，如具有填料的环氧树脂、具有填料的环氧丙烯酸酯或具有适当填料的聚合物。密封剂154是非导电的，提供物理支撑并且在环境上保护半导体器件不受外部元件和污染之害。
图4e示出被密封剂154覆盖的复合衬底或重组晶圆156。图4e中，密封剂154的表面158经过研磨机160的研磨操作来平面化该表面并降低密封剂的厚度。也可以使用化学刻蚀来去除并平面化密封剂154。密封剂154的一部分被去除以减薄该密封剂。也可以去除密封剂154的一部分以暴露或减薄半导体管芯124的背面。
图4f中，通过化学刻蚀、机械剥蚀、化学机械平面化（CMP）、机械研磨、热烘、UV射线、激光扫描或湿法去膜(wet stripping)来从复合衬底156去除载板150和界面层152以促进半导体管芯124的有源表面130和半导体管芯外围周围的密封剂154之上的互连结构的形成。
图4g中，在密封剂154和半导体管芯124之上形成堆积式（built-up）互连结构168。堆积式互连结构168包括使用如溅射、电镀、和无电镀的图案化和金属沉积工艺形成的电气导电层或再分配层(RDL)172。导电层172可以是一层或多层Al、Cu、Sn、Ni、Au、Ag或其它合适的电气导电材料。将导电层172电连接到接触焊垫132。取决于半导体管芯124的设计和功能，导电层172的其它部分可以是电共通(electrically common)或电隔离的。
堆积式互连结构168进一步包括使用PVD、CVD、印刷、悬涂、喷涂、烧结或热氧化来在导电层172之间形成的绝缘或钝化层174以用于电隔离。绝缘层174包含一层或多层二氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅、氧化钽(Ta2O5)、氧化铝(Al2O3)或具有类似绝缘和结构特性的其它材料。在一个实施例中，堆积式互连结构168具有10微米（μm）/10μm的线宽/间距。
图4h中，使用蒸发、电镀、无电镀、植球(ball drop)或丝网印刷工艺来将电气导电凸块材料沉积在堆积式互连结构168之上并将其电连接到表面176上的导电层172。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu焊料以及它们的组合连同可选的焊剂溶液。例如，凸块材料可以是共熔的Sn/Pb、高铅焊料或无铅焊料。使用合适的附着或接合工艺将凸块材料接合到导电层172。在一个实施例中，通过在其熔点之上加热凸块材料来使该材料回流以形成球或凸块190。在一些应用中，使凸块190二次回流以改善与导电层172的电接触。可以在凸块190下形成凸块下金属化(UBM)层。凸块190也可以被压缩接合到导电层172。凸块190代表可以在导电层172之上形成的一种类型的互连结构。该互连结构也可以使用接合线、钉头凸块、微凸块或其它电互连。
图4i中，使用激光202通过激光直接烧蚀（LDA）来去除密封剂154的一部分以形成向下延伸至互连结构168的导电层172的开口或通孔200。备选地，可以经由图案化的光刻胶层通过刻蚀工艺来形成开口200。开口200具有包括在开口200顶部处的较大直径并且在开口200底部处的较小直径的锥形形状。当将凸块材料206插入开口200中时，锥形通孔形状实现稳定的焊料球载入。锥形通孔形状还提供稳定的凸块材料高度以供均匀的PoP层叠。形成开口200后，清洗开口200和暴露的导电层172。导电层172的无残留表面为PoP层叠提供了改进的焊料润湿性和电气连接。
图4j示出了去除密封剂154的一部分之后复合衬底156的平面视图。密封剂154围绕并覆盖半导体管芯124。在密封剂154中在半导体管芯124周围形成开口200。开口200向下延伸到导电层172的表面178并且包括锥形侧壁。开口200的锥形侧壁基于较大的顶部直径和较小的底部直径，其在焊料填充期间帮助实现稳定的焊料球载入以及实现稳定的焊料高度以供均匀的PoP层叠。
图4k中，使用蒸发、电镀、无电镀、植球或丝网印刷工艺将电气导电凸块材料206沉积在导电层172之上。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合，连同可选的焊剂溶液。例如，凸块材料可以是共熔的Sn/Pb、高铅焊料或无铅焊料。使用合适的附着或接合工艺来将凸块材料接合到导电层172上。
图4l中，通过将在其熔点之上加热凸块材料来使该材料回流以在导电层172的表面178之上形成球或凸块208，并且使凸块材料在开口200内凹进。在一些应用中，使凸块208二次回流以改善与导电层172的电接触。凸块208也可以被压缩接合或热压缩接合到导电层172。凸块208代表可以在导电层172之上形成的一种类型的互连结构。该互连结构也可以使用钉头凸块、微凸块或其它电互接。当将上部封装层叠在下部封装220之上以形成PoP器件时，通过在开口200内连接顶部和底部封装，在互连208以上的开口200部分降低了PoP封装的高度。通过创建薄的3D PoP eWLB器件，半导体器件250的较小的封装廓形改进了半导体器件热性能、电性能以及翘曲表现。
图4m中，形成凸块208之后，利用锯片或激光切割器件218将复合衬底或重组晶圆156单片化成单独半导体器件220。通过在复合衬底之上安装附加的半导体器件之前单片化复合衬底156，通过在单独器件级而不是重构晶圆级安装附加的半导体管芯，来完成单独半导体器件220的形成。备选地，如图5中所示，在将附加的半导体器件安装到复合衬底之后单片化复合衬底156。
图4n示出单片化后的单独半导体器件220。半导体器件220为eWLB结构。在一个实施例中，半导体器件220具有250μm的高度。半导体器件220包括凹进的垂直互连或凸块208以适应如存储器件的以倒装管芯朝向的高密度半导体管芯。半导体器件220也适应混合的半导体管芯尺寸。
图5示出单独半导体器件250作为3D PoP结构，其中半导体管芯252层叠在半导体管芯124之上。半导体器件250也适应混合的半导体管芯尺寸。例如，具有存储功能的半导体管芯和应用处理器管芯可以采用层叠配置的方式被集成到半导体器件250中。
通过导电层256将半导体管芯252电连接到互连结构254。密封剂258围绕半导体管芯252，并且可以是聚合物复合材料，如具有填料的环氧树脂、具有填料的环氧丙烯酸酯或具有适当填料的聚合物。密封剂258是非导电的，提供物理支撑并且在环境上保护半导体器件不受外部元件和污染之害。通过导电通孔260将半导体器件250进一步电连接以适应以倒装管芯朝向的如存储器件的半导体管芯252。半导体器件250具有减少的厚度。在一个实施例中，底部封装262的厚度为480μm，从底部封装的上表面开始，顶部封装上表面的高度264为520μm，并且顶部封装的厚度266为450μm。半导体器件250具有970μm的厚度。使用常规eWLB的层叠器件的封装厚度为1.4mm。图4n的凹进的互连结构208降低了具有层叠在下部封装之上的上部封装的器件250的高度，这是因为互连208以上的开口200部分取消了上部封装互连结构部分的高度，其与互连结构208电连接以形成导电通孔260。通过创建薄的3DPoP eWLB器件，半导体器件250的较小的封装廓形改进了半导体器件热性能、电性能以及翘曲表现。
图6示出采用PoP配置的组装并安装在的PCB上的层叠封装，PoP配置包括如图4a-4n所示的底部器件。PoP组件包括具有250μm的体厚度和500μm的高度的顶部eWLB封装280。包括顶部和底部封装的eWLB-MLP层叠器件的总高度为750-770μm。封装280包含具有电连接到凸块材料282的有源表面的半导体管芯，凸块材料282被沉积在开口284中。开口284是具有顶部处较大的开口且在底部处较小开口的锥形。在将凸块材料插入到开口284中时，开口284的锥形形状实现稳定的焊料球载入。锥形通孔形状还提供稳定的凸块材料高度以供均匀的PoP层叠。凸块材料282在延伸至互连结构288的开口284中形成穿过密封剂286的导电通孔。互连结构288包括一个或多个导电和绝缘层。通过凸块材料290将互连结构288电连接到电路板或衬底294上的接触焊垫292。用导电材料填充的锥形通孔增加了封装强度和稳健性以减少在如管芯接合、载板分离、处理和传输的制造工艺期间互连结构的破裂和其它损坏。通过创建薄的3D PoP eWLB器件，半导体器件较小的封装廓形改进了半导体器件的热性能、电性能以及翘曲表现。
尽管已经详细介绍了本发明的一个或多个实施例，本领域技术人员应该意识到的是，在不背离如下述权利要求所声明的本发明的精神的范围内可以对那些实施例进行修改和变型。

Claims (15)

1.一种制造半导体器件的方法，包括：
提供半导体管芯；
在所述半导体管芯周围沉积密封剂；
在所述密封剂上形成互连结构，并与所述半导体管芯的有源表面接触；
形成穿过所述密封剂延伸至所述互连结构的开口；以及
在所述开口内形成凸块，并连接到所述互连结构。
2.根据权利要求1所述的方法，进一步包括在所述互连结构上形成多个凸块。
3.根据权利要求1所述的方法，其中，所述半导体器件包括小于1毫米的高度。
4.根据权利要求1所述的方法，还包括在所述密封剂上设置半导体封装。
5.根据权利要求4所述的方法，其中，所述半导体封装包括存储器件。
6.一种制造半导体器件的方法，包括：
提供半导体管芯；
在所述半导体管芯周围沉积密封剂；
形成穿过所述密封剂的开口；以及
形成在所述密封剂的开口内凹进的凸块以用于外部电互连。
7.根据权利要求6所述的方法，进一步包括在所述密封剂和所述半导体管芯上形成互连结构。
8.根据权利要求1所述的方法，其中，所述半导体器件包括小于1毫米的高度。
9.根据权利要求6所述的方法，进一步包括在所述半导体管芯和所述密封剂上设置半导体封装。
10.根据权利要求9所述的方法，其中，所述半导体封装包括存储器件。
11.一种半导体器件，包括：
半导体管芯，；
沉积在所述半导体管芯周围的密封剂，其中一开口穿过所述所述密封剂；
形成在所述密封剂的开口内凹进的凸块以用于外部电互连。
12.根据权利要求11所述的半导体器件，进一步包括在所述密封剂和所述半导体管芯上形成的互连结构。
13.根据权利要求11所述的半导体器件，其中，所述半导体器件包括小于1毫米的高度。
14.根据权利要求11所述的半导体器件，进一步包括在所述半导体器件和所述密封剂上设置的半导体封装。
15.根据权利要求14所述的半导体器件，其中，所述半导体封装包括存储器件。
CN201810430430.5A 2012-03-02 2013-03-01 半导体器件以及用于形成低廓形嵌入式晶圆级球栅阵列模塑激光封装的方法 Active CN108666214B (zh)

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