SG10201506633SA - Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (ewlb-mlp) - Google Patents

Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (ewlb-mlp)

Info

Publication number
SG10201506633SA
SG10201506633SA SG10201506633SA SG10201506633SA SG10201506633SA SG 10201506633S A SG10201506633S A SG 10201506633SA SG 10201506633S A SG10201506633S A SG 10201506633SA SG 10201506633S A SG10201506633S A SG 10201506633SA SG 10201506633S A SG10201506633S A SG 10201506633SA
Authority
SG
Singapore
Prior art keywords
ewlb
mlp
semiconductor device
forming
grid array
Prior art date
Application number
SG10201506633SA
Other languages
English (en)
Inventor
Seung Wook Yoon
Jose A Caparas
Yaojian Lin
Pandi C Marimuthu
Original Assignee
Stats Chippac Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Ltd filed Critical Stats Chippac Ltd
Publication of SG10201506633SA publication Critical patent/SG10201506633SA/en

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    • H—ELECTRICITY
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
SG10201506633SA 2012-03-02 2013-02-25 Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (ewlb-mlp) SG10201506633SA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201261606327P 2012-03-02 2012-03-02
US13/772,683 US9293401B2 (en) 2008-12-12 2013-02-21 Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLP-MLP)

Publications (1)

Publication Number Publication Date
SG10201506633SA true SG10201506633SA (en) 2015-10-29

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Application Number Title Priority Date Filing Date
SG10201506633SA SG10201506633SA (en) 2012-03-02 2013-02-25 Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (ewlb-mlp)
SG2013013891A SG193122A1 (en) 2012-03-02 2013-02-25 Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (ewlb-mlp)

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Application Number Title Priority Date Filing Date
SG2013013891A SG193122A1 (en) 2012-03-02 2013-02-25 Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (ewlb-mlp)

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US (2) US9293401B2 (zh)
CN (2) CN108666214B (zh)
SG (2) SG10201506633SA (zh)
TW (2) TWI680540B (zh)

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US20130228917A1 (en) 2013-09-05
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US20160141238A1 (en) 2016-05-19

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