SG10201506633SA - Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (ewlb-mlp) - Google Patents
Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (ewlb-mlp)Info
- Publication number
- SG10201506633SA SG10201506633SA SG10201506633SA SG10201506633SA SG10201506633SA SG 10201506633S A SG10201506633S A SG 10201506633SA SG 10201506633S A SG10201506633S A SG 10201506633SA SG 10201506633S A SG10201506633S A SG 10201506633SA SG 10201506633S A SG10201506633S A SG 10201506633SA
- Authority
- SG
- Singapore
- Prior art keywords
- ewlb
- mlp
- semiconductor device
- forming
- grid array
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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- H01L2924/351—Thermal stress
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Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201261606327P | 2012-03-02 | 2012-03-02 | |
US13/772,683 US9293401B2 (en) | 2008-12-12 | 2013-02-21 | Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLP-MLP) |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10201506633SA true SG10201506633SA (en) | 2015-10-29 |
Family
ID=49042375
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10201506633SA SG10201506633SA (en) | 2012-03-02 | 2013-02-25 | Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (ewlb-mlp) |
SG2013013891A SG193122A1 (en) | 2012-03-02 | 2013-02-25 | Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (ewlb-mlp) |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG2013013891A SG193122A1 (en) | 2012-03-02 | 2013-02-25 | Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (ewlb-mlp) |
Country Status (4)
Country | Link |
---|---|
US (2) | US9293401B2 (en) |
CN (2) | CN108666214B (en) |
SG (2) | SG10201506633SA (en) |
TW (2) | TWI680540B (en) |
Families Citing this family (36)
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US8810024B2 (en) | 2012-03-23 | 2014-08-19 | Stats Chippac Ltd. | Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units |
US10049964B2 (en) | 2012-03-23 | 2018-08-14 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units |
US9842798B2 (en) | 2012-03-23 | 2017-12-12 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a PoP device with embedded vertical interconnect units |
US9837303B2 (en) | 2012-03-23 | 2017-12-05 | STATS ChipPAC Pte. Ltd. | Semiconductor method and device of forming a fan-out device with PWB vertical interconnect units |
JP6273362B2 (en) * | 2013-12-23 | 2018-01-31 | インテル コーポレイション | Package on package structure and method for manufacturing the same |
US9870946B2 (en) | 2013-12-31 | 2018-01-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer level package structure and method of forming same |
CN104795377B (en) * | 2014-01-17 | 2019-02-19 | 恩智浦美国有限公司 | Semiconductor devices with lead net |
CN104882386B (en) * | 2014-02-27 | 2019-03-01 | 恩智浦美国有限公司 | Semiconductor devices grid array package |
US20150282367A1 (en) * | 2014-03-27 | 2015-10-01 | Hans-Joachim Barth | Electronic assembly that includes stacked electronic components |
US9595485B2 (en) * | 2014-06-26 | 2017-03-14 | Nxp Usa, Inc. | Microelectronic packages having embedded sidewall substrates and methods for the producing thereof |
US9343385B2 (en) * | 2014-07-30 | 2016-05-17 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device comprising a chip substrate, a mold, and a buffer layer |
US10319607B2 (en) * | 2014-08-22 | 2019-06-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-on-package structure with organic interposer |
DE102014114982B4 (en) * | 2014-10-15 | 2023-01-26 | Infineon Technologies Ag | Method of forming a chip package |
US9806066B2 (en) | 2015-01-23 | 2017-10-31 | Samsung Electronics Co., Ltd. | Semiconductor package including exposed connecting stubs |
CN107039369A (en) * | 2015-01-23 | 2017-08-11 | 三星半导体(中国)研究开发有限公司 | Encapsulation includes the encapsulation stacking structure and its manufacture method of the encapsulation |
SG10201501021PA (en) * | 2015-02-10 | 2016-09-29 | Delta Electronics Int L Singapore Pte Ltd | Package structure |
SG10201501172RA (en) * | 2015-02-13 | 2016-09-29 | Delta Electronics Int’L Singapore Pte Ltd | Packaging process of electronic component |
US20160240457A1 (en) * | 2015-02-18 | 2016-08-18 | Altera Corporation | Integrated circuit packages with dual-sided stacking structure |
US9786623B2 (en) | 2015-03-17 | 2017-10-10 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming PoP semiconductor device with RDL over top package |
US9899285B2 (en) * | 2015-07-30 | 2018-02-20 | Semtech Corporation | Semiconductor device and method of forming small Z semiconductor package |
US9761571B2 (en) * | 2015-09-17 | 2017-09-12 | Deca Technologies Inc. | Thermally enhanced fully molded fan-out module |
US20170092594A1 (en) * | 2015-09-25 | 2017-03-30 | Qualcomm Incorporated | Low profile package with passive device |
US10727207B2 (en) | 2016-07-07 | 2020-07-28 | Agency For Science, Technology And Research | Semiconductor packaging structure and method of forming the same |
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CN108666214A (en) | 2018-10-16 |
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US10622293B2 (en) | 2020-04-14 |
US9293401B2 (en) | 2016-03-22 |
CN108666214B (en) | 2022-03-08 |
TWI680540B (en) | 2019-12-21 |
US20130228917A1 (en) | 2013-09-05 |
TWI606523B (en) | 2017-11-21 |
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