JP5064768B2 - 電子部品および電子部品の製造方法 - Google Patents
電子部品および電子部品の製造方法 Download PDFInfo
- Publication number
- JP5064768B2 JP5064768B2 JP2006316202A JP2006316202A JP5064768B2 JP 5064768 B2 JP5064768 B2 JP 5064768B2 JP 2006316202 A JP2006316202 A JP 2006316202A JP 2006316202 A JP2006316202 A JP 2006316202A JP 5064768 B2 JP5064768 B2 JP 5064768B2
- Authority
- JP
- Japan
- Prior art keywords
- conductive material
- electronic component
- electronic
- manufacturing
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 61
- 238000000034 method Methods 0.000 title description 41
- 239000000758 substrate Substances 0.000 claims abstract description 96
- 239000004020 conductor Substances 0.000 claims abstract description 80
- 239000004065 semiconductor Substances 0.000 claims abstract description 76
- 230000000149 penetrating effect Effects 0.000 claims abstract description 16
- 230000003287 optical effect Effects 0.000 claims description 11
- 238000003825 pressing Methods 0.000 claims description 5
- 239000002184 metal Substances 0.000 description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 19
- 238000010586 diagram Methods 0.000 description 19
- 229910052710 silicon Inorganic materials 0.000 description 19
- 239000010703 silicon Substances 0.000 description 19
- 239000000463 material Substances 0.000 description 17
- 239000011347 resin Substances 0.000 description 9
- 229920005989 resin Polymers 0.000 description 9
- 238000005530 etching Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 229910010293 ceramic material Inorganic materials 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 239000007788 liquid Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/147—Semiconductor insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/483—Containers
- H01L33/486—Containers adapted for surface mounting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/049—Wire bonding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
- H05K3/4015—Surface contacts, e.g. bumps using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Description
400,500,500A,500B,500C 電子部品
101,201,301 半導体基板
101A,201A,301A,301B 貫通穴
102,202,302,303 マスクパターン
102A,202A,302A,302B,303A,303B 開口部
103,203,304 絶縁膜
104,204,305,306 導電材料
105,106,205,206,307,308,309 金属層
107、310,311 突起部
301C 凹部
312,312A,312B,502,503 電子素子
501,501A,501B 開口部
504 デバイス
Claims (7)
- 半導体基板を貫通する貫通穴に導電材料が埋設されてなる構造を有する配線基板を複数形成する第1の工程と、
複数の前記配線基板のうちのいずれかの前記導電材料に、導電性の突起部を設置する第2の工程と、
複数の前記配線基板を貼り合わせるとともに、各々の前記配線基板の各々の前記導電材料を、前記突起部により電気的に接続する第3の工程と、を有し、
複数の前記半導体基板のいずれかに、電子素子を実装する凹部を形成する工程と、
当該凹部に電子素子を実装する工程と、をさらに有しており、
前記第1の工程では、前記貫通穴とともに前記凹部の底部に素子実装用貫通穴が形成されて、該素子実装用貫通穴に前記導電材料が埋設され、
前記電子素子は前記素子実装用貫通穴に埋設された前記導電材料に接続されて実装され、
前記第3の工程では、前記電子素子が複数の前記半導体基板の貼り合わせにより前記凹部に封止されることを特徴とする電子部品の製造方法。 - 前記突起部は、ボンディングワイヤにより形成されることを特徴とする請求項1記載の電子部品の製造方法。
- 前記第3の工程では、前記突起部が押圧されることにより、各々の前記配線基板の各々の前記導電材料が電気的に接続されることを特徴とする請求項2記載の電子部品の製造方法。
- 前記電子素子は光機能性素子よりなり、
前記第1の工程では、複数の前記半導体基板のいずれかに、当該光機能性素子への光の入射または当該光機能性素子からの光の出射のための開口部が形成されることを特徴とする請求項1乃至3いずれか一項に記載の電子部品の製造方法。 - 半導体基板を貫通する貫通穴に導電材料が埋設されてなる構造を有する複数の配線基板を有し、
複数の前記半導体基板のいずれかに凹部が形成され、
前記凹部の底部には素子実装用貫通穴が形成されて、該素子実装用貫通穴に導電材料が埋設された構造を有し、
電子素子が前記素子実装用貫通穴に埋設された導電材料に接続され、前記凹部に実装されており、
前記複数の配線基板が互いに貼り合わせられるとともに、当該貼り合わせによって押圧される電気接続部材により、各々の前記配線基板の各々の前記半導体基板を貫通する貫通穴に埋設された前記導電材料が電気的に接続され、前記電子素子は前記凹部に封止されていることを特徴とする電子部品。 - 前記電子素子は光機能性素子よりなり、前記複数の配線基板のいずれかに、当該光機能性素子への光の入射または当該光機能性素子からの光の出射のための開口部が形成されていることを特徴とする請求項5記載の電子部品。
- 前記凹部が形成された前記配線基板と貼り合わせられる前記配線基板の、当該凹部に面する側の反対側に、別の電子素子が実装されていることを特徴とする請求項5または6記載の電子部品。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006316202A JP5064768B2 (ja) | 2006-11-22 | 2006-11-22 | 電子部品および電子部品の製造方法 |
KR1020070109932A KR101436034B1 (ko) | 2006-11-22 | 2007-10-31 | 전자 부품 및 그 제조 방법 |
TW096143839A TWI442529B (zh) | 2006-11-22 | 2007-11-20 | 電子零件 |
US11/943,194 US7894201B2 (en) | 2006-11-22 | 2007-11-20 | Electronic component and method for manufacturing the same |
EP07022679.0A EP1926136B1 (en) | 2006-11-22 | 2007-11-22 | Electronic component and method for manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006316202A JP5064768B2 (ja) | 2006-11-22 | 2006-11-22 | 電子部品および電子部品の製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2008130934A JP2008130934A (ja) | 2008-06-05 |
JP2008130934A5 JP2008130934A5 (ja) | 2009-10-01 |
JP5064768B2 true JP5064768B2 (ja) | 2012-10-31 |
Family
ID=39185720
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006316202A Active JP5064768B2 (ja) | 2006-11-22 | 2006-11-22 | 電子部品および電子部品の製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7894201B2 (ja) |
EP (1) | EP1926136B1 (ja) |
JP (1) | JP5064768B2 (ja) |
KR (1) | KR101436034B1 (ja) |
TW (1) | TWI442529B (ja) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8072079B2 (en) * | 2008-03-27 | 2011-12-06 | Stats Chippac, Ltd. | Through hole vias at saw streets including protrusions or recesses for interconnection |
US11302617B2 (en) * | 2008-09-06 | 2022-04-12 | Broadpak Corporation | Scalable semiconductor interposer integration |
CN102144291B (zh) * | 2008-11-17 | 2015-11-25 | 先进封装技术私人有限公司 | 半导体基板、封装与装置 |
JP5568170B2 (ja) * | 2009-02-23 | 2014-08-06 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
JP5367616B2 (ja) * | 2009-02-23 | 2013-12-11 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
US8804368B2 (en) * | 2009-04-30 | 2014-08-12 | Sony Corporation | Downward-facing optical component module |
US8796850B2 (en) * | 2009-09-01 | 2014-08-05 | Tohoku University | Wiring connection method and functional device |
US20110175218A1 (en) | 2010-01-18 | 2011-07-21 | Shiann-Ming Liou | Package assembly having a semiconductor substrate |
US20110186960A1 (en) * | 2010-02-03 | 2011-08-04 | Albert Wu | Techniques and configurations for recessed semiconductor substrates |
US8847376B2 (en) | 2010-07-23 | 2014-09-30 | Tessera, Inc. | Microelectronic elements with post-assembly planarization |
JP2012049298A (ja) * | 2010-08-26 | 2012-03-08 | Tohoku Univ | 多孔質金属を電気的接続に用いたデバイス、及び配線接続方法 |
US9029689B2 (en) * | 2010-12-23 | 2015-05-12 | Sunpower Corporation | Method for connecting solar cells |
DE102012107668A1 (de) | 2012-08-21 | 2014-03-20 | Epcos Ag | Bauelementanordnung |
WO2015136998A1 (ja) * | 2014-03-10 | 2015-09-17 | 三菱重工業株式会社 | マルチチップモジュール、オンボードコンピュータ、センサインターフェース基板、及びマルチチップモジュール製造方法 |
US9481572B2 (en) | 2014-07-17 | 2016-11-01 | Texas Instruments Incorporated | Optical electronic device and method of fabrication |
FR3042064B1 (fr) * | 2015-10-05 | 2019-06-14 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Dispositif pour connecter au moins un nano-objet associe a une puce permettant une connexion a au moins un systeme electrique externe et son procede de realisation |
US11600432B2 (en) | 2016-02-24 | 2023-03-07 | Murata Manufacturing Co., Ltd. | Substrate-embedded transformer with improved isolation |
WO2018004686A1 (en) * | 2016-07-01 | 2018-01-04 | Intel Corporation | Device, method and system for providing recessed interconnect structures of a substrate |
EP3483921A1 (en) * | 2017-11-11 | 2019-05-15 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Embedding known-good component in known-good cavity of known-good component carrier material with pre-formed electric connection structure |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5061987A (en) * | 1990-01-09 | 1991-10-29 | Northrop Corporation | Silicon substrate multichip assembly |
JP2940269B2 (ja) | 1990-12-26 | 1999-08-25 | 日本電気株式会社 | 集積回路素子の接続方法 |
JP3994531B2 (ja) * | 1998-07-21 | 2007-10-24 | 株式会社デンソー | 半導体圧力センサの製造方法 |
JP2001135785A (ja) * | 1999-11-08 | 2001-05-18 | Seiko Epson Corp | 半導体チップ、マルチチップパッケージ、半導体装置、および電子機器、並びにこれらの製造方法 |
DE10163799B4 (de) | 2000-12-28 | 2006-11-23 | Matsushita Electric Works, Ltd., Kadoma | Halbleiterchip-Aufbausubstrat und Verfahren zum Herstellen eines solchen Aufbausubstrates |
JP2002290030A (ja) * | 2001-03-23 | 2002-10-04 | Ngk Spark Plug Co Ltd | 配線基板 |
US6873529B2 (en) * | 2002-02-26 | 2005-03-29 | Kyocera Corporation | High frequency module |
US7485489B2 (en) * | 2002-06-19 | 2009-02-03 | Bjoersell Sten | Electronics circuit manufacture |
JP3908147B2 (ja) | 2002-10-28 | 2007-04-25 | シャープ株式会社 | 積層型半導体装置及びその製造方法 |
US7361593B2 (en) | 2002-12-17 | 2008-04-22 | Finisar Corporation | Methods of forming vias in multilayer substrates |
JP2004273690A (ja) * | 2003-03-07 | 2004-09-30 | Stanley Electric Co Ltd | 極小光源用led素子およびその製造方法 |
JP2004363351A (ja) * | 2003-06-05 | 2004-12-24 | Mitsubishi Electric Corp | 積層型の半導体装置 |
JP4312631B2 (ja) * | 2004-03-03 | 2009-08-12 | 三菱電機株式会社 | ウエハレベルパッケージ構造体とその製造方法、及びそのウエハレベルパッケージ構造体から分割された素子 |
JP4354398B2 (ja) * | 2004-12-27 | 2009-10-28 | 三菱重工業株式会社 | 半導体装置及びその製造方法 |
US7262622B2 (en) | 2005-03-24 | 2007-08-28 | Memsic, Inc. | Wafer-level package for integrated circuits |
JP2006316202A (ja) | 2005-05-13 | 2006-11-24 | Takashi Sawaguchi | 末端ビニリデン基を有する末端反応性オリゴマー |
-
2006
- 2006-11-22 JP JP2006316202A patent/JP5064768B2/ja active Active
-
2007
- 2007-10-31 KR KR1020070109932A patent/KR101436034B1/ko not_active Application Discontinuation
- 2007-11-20 US US11/943,194 patent/US7894201B2/en active Active
- 2007-11-20 TW TW096143839A patent/TWI442529B/zh active
- 2007-11-22 EP EP07022679.0A patent/EP1926136B1/en active Active
Also Published As
Publication number | Publication date |
---|---|
EP1926136A3 (en) | 2008-10-29 |
KR101436034B1 (ko) | 2014-09-01 |
TWI442529B (zh) | 2014-06-21 |
US20080117607A1 (en) | 2008-05-22 |
JP2008130934A (ja) | 2008-06-05 |
EP1926136B1 (en) | 2017-01-11 |
US7894201B2 (en) | 2011-02-22 |
KR20080046558A (ko) | 2008-05-27 |
EP1926136A2 (en) | 2008-05-28 |
TW200828545A (en) | 2008-07-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5064768B2 (ja) | 電子部品および電子部品の製造方法 | |
US7973397B2 (en) | Package substrate having embedded semiconductor chip and fabrication method thereof | |
JP5106460B2 (ja) | 半導体装置及びその製造方法、並びに電子装置 | |
JP2007027451A (ja) | 回路基板及びその製造方法 | |
KR100907508B1 (ko) | 패키지 기판 및 그 제조방법 | |
JP5179046B2 (ja) | 電子部品および電子部品の製造方法 | |
JP2008205123A (ja) | 電子部品内蔵型配線基板及びその実装部品 | |
JP4955349B2 (ja) | 半導体装置 | |
US20160099206A1 (en) | Wafer level packaging of electronic device | |
JP2004356630A (ja) | 電気的相互接続のためのスタンドオフ/マスク構造 | |
JP2009004648A (ja) | 配線基板 | |
TWI624011B (zh) | 封裝結構及其製法 | |
US20110216514A1 (en) | Combined multilayer circuit board having embedded components and manufacturing method of the same | |
JP4837328B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
JP4848789B2 (ja) | 電子装置の製造方法 | |
KR101582548B1 (ko) | 인터포져 제조 방법 및 이를 이용한 반도체 패키지 제조 방법 | |
JP2005294875A (ja) | 半導体装置及びその製造方法 | |
TWI825870B (zh) | 電子封裝結構及其製造方法 | |
KR101089840B1 (ko) | 회로 기판 모듈 및 그의 제조 방법 | |
KR100997880B1 (ko) | 칩 내장 기판의 패드와 기판을 접속 제조하는 방법 및 이를적용한 다기능 인쇄회로기판 | |
JP4117477B2 (ja) | 光モジュール及びその製造方法並びに電子機器 | |
JP2015159160A (ja) | 配線基板及び接続構造 | |
KR20090015619A (ko) | 인쇄회로 기판 및 그 제조 방법과 그를 이용한 전자 기기 | |
US7827679B1 (en) | Thermal management circuit board and methods of producing the same | |
JP2001148443A (ja) | 多層配線基板及び半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090819 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20090819 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100301 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120321 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120518 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120807 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120809 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5064768 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150817 Year of fee payment: 3 |