CN107146780A - 半导体芯片及半导体装置 - Google Patents
半导体芯片及半导体装置 Download PDFInfo
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- CN107146780A CN107146780A CN201610580840.9A CN201610580840A CN107146780A CN 107146780 A CN107146780 A CN 107146780A CN 201610580840 A CN201610580840 A CN 201610580840A CN 107146780 A CN107146780 A CN 107146780A
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Abstract
一种半导体装置包含衬底主体、多个第一凸块衬垫和再分布层RDL。所述第一凸块衬垫邻近于所述衬底主体的表面而安置,所述第一凸块衬垫中的每一者具有来自俯视图的第一构型,所述第一构型具有沿着第一方向的第一宽度和沿着垂直于所述第一方向的第二方向的第二宽度,且所述第一构型的所述第一宽度大于所述第一构型的所述第二宽度。所述RDL邻近于所述衬底主体的所述表面而安置,且所述RDL包含安置于两个第一凸块衬垫之间的第一部分。
Description
技术领域
本发明涉及一种半导体芯片、一种半导体装置及其制造方法,且更明确地说涉及一种半导体芯片和一种能够在所述半导体芯片下方布设再分布层(RDL)的半导体装置,及其制造方法。
背景技术
常规半导体封装可包含衬底和安置在衬底上的半导体芯片。衬底可包含RDL和凸块衬垫。半导体芯片可包含接合到衬底的芯片接合区域中的凸块衬垫的支柱。RDL可需要绕过芯片接合区域或远离芯片接合区域布设,以避免RDL与芯片接合区域中的凸块衬垫之间的短路。然而,此配置可导致RDL中增加的路径长度和增加的阻抗,且因此不利地影响半导体封装内电路的性能。
发明内容
在一方面中,一种半导体芯片包含芯片主体、至少一个第一支柱和至少一个第二支柱。第一支柱邻近于芯片主体的表面而安置。第一支柱具有来自仰视图的第一构型,所述第一构型具有沿着第一方向的第一宽度和沿着垂直于所述第一方向的第二方向的第二宽度,且所述第一构型的所述第一宽度大于所述第一构型的所述第二宽度。第二支柱邻近于芯片主体的表面而安置,所述第二支柱具有来自仰视图的第二构型,且所述第一构型的形状不同于所述第二构型的形状。
在一方面中,一种半导体装置包含一衬底主体、多个第一凸块衬垫和一RDL。第一凸块衬垫邻近于衬底主体的表面而安置,所述第一凸块衬垫中的每一者具有来自俯视图的第一构型,所述第一构型具有沿着第一方向的第一宽度和沿着垂直于所述第一方向的第二方向的第二宽度,且所述第一构型的第一宽度大于所述第一构型的第二宽度。RDL邻近于衬底主体的表面而安置,且RDL包含安置于两个第一凸块衬垫之间的第一部分。
在一方面中,一种半导体装置包含衬底主体、衬底主体上的芯片接合区域,和RDL。RDL邻近于衬底主体的的表面而安置。RDL包含安置在芯片接合区域内的第一部分和安置在芯片接合区域外部的第二部分。第一部分的宽度小于第二部分的宽度。
在一方面中,一种制造方法包含:(a)提供衬底主体,所述主体包含邻近于其表面的衬垫;(b)形成邻近于衬底主体的表面且覆盖衬垫的光致抗蚀剂层;(c)在所述光致抗蚀剂层中形成第一开口和第二开口以暴露所述衬垫,其中第二开口的形状不同于第一开口的形状,且第二开口中的每一者的横截面面积大体上等于第一开口中的每一者的横截面面积;(d)用金属同时填充所述第一开口和所述第二开口;以及(e)移除所述光致抗蚀剂层。
附图说明
图1说明根据本发明的实施例的半导体芯片的仰视图。
图2说明根据本发明的实施例的图1中展示的区A1的放大视图。
图3说明根据本发明的实施例的图2中展示的区A1的横截面图。
图4说明根据本发明的实施例的半导体装置的俯视图。
图5说明根据本发明的实施例的图4中展示的区A4的放大视图。
图6说明根据本发明的实施例的图5中展示的区A4的横截面图。
图7说明根据本发明的实施例的图5中展示的区A4的横截面图。
图8说明半导体封装的俯视图。
图9说明根据本发明的实施例的半导体装置的俯视图。
图10说明根据本发明的实施例的图9中展示的区A9的放大视图。
图11说明根据本发明的实施例的图10中展示的区A9的横截面图。
图12说明根据本发明的实施例的图10中展示的区A9的横截面图。
图13说明根据本发明的实施例的半导体装置的横截面图。
图14说明根据本发明的实施例的半导体装置的横截面图。
图15说明根据本发明的实施例的半导体装置的俯视图。
图16A、图16B、图16C和图16D说明根据本发明的实施例的制造方法。
具体实施方式
本发明提供一种允许减小RDL中的电路路径长度的改进的半导体封装结构。
半导体芯片的支柱可接合到衬底的芯片接合区域中的凸块衬垫,且芯片接合区域中的每一凸块衬垫的大小和位置可对应于对应支柱的大小和位置。邻近支柱之间的间距可较小,且对应地,芯片接合区域中的邻近凸块衬垫之间的间距也可较小。因此,芯片接合区域中的两个邻近凸块衬垫之间的间隙可较小。如果RDL的一部分穿过所述间隙,那么存在归因于RDL接触凸块衬垫中的一或两者而发生的短路的风险。为解决此些问题,RDL可经设计以绕过芯片接合区域中的凸块衬垫或远离所述凸块衬垫而布设。然而,此绕过或远离布设可大大增加RDL中电路路径的路径长度(和阻抗)。因此,此绕过或远离布设设计可能会不利地影响半导体封装内的电路的性能。
为解决以上问题,形成改进的结构,其经由改进的支柱结构和凸块衬垫结构提供RDL中的电路路径的较短路径长度(和较低阻抗)。所描述的技术可有助于产生具有改进的性能的电路。改进的支柱结构提供邻近支柱之间更宽的间隙,且改进的凸块衬垫结构提供邻近凸块衬垫之间更宽的间隙,使得RDL的一部分可直接穿过两个邻近凸块衬垫之间的间隙空间而非绕过或远离布设。短路的风险较低,因为RDL的所述部分将不容易接触所述两个凸块衬垫中的一或两者。
图1说明根据本发明的实施例的半导体芯片10的仰视图。半导体芯片10包含用于电连接的第一支柱101和第二支柱102。第一支柱101具有来自仰视图的第一构型,且第二支柱102具有来自仰视图的第二构型,且第一构型的形状不同于第二构型的形状。在一或多个实施例中,第一支柱101的第一构型的形状大体上为椭圆形,且第二支柱102的第二构型的形状大体上为圆形。
第一支柱101沿着第一方向D1布置。第一支柱101布置成阵列,且第二支柱102经布置以使得存在第二支柱102的阵列,在第一支柱101的阵列的两侧中的每一者上具有第二支柱102的一子阵列。在图1的实施例中,存在第一支柱101的阵列中的两行,且第二支柱102的每一阵列布置成环形链路结构。应注意,第一支柱101的两个行之间的间隙空间对应于衬底的RDL的一部分。
从图1中说明的仰视图来看,钝化层108暴露第一支柱101和第二支柱102。
图2说明根据本发明的实施例的图1中展示的半导体芯片10的区A1的放大视图。第一支柱101的第一构型具有沿着第一方向D1的第一宽度W1和沿着垂直于第一方向D1的第二方向D2的第二宽度W2。第一支柱101的第一构型的第一宽度W1大于第一支柱101的第一构型的第二宽度W2。在一或多个实施例中,第一支柱101的第一构型的第一宽度W1是第一支柱101的第一构型的第二宽度W2的至少约2倍、至少约3倍或约4倍到约9倍。换句话说,(W1)>(n)(W2),其中,在一些实施例中,4≤n≤9。在所展示的实施例中,在图2中,第二支柱102的第二构型的形状近似为圆形且具有直径W'。换句话说,第二支柱102的第二构型具有沿着第一方向D1和沿着第二方向D2的直径W'。更一般地说,第二构型具有沿着第一方向D1的第一宽度和沿着垂直于第一方向的第二方向D2的第二宽度,且第二构型的第一宽度大体上等于第二构型的第二宽度。在图2中展示的实施例中,第一支柱101的第一构型的第一宽度W1为第二支柱102的直径W'的约两倍,且第一支柱101的第一构型的第二宽度W2为第二支柱102的直径W'的约二分之一。因此,在此实施例中,第一支柱101的第一构型的第一宽度W1近似为第一支柱101的第一构型的第二宽度W2的四倍。在一些实施例中,第一支柱101的第一构型的面积大体上等于第二支柱102的第二构型的面积。
返回参看图1,应注意,邻近的第一支柱101之间的间距可类似于或可不同于邻近的第二支柱102之间的间距。应进一步注意,第一支柱101与邻近的第二支柱102之间的间距可类似于或可不同于邻近的第一支柱101之间的间距或邻近的第二支柱102之间的间距。
图3说明沿着图2的线3-3截取的横截面图。半导体芯片10包含芯片主体106、第一支柱101、第二支柱102、第一支柱衬垫103、第二支柱衬垫104和钝化层108。芯片主体106具有第一表面106a。第一支柱101和第二支柱102邻近于芯片主体106的第一表面106a而安置。在图3中所说明的实施例中,第一支柱衬垫103、第二支柱衬垫104和钝化层108安置在芯片主体106的第一表面106a上。钝化层108覆盖芯片主体106的第一表面106a,且部分覆盖第一支柱衬垫103和第二支柱衬垫104从而在第一支柱衬垫103和第二支柱衬垫104中的相应者上形成多个开口。第一支柱101和第二支柱102分别安置在对应于第一支柱衬垫103和第二支柱衬垫104的开口中。
第一支柱101中的每一者具有第二宽度W2,且第二支柱102中的每一者具有直径W'。在一或多个实施例中,第一支柱101的第二宽度W2小于第二支柱102的直径W'。举例来说,第一支柱101的第二宽度W2为(但不限于)第二支柱102的直径W'的约二分之一。在一或多个实施例中,对应于第一支柱101的第一支柱衬垫103的横截面尺寸小于对应于第二支柱102的第二支柱衬垫104的横截面尺寸。在其它实施例中,第一支柱衬垫103与第二支柱衬垫104的横截面尺寸可类似。
图4说明根据本发明的实施例的半导体装置4的俯视图。半导体装置4可为衬底或插入件,且包含衬底主体46、凸块衬垫40、接合垫44、一或多个芯片接合区域C1、C2,以及RDL47。凸块衬垫40、接合垫44、芯片接合区域C1、C2以及RDL 47安置在衬底主体46的表面46a上或邻近于表面46a而安置。
从俯视图来看,每一凸块衬垫40具有近似相同的形状,且每一凸块衬垫40是具有与凸块衬垫40中的其它者近似相同的直径的近似圆形。凸块衬垫40是为待安置在其上的凸块而提供,以连接到半导体芯片的相应支柱。如图4中所展示,凸块衬垫40布置成阵列,其中凸块衬垫40的一子阵列布置在芯片接合区域C1中,且凸块衬垫40的一子阵列布置在芯片接合区域C2中。半导体装置40的一侧上的一组凸块衬垫40的最外环圈周围的虚拟周界勾勒芯片接合区域C1,且半导体装置40的另一侧上的另一组凸块衬垫40的另一最外环圈周围的另一虚拟周界勾勒芯片接合区域C2。芯片接合区域C1、C2中的每一者的虚拟周界内的面积大体上等于对应半导体芯片的表面面积。
接合垫44是为待安置在其上的互连元件(例如,焊料球)而提供;举例来说,以连接到母板。接合垫44安置在衬底主体46的外围处且包围凸块衬垫40。接合垫44的尺寸大于凸块衬垫40的对应尺寸(俯视图中)。
RDL 47、凸块衬垫40和接合垫44可在相同工艺阶段期间(例如,在相同镀敷和蚀刻阶段中)形成。RDL 47、凸块衬垫40和接合垫44在相同层中,是经图案化电路层的部分,且由相同材料(例如,铜)制成。RDL 47将凸块衬垫40彼此连接,将接合垫44彼此连接,且/或将凸块衬垫40连接到接合垫44。
在所展示的实施例中,在图4中,RDL 47包含第一部分47A、第二部分47B、第三部分47C和第四部分47D。第一部分47A安置在芯片接合区域C1内且在凸块衬垫40的两个行之间。也就是说,第一部分47A安置在凸块衬垫40的两个行之间的间隙处。因此,RDL 47的第一部分47A延伸穿过芯片接合区域C1,且与第一方向D1平行。第一部分47A物理上连接到芯片接合区域C1外部的电元件。在一或多个实施例中,电元件为接合垫44、RDL 47的第二部分47B,或另一芯片接合区域(例如,C2)中的凸块衬垫40。应注意,电元件和RDL 47是相同层的一部分。
RDL 47的第二部分47B安置在芯片接合区域C1外部,且物理上连接第一部分47A和接合垫44,或第一部分47A和第三部分47C。第三部分47C安置在芯片接合区域C1内且物理上连接两个凸块衬垫40。第四部分47D物理上连接凸块衬垫40和接合垫44。在一或多个实施例中,第二部分47B、第三部分47C和第四部分47D的宽度大体上相同;且第一部分47A的宽度小于第二部分47B的宽度。RDL 47的包含第一部分47A和第二部分47B的片段大体上为直式的。第一部分47A和第二部分47B的直接连接路径穿过凸块衬垫40的两个行之间的间隙而不绕过芯片接合区域C1或远离芯片接合区域C1来布设。此外,因为第一部分47A的宽度小于第二部分47B的宽度,所以短路的风险为低,因为RDL 47的第一部分47A通常将不接触凸块衬垫40的两个行中的一或两者。因此,RDL 47的电路路径的长度(和其阻抗)可大大减小。换句话说,此实施例对于产生性能改进的电路是有益的。
图5说明根据本发明的实施例的图4中展示的半导体装置4的区A4的放大视图。连接两个凸块衬垫40的第三部分47C具有宽度L,第一部分47A具有宽度L1,且第二部分47B具有宽度L2。在一或多个实施例中,第三部分47C的宽度L大体上等于第二部分47B的宽度L2,且第一部分47A的宽度L1为第二部分47B的宽度L2的约二分之一。在其它实施例中,第一部分47A的宽度L1为第二部分47B的宽度L2的约1/3。其它实施例使宽度L、L1和L2相对于彼此变化。
图6说明沿着图5的线6-6截取的横截面图。如图6中所展示,半导体装置4包括衬底主体46、凸块衬垫40和RDL 47。凸块衬垫40和RDL 47邻近于衬底主体46的表面46a而安置。RDL 47包含安置于两个凸块衬垫40之间的第一部分47A。如图6中所展示,RDL 47的第一部分47A的宽度L1为凸块衬垫40中的每一者的直径W3的约三分之一。在一或多个实施例中,第一部分47A的宽度L1可为(但不限于)凸块衬垫40中的每一者的直径W3的约二分之一到约四分之一。此外,其间无第一部分47A的两个邻近凸块衬垫40之间的间距Wx大体上与其间具有第一部分47A的两个邻近凸块衬垫40之间的间距Wx相同。因此,RDL 47可布设在凸块衬垫40之间。
图7说明根据本发明的实施例的图6的半导体装置4的横截面图,其中保护层48安置在衬底主体46的表面46a上,且凸块43安置在相应凸块衬垫40上。保护层48覆盖衬底主体46的表面46a和RDL 47,且部分覆盖凸块衬垫40从而在凸块衬垫40的对应者上方形成多个开口。凸块43安置在对应于凸块衬垫40的开口中。凸块43为圆柱形。凸块43的大小和位置对应于凸块衬垫40的大小和位置。因此,因为两个邻近凸块衬垫40之间的间距Wx对于每对邻近凸块衬垫40是恒定的(大致相同),所以当凸块43定位在所有凸块衬垫40上时每对邻近凸块43之间的间距也可为恒定的(大致相同)。应注意,图4中,存在不含凸块衬垫40的区域;术语相对于凸块衬垫40对或凸块43对“邻近”并不包含跨越此空区域的对。
图8说明借助于比较来自俯视图的电路设计。图8的电路设计包含芯片接合区域C3、凸块衬垫40a和RDL 49的部分49A。图8的电路设计并不允许在凸块衬垫40a之间布设RDL。芯片接合区域C3的尺寸与图4的芯片接合区域C1或C2的尺寸大致相同。凸块衬垫40a安置在芯片接合区域C3内。RDL 49的部分49A具有恒定的宽度,且图8中的RDL 49的部分49A的宽度与图4中的RDL 47的第二部分47B的宽度相同。图8中的RDL 49的部分49A安置在芯片接合C3外部且布设在芯片接合区域C3周围。
出于比较的目的,在图8的电路设计的实例中,芯片接合区域C3的宽度约为7毫米(mm),部分49A的宽度约为20微米(μm),部分49A的厚度约为3μm,从点P3到点P4的部分49A的长度约为20.7mm,且从点P3到点P4的部分49A的电阻约为5.8欧姆。
相比而言,针对图4的实施例的实例,芯片接合区域C1的宽度约为7mm(类似于图8的芯片接合区域C3的宽度)、第二部分47B的宽度L2约为20μm(类似于图8的部分49A的宽度),且包含第一部分47A和第二部分47B的片段的厚度约为3μm(类似于图8的部分49A的厚度)。然而,第一部分47A的宽度L1约为10μm,从点P1到点P2的片段的长度约为11.2mm,且从点P1到点P2的片段的电阻约为5.26欧姆。相比于图8,将理解,根据图4的实施例的配置可通过减小RDL中的路径长度来降低两个点之间的电阻。
图9说明根据本发明的实施例的半导体装置5的俯视图。图9的半导体装置5类似于图4中说明的半导体装置4,差别在于:在图9中,凸块衬垫40包含第一凸块衬垫401和第二凸块衬垫402,且RDL 47的第一部分47A的宽度大体上等于RDL 47的第二部分47B的宽度。
第一凸块衬垫401具有来自俯视图的第一构型,且第二凸块衬垫402具有来自俯视图的第二构型,且第一构型的形状不同于第二构型的形状(相对于图10提供一实例)。第一和第二凸块衬垫401和402是针对待安置在其上的凸块提供,以连接到半导体芯片的支柱。如图9中所展示,凸块衬垫40布置成阵列,凸块衬垫40的一子阵列布置在芯片接合区域C1中,且凸块衬垫40的一子阵列布置在芯片接合区域C2中。半导体装置40的一侧上的一组凸块衬垫40的最外环圈周围的虚拟周界勾勒芯片接合区域C1,且半导体装置40的另一侧上的另一组凸块衬垫40的另一最外环圈周围的另一虚拟周界勾勒芯片接合区域C2。芯片接合区域C1、C2中的每一者的虚拟周界内的面积大体上等于对应半导体芯片的表面面积。
接合垫44是为待安置在其上的互连元件(例如,焊料球)而提供;举例来说,以连接到母板。接合垫44安置在衬底主体46的外围处且包围凸块衬垫40。接合垫44的尺寸大于凸块衬垫40的对应尺寸(俯视图中)。
RDL 47、凸块衬垫40和接合垫44可在相同工艺阶段期间(例如,在相同镀敷和蚀刻阶段中)形成。RDL 47、凸块衬垫40和接合垫44在相同层中,是经图案化电路层的部分,且由相同材料(例如,铜)制成。RDL 47将凸块衬垫40彼此连接,将接合垫44彼此连接,且/或将凸块衬垫40连接到接合垫44。
在所展示的实施例中,在图9中,RDL 47包含第一部分47A、第二部分47B、第三部分47C和第四部分47D。第一部分47A安置在芯片接合区域C1内且在第一凸块衬垫401的两个行之间。也就是说,第一部分47A安置在第一凸块衬垫401的两个行之间的间隙处。因此,RDL47的第一部分47A延伸穿过芯片接合区域C1,且与第一方向D1平行。第一部分47A物理上连接到芯片接合区域C1外部的电元件。在一或多个实施例中,电元件为接合垫44、RDL 47的第二部分47B,或另一芯片接合区域(例如,C2)中的第一凸块衬垫401或第二凸块衬垫402。应注意,电元件和RDL 47是相同层的一部分。
RDL 47的第二部分47B安置在芯片接合区域C1外部,且物理上连接第一部分47A和接合垫44,或第一部分47A和第三部分47C。第三部分47C安置在芯片接合区域C1内且物理上连接第一凸块衬垫401和第二凸块衬垫402。第四部分47D物理上连接第二凸块衬垫402和接合垫44。在一或多个实施例中,第一部分47A、第二部分47B、第三部分47C和第四部分47D的宽度大体上相同。RDL 47的包含第一部分47A和第二部分47B的片段大体上为直式的。第一部分47A和第二部分47B的直接连接路径穿过第一凸块衬垫401的两个行之间的间隙而不绕过芯片接合区域C1或远离芯片接合区域C1来布设。此外,因为方向D2上的第一凸块衬垫401的宽度小于方向D2上的凸块衬垫402的宽度,所以短路的风险为低,因为RDL 47的第一部分47A通常将不接触第一凸块衬垫401的两个行中的一或两者。因此,RDL 47的电路路径的长度(和其阻抗)可大大减小。换句话说,此实施例对于产生性能改进的电路是有益的。
图10说明根据本发明的实施例的图9中展示的半导体装置5的区A9的放大视图。在此实施例中,第一凸块衬垫401的第一构型的形状大体上为椭圆形,且第二凸块衬垫402的第二构型的形状大体上为圆形。第一凸块衬垫401的第一构型具有沿着第一方向D1的第一宽度W4和沿着垂直于第一方向D1的第二方向D2的第二宽度W5。第一凸块衬垫401的第一构型的第一宽度W4大于第一凸块衬垫401构型的第一构型的第二宽度W5。在一或多个实施例中,第一凸块衬垫401的第一构型的第一宽度W4为第一凸块衬垫401的第一构型的第二宽度W5的至少约2倍、至少约3倍、或约4到约9倍。换句话说,(W4)>(n)(W5),其中在一些实施例中,4≤n≤9。
在图10中所说明的实施例中,第二凸块衬垫402的第二构型的形状为具有直径W的近似圆形。更一般地说,第二构型具有沿着第一方向D1的第一宽度和沿着垂直于第一方向的第二方向D2的第二宽度,且第二构型的第一宽度大体上等于第二构型的第二宽度。如图10中所展示,第一凸块衬垫401的第一构型的第一宽度W4为第二凸块衬垫402的第二构型的直径W的约两倍,且凸块衬垫401的第一构型的第二宽度W5为第二凸块衬垫402的第二构型的直径W的约二分之一。在此实施例中,第一凸块衬垫401的第一构型的第一宽度W4为第一凸块衬垫401的第一构型的第二宽度W5的约四倍。对于其它实施例预期其它相对尺寸。在一或多个实施例中,第一凸块衬垫401的第一构型的面积大体上等于第二凸块衬垫402的第二构型的面积。在一或多个实施例中,邻近的第一凸块衬垫401之间的间距为恒定的(每对邻近第一凸块衬垫401具有近似相同间距),且邻近的第二凸块衬垫402之间的间距为恒定的(每对邻近第二凸块衬垫402具有近似相同间距)。在一或多个实施例中,邻近的第一凸块衬垫401与第二凸块衬垫402之间的间距为恒定的(每对第一凸块衬垫401邻近于第二凸块衬垫402具有近似相同间距)。应注意,邻近的第一凸块衬垫401之间的间距、邻近的第二凸块衬垫402之间的间距以及邻近的第一凸块衬垫401与第二凸块衬垫402之间的间距可大致相同,或可不同。
图11说明沿着图10的线11-11截取的横截面图。如图11中所展示,半导体装置5包含衬底主体46、第一凸块衬垫401、第二凸块衬垫402和RDL 47。第一凸块衬垫401、第二凸块衬垫402和RDL 47邻近于衬底主体46的表面46a而安置。RDL包含安置于两个第一凸块衬垫401之间的第一部分47A。此外,其间无第一部分47A的两个邻近凸块衬垫40(凸块衬垫401或402)之间的间距Wx大体上与其间有第一部分47A的两个邻近凸块衬垫40(凸块衬垫401)之间的间距Wx相同。因此,RDL可布设在凸块衬垫40之间。
图12说明根据本发明的实施例的图11的半导体装置5的横截面图,其中保护层48安置在衬底主体46的表面46a上,且凸块43安置在相应凸块衬垫40上。凸块43包含安置在相应凸块衬垫401上的第一凸块431和安置在相应凸块衬垫402上的第二凸块432。保护层48覆盖衬底主体46的表面46a和RDL 47,且部分覆盖凸块衬垫40(第一凸块衬垫401和第二凸块衬垫402)从而在凸块衬垫40的对应者上方形成多个开口。凸块43安置在对应于凸块衬垫40的开口中。第一凸块431和第二凸块432分别安置在对应于第一凸块衬垫401和第二凸块衬垫402的开口中。凸块43为圆柱形。凸块43的大小和位置对应于凸块衬垫40的大小和位置。因此,如果两个邻近凸块衬垫40之间的间距Wx对于每对邻近凸块衬垫40为恒定的(大致相同),那么当凸块43定位在所有凸块衬垫40上时每对邻近凸块43之间的间距也可为恒定的(大致相同)。应注意,图9中,存在不含凸块衬垫40的区域;术语相对于凸块衬垫40对或凸块43对“邻近”并不包含跨越此空区域的对。
如图9-12中所展示,RDL 47的第一部分47A延伸穿过第一凸块衬垫401(如图9中所展示)的两个行之间的间隙。穿过两个第一凸块衬垫401之间的间隙空间的此直接连接路径避免绕过芯片接合区域C1(如图9中所展示)或远离芯片接合区域C1而布设。此外,因为方向D2中第一凸块衬垫401的宽度小于方向D2中第二凸块衬垫402的宽度,所以短路的风险为低,因为RDL 47的第一部分47A通常将不接触凸块衬垫401的两个行中的一或两者。因此,RDL 47的电路路径的长度(和其阻抗)可大大减小。换句话说,此实施例对于产生性能改进的电路是有益的。
图13说明根据本发明的实施例的半导体装置130的横截面图。半导体装置130可为封装,且包含半导体芯片10(如图3中所展示)和半导体装置5(如图12中所展示)。图13中,半导体芯片10的第一支柱101物理上连接到半导体装置5的第一凸块431,且半导体芯片10的第二支柱102物理上连接到半导体装置5的第二凸块432。在图13中所说明的实施例中,第一支柱101(参看图2)的第二宽度W2和第一凸块431的对应宽度大体上相同,且第二支柱102(参看图2)的直径W'和第二凸块432的对应宽度大体上相同。在图13中可以看出,RDL 47的第一部分47A布设在半导体芯片10下方。
图14说明根据本发明的实施例的半导体装置140的横截面图。图14的半导体装置140类似于图13中说明的半导体装置130,且半导体装置140进一步包括母板200和至少一个互连元件210。互连元件210连接半导体装置5(图9)的母板200和相应接合垫44。母板200可为(例如)印刷电路板(PCB),且互连元件210可为焊球。
图15说明根据本发明的实施例的半导体装置5a的俯视图。图15和图9中的类似编号的特征指代类似组件。半导体装置5a为衬底,且包含第一凸块衬垫401、第二凸块衬垫402、RDL 47的第四部分47D和接合垫44。第一凸块衬垫401和第二凸块衬垫402布置在两个子阵列中以界定两个芯片接合区域C3和C4。在图15中所说明的实施例中,第一凸块衬垫401沿着第二方向D2布置,沿着方向D2的第一凸块衬垫401的宽度大于沿着方向D1的第一凸块衬垫401的宽度,且RDL 47的第四部分47D与第二方向D2平行。
RDL 47的第四部分47D的一端连接到芯片接合区域C3、C4内的第二凸块衬垫402,且RDL 47的第四部分47D的另一端连接到芯片接合区域C3、C4外部的电元件。在一或多个实施例中,电元件为接合垫44、RDL 47的另一部分或另一芯片接合区域中(例如,芯片接合区域C3、C4中的另一者中)的凸块衬垫40。第一凸块衬垫401的布置提供第一凸块衬垫401之间的更宽间隙,使得RDL 47的第四部分47D可直接穿过两个邻近的第一凸块衬垫401之间的间隙。因此,RDL 47的第四部分47D可布设在半导体芯片下方。
图16A-16D说明根据本发明的实施例的制造方法。在此实施例中,所述制造方法用于制造如图12中所展示的半导体装置5。然而,所述制造方法还可用于制造如图1到图3中所展示的半导体芯片10。参看图16A,提供如图11中所展示的半导体装置5。半导体装置5包含安置在衬底主体46的表面46a上的保护层48。保护层48覆盖衬底主体46的表面46a和RDL47,且部分覆盖第一凸块衬垫401和第二凸块衬垫402从而形成暴露第一凸块衬垫401和第二凸块衬垫402的对应者的开口。光致抗蚀剂层50形成在保护层以及暴露的第一凸块衬垫401和第二凸块衬垫402上方。在一些实施例中,省略保护层48,且光致抗蚀剂层50形成在表面46a上方且形成在第一凸块衬垫401和第二凸块衬垫402上方。
参看图16B,第一开口501和第二开口502形成于光致抗蚀剂层50中。第一开口501和第二开口502延伸穿过光致抗蚀剂层50以分别暴露第一凸块衬垫401和第二凸块衬垫402。也就是说,第一开口501和第二开口502的位置对应于相应的第一凸块衬垫401和第二凸块衬垫402。
参看图16C,展示图16B的光致抗蚀剂层50的部分区域的俯视图。图16C中,第一开口501中的每一者界定第一构型,且第二开口502中的每一者界定第二构型。第一开口501的第一构型具有沿着第一方向D1的第一宽度W6和沿着垂直于第一方向D1的第二方向D2的第二宽度W7。第一开口501的第一构型的第一宽度W6大于第一开口501的第一构型的第二宽度W7。在一或多个实施例中,第一开口501的第一构型的第一宽度W6是第一开口501的第一构型的第二宽度W7的至少约2倍、至少约3倍或约4倍到约9倍。换句话说,(W6)>(n)(W7),其中在一些实施例中,4<n<9。在图16C中所说明的实施例中,第二开口502的第二构型的形状为圆形且具有直径W"。参看图16C和图10,第一开口501的第一构型的第一宽度W6可大体上等于第一凸块衬垫401的第一构型的第一宽度W4,第一开口501的第一构型的第二宽度W7可大体上等于第一凸块衬垫401的第一构型的第二宽度W5,且第二开口502的第二构型的直径W"可大体上等于第二凸块衬垫402的第二构型的直径W。
在一或多个实施例中,第一开口501的第一构型的第一宽度W6为第二开口502的第二构型的直径W"的约两倍,且第一开口501的第一构型的第二宽度W7为第二开口502的第二构型的直径W"的约二分之一。因此,在此实施例中,第一开口501的第一构型的第一宽度W6为第一开口501的第一构型的第二宽度W7的约四倍。对于其它实施例预期有不同的相对尺寸。如图16B中所展示,第一开口501和第二开口502的高度大体上相同。在一或多个实施例中,第一开口501的第一构型的面积大体上等于第二开口502的第二构型的面积;因此,第一开口501和第二开口502的体积大体上相同。
参看图16D,第一开口501和第二开口502在相同工艺阶段中由金属材料(例如,铜)填充从而在第一开口501中形成第一凸块431(参看图12)且在第二开口502中形成第二凸块432(参看图12),或在第一开口501中形成第一支柱101(参看图3)且在第二开口502中形成第二支柱102(参看图3)。在其中第一开口501和第二开口502的体积大体上相同的实施例中,第一开口501和第二开口502可同时填充(例如,使用一个电镀阶段),这简化了制造工艺。相比之下,如果凸块具有不同横截面面积(例如,使用第一电镀填充光致抗蚀剂层中具有小直径的开口,且接着第二电镀填充光致抗蚀剂层的具有较大直径的开口),那么可需要多个电镀阶段。
在填充第一开口501和第二开口502之后,移除光致抗蚀剂层50以获得图12中展示的半导体装置5。
除非另外规定,否则例如“上面”、“下面”、“向上”、“左侧”、“右侧”、“向下”、“顶部”、“底部”、“垂直”、“水平”、“侧部”、“较高”、“较低”、“上部”、“上方”、“下方”等空间描述是相对于图式中所展示的定向而指示。应理解,本文中所使用的空间描述仅是出于说明的目的,且本文中所描述的结构的实际实施方案可以任何定向或方式在空间上布置,其限制条件为本发明的实施例的优点不因此布置而有偏差。
如本文中所使用,术语“大致”、“大体上”、“大体”及“约”用以描述及考虑小变化。当与事件或情形接合使用时,所述术语可指代其中事件或情形精确发生的例子以及其中事件或情形极近似地发生的例子。举例来说,当结合数值使用时,术语可指代小于或等于所述数值的±10%的变化范围,例如小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%、或小于或等于±0.05%。对于另一实例,如果两个数值之间的差值小于或等于所述值的平均值的±10%(例如小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%、或小于或等于±0.05%),那么可认为所述两个数值"大体上"相同。
另外,有时在本文中以范围格式呈现量、比率和其它数值。应理解,此类范围格式是用于便利和简洁起见,且应灵活地理解,不仅包含明确地指定为范围限制的数值,而且包含涵盖于所述范围内的所有个别数值或子范围,如同明确地指定每一数值和子范围一般。
虽然已参考本发明的特定实施例描述和说明本发明,但这些描述和说明并不限制本发明。所属领域的技术人员应理解,在不脱离如由所附权利要求书界定的本发明的真实精神和范围的情况下,可作出各种改变且可取代等效物。所述说明可能未必按比例绘制。归因于制造工艺和容差,本发明中的艺术再现与实际设备之间可存在区别。可存在并未特定说明的本发明的其它实施例。应将本说明书和图式视为说明性的而非限制性的。可作出修改,以使特定情况、材料、物质组成、方法或工艺适应于本发明的目标、精神和范围。所有此些修改都打算属于在此所附权利要求书的范围内。虽然本文揭示的方法已参考按特定次序执行的特定操作描述,但应理解,可在不脱离本发明的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此,除非本文中特别指示,否则操作的次序和分组并非本发明的限制。
Claims (10)
1.一种半导体芯片,其包括:
芯片主体;
至少一个第一支柱,其邻近于所述芯片主体的表面而安置,其中所述第一支柱具有来自仰视图的第一构型,所述第一构型具有沿着第一方向的第一宽度和沿着垂直于所述第一方向的第二方向的第二宽度,且所述第一构型的所述第一宽度大于所述第一构型的所述第二宽度;以及
至少一个第二支柱,其邻近于所述芯片主体的所述表面而安置,其中所述第二支柱具有来自仰视图的第二构型,且所述第一构型的形状不同于所述第二构型的形状。
2.根据权利要求1所述的半导体芯片,其中所述至少一个第一支柱为沿着所述第一方向布置的多个第一支柱。
3.根据权利要求1所述的半导体芯片,其中所述至少一个第二支柱为布置成阵列的多个第二支柱。
4.根据权利要求1所述的半导体芯片,其中所述第一构型的面积大体上等于所述第二构型的面积。
5.根据权利要求1所述的半导体芯片,其中所述第二构型具有沿着所述第一方向的第一宽度和沿着垂直于所述第一方向的所述第二方向的第二宽度,且所述第二构型的所述第一宽度大体上等于所述第二构型的所述第二宽度。
6.根据权利要求5所述的半导体芯片,其中所述第一构型的所述第一宽度为所述第二构型的所述第一宽度的约两倍,且所述第一构型的所述第二宽度为所述第二构型的所述第二宽度的约二分之一。
7.一种半导体装置,其包括:
衬底主体;
多个第一凸块衬垫,其邻近于所述衬底主体的表面而安置,所述第一凸块衬垫中的每一者具有来自俯视图的第一构型,所述第一构型具有沿着第一方向的第一宽度和沿着垂直于所述第一方向的第二方向的第二宽度,且所述第一构型的所述第一宽度大于所述第一构型的所述第二宽度;以及
再分布层,其邻近于所述衬底主体的所述表面而安置,其中所述再分布层包含安置于两个第一凸块衬垫之间的第一部分。
8.根据权利要求7所述的半导体装置,其进一步包括所述衬底主体上的芯片接合区域和所述芯片接合区域外部的电元件,所述再分布层的所述第一部分安置在所述芯片接合区域内,且所述再分布层的所述第一部分物理上连接到所述芯片接合区域外部的所述电元件。
9.根据权利要求7所述的半导体装置,其中所述第一凸块衬垫沿着所述第一方向布置,且所述再分布层的所述第一部分与所述第一方向平行。
10.根据权利要求7所述的半导体装置,其进一步包括多个第二凸块衬垫,所述第二凸块衬垫中的每一者具有来自俯视图的第二构型,且所述第二构型的形状不同于所述第一构型的形状,且所述第一构型的面积大体上等于所述第二构型的面积。
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