CN107527889B - 半导体装置封装 - Google Patents

半导体装置封装 Download PDF

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Publication number
CN107527889B
CN107527889B CN201710451949.7A CN201710451949A CN107527889B CN 107527889 B CN107527889 B CN 107527889B CN 201710451949 A CN201710451949 A CN 201710451949A CN 107527889 B CN107527889 B CN 107527889B
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layer
bare chip
conductive
chamber
semiconductor bare
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CN107527889A (zh
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凯·史提芬·艾斯格
邱基综
李彗华
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

一种半导体装置封装包含第一导电基底、第一半导体裸片、电介质层、第一经图案化导电层以及第二经图案化导电层。所述第一导电基底界定第一腔。所述第一半导体裸片在所述第一腔的底部表面上。所述电介质层覆盖所述第一半导体裸片、所述第一导电基底的第一表面和第二表面且填充所述第一腔。所述第一经图案化导电层在所述电介质层的第一表面上。所述第二经图案化导电层在所述电介质层的第二表面上。

Description

半导体装置封装
相关申请案的交叉参考
本申请案主张2016年6月15日申请的第62/350,622号美国临时申请案的权益和优先权，所述美国临时申请案的内容以全文引用的方式并入本文中。
技术领域
本发明涉及一种半导体装置封装及其制造方法。确切地说，本发明涉及包含改进的导电基底的半导体装置封装结构及其制造方法。
背景技术
在其中一或多个半导体装置安置于引线框的裸片脚座中的一些嵌入式半导体装置封装中，将大量组件和/或输入/输出(I/O)(例如，导电线/通孔/迹线)集成到所述嵌入式半导体装置封装中且同时防止或缓解寄生电容可为挑战性的。
发明内容
在根据本发明的第一方面的一或多个实施例中，一种半导体装置封装包含第一导电基底、第一半导体裸片、电介质层、第一经图案化导电层、第二经图案化导电层、多个第一互连结构以及多个第二互连结构。所述第一导电基底具有第一表面以及与所述第一表面相对的第二表面。第一腔由所述第一导电基底界定且形成于所述第一导电基底的第一表面中。所述第一腔具有底部表面。所述第一半导体裸片安置于所述第一腔的底部表面上。所述电介质层安置于所述第一半导体裸片、所述第一导电基底的第一表面和第二表面上且填充所述第一腔。所述电介质层具有第一表面和与所述第一表面相对的第二表面。所述第一经图案化导电层安置于所述电介质层的第一表面上。所述第二经图案化导电层安置于所述电介质层的第二表面上。所述多个第一互连结构安置于所述电介质层中且电连接到所述第一半导体裸片和所述第一经图案化导电层。所述多个第二互连结构安置于所述电介质层中且电连接到所述第一导电基底的所述第二表面和所述第二经图案化导电层。
在根据本发明的另一方面的一或多个实施例中，一种半导体装置封装包含导电基底、第一半导体裸片、第二半导体裸片、电介质层、第一经图案化导电层、多个第一互连结构以及多个第二互连结构。所述导电基底具有第一表面以及与所述第一表面相对的第二表面。所述导电基底界定形成于所述第一导电基底的第一表面中的腔。所述腔具有底部表面。所述第一半导体裸片安置于所述腔的底部表面上。所述第二半导体裸片安置于所述腔的底部表面上。所述电介质层安置于所述导电基底的第一表面、所述第一半导体裸片和所述第二半导体裸片上且填充所述腔。所述电介质层具有第一表面。所述第一经图案化导电层和第二经图案化导电层安置于所述电介质层的第一表面上。所述多个第一互连结构安置于所述电介质层中且电连接到所述第一半导体裸片和所述第一经图案化导电层。所述多个第二互连结构安置于所述电介质层中且电连接到所述第二半导体裸片和所述第二经图案化导电层。
在根据本发明的另一方面的一或多个实施例中，一种半导体装置封装包含导电基底、第一半导体裸片、第一电介质层、第一经图案化导电层、第二半导体裸片、第二电介质层以及第二经图案化导电层。所述导电基底具有第一表面以及与所述第一表面相对的第二表面。所述导电基底界定形成于所述导电基底的第一表面中的腔。所述腔具有底部表面。所述第一半导体裸片安置于所述腔的底部表面上。所述第一电介质层安置于所述导电基底的第一表面和所述第一半导体裸片上。所述第一电介质层具有第一表面。所述第一经图案化导电层安置于所述第一电介质层上且电连接到所述第一半导体裸片。所述第二半导体裸片安置于所述第一经图案化导电层上。所述第二电介质层安置于所述第一经图案化导电层、所述第一电介质层的所述第一表面以及所述第二半导体裸片上。所述第二经图案化导电层安置于所述第二电介质层上且电连接到所述第二半导体裸片。
附图说明
图1是根据本发明的第一方面的半导体装置封装的一些实施例的横截面视图。
图2A、图2B、图2C、图2D、图2E、图2F、图2G和图2H说明制造图1中描绘的半导体装置封装的方法的一些实施例。
图3A、图3B、图3C、图3D、图3E、图3F、图3G、图3H、图3I和图3J说明制造图1中描绘的半导体装置封装的方法的一些实施例。
图4A是根据本发明的第二方面的半导体装置封装的一些实施例的横截面视图。
图4B说明图4A中描绘的半导体装置封装的一些实施例的俯视图。
图5A、图5B、图5C、图5D、图5E、图5F、图5G、图5H和图5I说明制造图4A中描绘的半导体装置封装的方法的一些实施例。
图6A是根据本发明的第三方面的半导体装置封装的一些实施例的横截面视图。
图6B说明图6A中描绘的半导体装置封装的一些实施例的俯视图。
图7A、图7B、图7C、图7D、图7E、图7F、图7G、图7H和图7I说明制造图6A中描绘的半导体装置封装的方法的一些实施例。
图8是根据本发明的第四方面的半导体装置封装的一些实施例的横截面视图。
图9A、图9B、图9C、图9D、图9E、图9F、图9G、图9H、图9I、图9J、图9K和图9L说明制造图8的半导体装置封装的方法的一些实施例。
图10A、图10B、图10C、图10D、图10E、图10F、图10G、图10H、图10I、图10J、图10K、图10L和图10M说明根据第五方面的制造半导体装置封装的方法的一些实施例。
图11A、图11B、图11C、图11D、图11E、图11F、图11G、图11H和图11I说明根据第六实施例的制造半导体装置封装的方法的一些实施例。
图12A、图12B、图12C、图12D、图12E、图12F、图12G、图12H和图12I说明根据第七方面的制造半导体装置封装的方法的一些实施例。
贯穿图式和具体实施方式使用共同参考数字以指示相同或类似元件。本发明的实施例将从结合附图进行的以下详细描述更显而易见。
具体实施方式
本发明中所描述的是用于提供具有减小的封装大小的装置的技术的实施例。举例来说，本发明描述包含改进的导电基底结构的半导体装置封装结构的实施例，所述改进的导电基底结构用于当一或多个半导体装置安置于引线框的裸片脚座中时缓解或消除寄生电容。
除非另外规定，否则例如“上面”、“下面”、“向上”、“左侧”、“右侧”、“向下”、“顶部”、“底部”、“垂直”、“水平”、“侧部”、“高于”、“下部”、“上部”、“上方”、“下方”等空间描述是相对于图式中所示的取向指示的。应理解，本文中所使用的空间描述仅是出于说明的目的，且本文中所描述的结构的实际实施方案可以任何定向或方式在空间上布置，其限制条件为本发明的实施例的优点是不因此布置而有偏差。
图1是根据本发明的第一方面的半导体装置封装1的一些实施例的横截面视图。半导体装置封装1包含衬底10、半导体裸片20、22、24和26、导电粘合剂层48、在至少一些实施例中可充当支撑层的保护层70(例如，电介质层)、绝缘层50和52、经图案化导电层80和82、互连结构801和821、连接元件90，以及导电连接件75。
衬底10包含导电基底101和导电基底102。在一些实施例中，导电基底101和102可构成引线框或可为引线框的部分。导电基底101具有第一表面101u以及与第一表面101u相对的表面101b。导电基底102具有第一表面102u以及与第一表面102u相对的表面102b。导电基底101和102的材料可包含(例如)铜(Cu)或另一金属或金属合金或其它导电材料。在一些实施例中，导电基底101和102可构成裸片脚座或可为裸片脚座的部分。包含导电基底101和导电基底102的至少部分地大体上对称的结构的实施方案可实现半导体装置封装1的减少翘曲。另外，大量组件可集成到具有大体上对称结构的引线框中。在一些实施例中，通过在连接元件90的相对侧上安置导电基底101和导电基底102，具有距连接元件90大体上相同最小距离的每一导电基底可实现半导体装置封装1的减少翘曲以及大量组件到引线框中的集成。
在一些实施例中，导电基底101和102界定一或多个弯曲结构60(例如，经平滑或圆化的拐角)，其可帮助在制造操作期间减少或最小化在相应弯曲结构60处的应力(例如，相对于在保护层70的形成中涉及的应力减少的应力)。弯曲结构60可进一步帮助跨越导电基底101和102再分布应力，跨越导电基底101和102更均匀地分摊应力，或将应力点从导电基底101和102的一个部分转移到导电基底101和102的另一部分。不同弯曲结构60可具有不同曲率半径和/或可相对于导电基底101的表面101b或导电基底102的第一表面102u形成不同的锥形角度。
导电基底101在导电基底101的第一表面101u中界定腔30，且导电基底102在导电基底102的第一表面102u中界定腔32。腔30具有底部表面301且腔32具有上部表面321。半导体裸片20和半导体裸片24安置于腔30的底部表面301上。半导体裸片22安置于腔32的上部表面321上。
腔30和32分别形成于导电基底101和导电基底102中且可接纳半导体裸片20、22和24，这可帮助减小封装厚度。通过包含腔30和32的设计可实现紧凑的三维(3-D)嵌入式封装的一些实施例。
在一些实施例中，半导体裸片20具有第一表面201以及与第一表面201相对的第二表面202。半导体裸片20的表面202通过导电粘合剂层48结合到腔30的底部表面301。导电粘合剂层48可例如为导电凝胶或环氧树脂膜(与导电材料混合的环氧树脂)或其它导电材料。在一些实施例中，半导体裸片24具有第一表面241以及与第一表面241相对的第二表面242，且半导体裸片22具有第一表面221以及与第一表面221相对的第二表面222。半导体裸片24也通过导电粘合剂层48结合到腔30的底部表面301。半导体裸片26具有第一表面261以及与第一表面261相对的第二表面262。半导体裸片26的表面262通过导电粘合剂层48结合到导电基底102的表面102b。
半导体裸片24通过导电粘合剂层48结合到腔30的底部表面301，且半导体裸片22通过导电粘合剂层48结合到腔32的上部表面321。半导体裸片20和22可例如为电力裸片，且半导体裸片24可例如为控制裸片。裸片26安置于导电基底102的表面102b上。裸片26通过互连结构801电连接到经图案化导电层80。
导电粘合剂层48安置于半导体裸片20的表面202与腔30的底部表面301之间。在一些实施例中，导电粘合剂层48覆盖腔30的底部表面301的一部分，和/或覆盖大体上整个底部表面301。在一些实施例中，导电粘合剂层48可接触半导体裸片20的一或多个侧壁的一部分。导电粘合剂层48将半导体裸片20附接到导电基底101。半导体裸片24的布置类似于半导体裸片20(例如，半导体裸片24类似地经由导电粘合剂附接到底部表面301)。
对于半导体裸片22，导电粘合剂层48安置于半导体裸片22的表面222与腔32的上部表面321之间。在一些实施例中，导电粘合剂层48覆盖腔32的上部表面321的一部分和/或覆盖大体上整个上部表面321。在一些实施例中，导电粘合剂层48可接触半导体裸片22的一或多个侧壁的一部分。导电粘合剂层48将半导体裸片22附接到导电基底102。
保护层70安置于导电基底101和102上且安置于半导体裸片20、22和24上。保护层70具有第一表面701以及与第一表面701相对的第二表面702。保护层70囊封导电基底101的第一表面101u和第二表面101b，且囊封半导体裸片20和24的至少一部分。保护层70还囊封和/或覆盖导电基底102的第一表面102u和表面102b的至少一部分且囊封半导体裸片22的至少一部分。在一些实施例中，保护层70的材料可包含聚丙烯树脂；然而，可另外或替代地使用其它合适的材料。
互连结构801分别将相应经图案化导电层80电连接到半导体裸片20的第一表面201和半导体裸片24的第一表面241。互连结构821将经图案化导电层82电连接到半导体裸片22的第一表面221。互连结构801电连接到导电基底101的第一表面101u，且互连结构821电连接到导电基底102的第一表面102u。导电基底102的表面102b通过所述多个互连结构801电连接到经图案化导电层80。半导体裸片22通过所述多个互连结构821电连接到导电层82。在一些实施例中，裸片20通过导电基底101和互连结构821电连接到裸片22。
在一些实施例中，互连结构801和821是通过保护层70形成的导电通孔。互连结构801和821以及经图案化导电层80和82的材料可包含(例如)铜或另一金属或金属合金或其它导电材料。
绝缘层50安置于保护层70的第一表面701的至少一部分上和互连结构801上方。绝缘层52安置于保护层70的第二表面702的至少一部分上和互连结构821上方。在一些实施例中，绝缘层50和52可包含焊料掩模。绝缘层50和52中的一者或两者的材料可包含聚丙烯树脂和/或其它绝缘材料。导电连接件75(例如，焊料球)安置于经图案化导电层80上。
导电基底101界定弯曲结构60且导电基底102界定弯曲结构60。弯曲结构60可包含导电基底的圆化拐角。弯曲结构60可包含由导电基底中的一或多者界定的凹部(例如，形成于导电基底中的一或多者的外部侧壁或其它侧壁中的凹部)，且所述凹部可包含圆化拐角。所述凹部可由导电基底的侧壁的底部部分界定(例如，可延伸到所述侧壁和表面101b或表面102u连接的拐角)。在另一实施例中，导电基底101和导电基底102的弯曲结构60可填充有保护层70。弯曲结构可帮助减少或防止在个别半导体装置封装1从较大封装(例如，从面板)的分离(例如，单粒化)期间对保护层70的损坏。
连接元件90安置在保护层70中。连接元件90电连接到经图案化导电层80和经图案化导电层82中的至少一者(例如，通过互连结构801或821中的一者)。连接元件90的材料可包含(例如)铜或另一金属或金属合金或其它导电材料。在一些实施例中，连接元件90是填充有导电材料的金属组件(例如，金属框架)或穿孔。
半导体装置封装1中的一个实例电流路径(图1中由箭头指示)从经图案化导电层80通过导电基底101流动到经图案化导电层82。通过提供此路径，可实施经减少高度的一或多个通孔(例如与从顶部经图案化导电层80延伸到底部经图案化导电层82的通孔相比)。制造此相对短通孔可较容易。导电/电流路径的此缩减也可帮助避免信号衰减或干扰。
图2A到2H说明制造图1中描绘的半导体装置封装1的方法的一些实施例。参考图2A，提供导电基底101和102。导电基底101具有第一表面101u以及与第一表面101u相对的表面101b。导电基底102具有第一表面102u以及与第一表面102u相对的表面102b。导电基底101和102的材料包含(例如)铜或另一金属或金属合金或其它导电材料。例如通过钻孔(例如，通过在初始导电基底中钻至少两个孔，进而形成单独导电基底101和102以及连接元件90)而形成连接元件90。第一表面101u界定腔30(例如，第一表面101u具备腔30，或腔30形成于第一表面101u中)。第一表面102u界定腔32(例如，第一表面102u具备腔32，或腔32形成于第一表面102u中)。腔30具有底部表面301。腔32具有上部表面321。在一些实施例中，导电基底101具备腔30且未经蚀刻以形成腔30(例如，在导电基底101的上述提供之后未经蚀刻)。即，未通过蚀刻技术移除导电基底101的第一表面101u。可提供相对稳健或强结构的导电基底101的未经蚀刻结构相对较容易处置以促进后续电测量/测试。导电基底101界定一或多个弯曲结构60。导电基底101的弯曲结构60经平滑且可帮助再分布应力以避免在层压期间对保护层70的损坏。导电基底102的结构可以相似方式形成。
参考图2B，导电粘合剂层48安置于腔30的底部表面301上和腔32的上部表面321上。导电粘合剂层48可包含(例如)导电凝胶或环氧树脂膜(与导电材料混合的环氧树脂)。半导体裸片20安置于腔30中的导电粘合剂层48上。导电粘合剂48用以将半导体裸片20附接到腔30的底部表面301。半导体裸片22、24和26可以类似方式安置。
参考图2C，保护层70通过例如层压技术形成于导电基底101和102以及半导体裸片20、22、24和26上。保护层70还覆盖或填充弯曲结构60。保护层70的材料可包含(例如)聚丙烯树脂或其它合适材料。保护层70的一部分在层压期间熔化。导电层80'通过涂覆、溅镀、电镀或另一合适的技术而安置于保护层70的第一表面701上。导电层82'通过涂覆、溅镀、电镀或另一合适的技术而安置于保护层70的第二表面702上。导电层80'和82'可包含(例如)铝或铜或其合金(例如AlCu)。
参考图2D，通孔38从导电层80'的表面穿过保护层70而形成，且通孔39从导电层82'的表面穿过保护层70而形成。通孔38和39可例如通过钻孔而形成。
参考图2E，经图案化光致抗蚀剂层74安置于导电层80'上且经图案化光致抗蚀剂层76安置于导电层82'上。经图案化光致抗蚀剂层74和76可通过涂覆或另一合适的技术而形成。经图案化光致抗蚀剂层74和76可包含正光致抗蚀剂或其它合适材料。
参考图2F，导电层80'和82'的厚度通过涂覆、溅镀、电镀或另一合适的技术而增加。导电层80和82以及互连结构801和821是通过例如此电镀而形成。
参考图2G，经图案化光致抗蚀剂层74和76通过例如蚀刻工艺等合适的技术而移除。在蚀刻之后，保护层70的第一表面701的一部分暴露且保护层70的第二表面702的一部分暴露。
参考图2H，绝缘层50安置于保护层70的第一表面701上且绝缘层52安置于保护层70的第二表面702上。绝缘层50覆盖经图案化导电层80的至少一部分且绝缘层52覆盖经图案化导电层82的至少一部分。绝缘层50和52中的一者或两者的材料可包含聚丙烯树脂或另外或替代地使用的其它绝缘材料。接着在由绝缘层50界定的通孔37上安置或形成导电连接件75以形成如图1中所说明的半导体装置封装1。导电连接件75可包含(例如)一或多个焊料球。通孔37安置于经图案化导电层80上方。
图3A到3J说明制造图1中描绘的半导体装置封装1的方法的一些实施例。参考图3A，提供导电基底101和102。导电基底101具有第一表面101u以及与第一表面101u相对的表面101b。导电基底102具有第一表面102u以及与第一表面102u相对的表面102b。导电基底101和102的材料包含(例如)铜或另一金属或金属合金或其它导电材料。例如通过钻孔(例如，通过在初始导电基底中钻至少两个孔，进而形成单独导电基底101和102以及连接元件90)而形成连接元件90。第一表面101u界定腔30(例如，第一表面101u具备腔30，或腔30形成于第一表面101u中)。第一表面102u界定腔32(例如，第一表面102u具备腔32，或腔32形成于第一表面102u中)。导电基底101和102界定一或多个弯曲结构60。
参考图3B，导电粘合剂层48安置于腔30的底部表面301上和腔32的上部表面321上。导电粘合剂层48可包含(例如)导电凝胶或环氧树脂膜(与导电材料混合的环氧树脂)。半导体裸片20安置于腔30中的导电粘合剂层48上。导电粘合剂48用以将半导体裸片20附接到腔30的底部表面301。半导体裸片22、24和26可以类似方式安置。
参考图3C，保护层70通过例如层压技术形成于导电基底101和102以及半导体裸片20、22、24和26上。保护层70还覆盖或填充弯曲结构60。保护层70的材料可包含(例如)聚丙烯树脂或其它合适材料。保护层70的一部分在层压期间熔化。导电层80'通过涂覆、溅镀、电镀或另一合适的技术而安置于保护层70的第一表面701上。导电层82'通过涂覆、溅镀、电镀或另一合适的技术而安置于保护层70的第二表面702上。
参考图3D，通孔38从导电层80'的表面穿过保护层70而形成，且通孔39从导电层82'的表面穿过保护层70而形成。通孔38和39可例如通过钻孔而形成。
参考图3E，导电层80'和82'形成且填充通孔38。导电层80'和82'是通过涂覆、溅镀、电镀或另一合适的技术而形成。参考图3F，经图案化光致抗蚀剂层74安置于导电层80'上且经图案化光致抗蚀剂层76安置于导电层82'上。经图案化光致抗蚀剂层74和76可通过涂覆或另一合适的技术而形成。经图案化光致抗蚀剂层74和76可包含正光致抗蚀剂或其它合适材料。
参考图3G，导电层80'的未由经图案化光致抗蚀剂层74覆盖的一部分是通过例如蚀刻或钻孔而移除。导电层82'的未由经图案化光致抗蚀剂层76覆盖的一部分是通过例如蚀刻或钻孔而移除。在蚀刻之后，经图案化导电层80和82以及互连结构801和821的形成完成。
参考图3H，经图案化光致抗蚀剂层74和76通过例如蚀刻工艺等合适的技术而移除。在蚀刻之后，保护层70的第一表面701的一部分暴露且保护层70的第二表面702的一部分暴露。
参考图3I，绝缘层50安置于保护层70的第一表面701的至少一部分上且绝缘层52安置于保护层70的第二表面702的至少一部分上。绝缘层50覆盖经图案化导电层80的至少一部分且绝缘层52覆盖经图案化导电层82的至少一部分。绝缘层50和52中的一者或两者的材料可包含聚丙烯树脂和/或其它绝缘材料。参考图3J，导电连接件75安置或形成于通孔37中以形成如图1中所说明的半导体装置封装1。导电连接件75可包含一或多个焊料球。
图4A是根据本发明的第二方面的半导体装置封装2的一些实施例的横截面视图。半导体装置封装2以某些方式相似于图1中描绘的半导体装置封装1，且一些相同编号的组件不再相对于图4A描述。在半导体装置封装2中，包含导电基底101，同时省略额外导电基底。导电基底101的材料包含例如铜或另一金属或金属合金或其它导电材料。半导体装置封装2包含导电基底101的表面101b上的表面修整层78。表面修整层78可包含任何合适的导电材料(例如包含例如镍(Ni)、钯(Pd)、金(Au)、银(Ag)、Cu和金属的组合)。
导电基底101在导电基底101的第一表面101u中界定腔30。腔30具有底部表面301。半导体裸片20具有电连接到经图案化导电层80的活性表面201和安置于腔30的底部表面301上的表面202。半导体裸片22具有电连接到经图案化导电层82的活性表面221和安置于半导体裸片20的活性表面201上的表面222。半导体裸片20安置于腔30的底部表面301上且半导体裸片22安置于半导体裸片20的活性表面201上。
半导体裸片24具有电连接到经图案化导电层84的活性表面241和腔30的底部表面301上的表面242。半导体裸片24安置于腔30的底部表面301上。半导体裸片20、22和24中的至少一者可为电力裸片，且半导体裸片20、22和24中的至少一者可为控制裸片。导电基底101的第一表面101u通过互连结构801和821电连接到半导体裸片20的活性表面201和堆叠半导体裸片22的活性表面221。堆叠裸片结构提供了在引线框和引线框的低区域(例如，表面积)中集成大量组件。半导体裸片20的活性表面201与半导体裸片22的表面222大体上共面。半导体裸片20的活性表面201沿着半导体裸片22的表面222的侧延伸。
保护层70具有表面701。经图案化导电层80和经图案化导电层82形成于保护层70的表面701上。保护层70覆盖导电基底101的表面101u以及半导体裸片20、22和24的至少一部分，且至少部分地填充腔30。保护层70中的互连结构801电连接到半导体裸片20和经图案化导电层80。保护层70中的互连结构821电连接到半导体裸片22和经图案化导电层82。保护层70中的互连结构841电连接到半导体裸片24和经图案化导电层84。互连结构841电连接到导电基底101的表面101u以及经图案化导电层80和经图案化导电层82中的一者。
图4B说明图4A中描绘的半导体装置封装2的一些实施例的俯视图。在图4B中，半导体裸片20和半导体裸片22至少稍微横向地偏移且并不完美地重叠(例如，半导体裸片20和半导体裸片22的对应侧面或表面并不对准)。半导体裸片20输出的电流可通过导电粘合剂层48传送到导电基底101且通过经图案化导电层80传送到互连结构801。半导体裸片22输出的电流可通过半导体裸片20和导电粘合剂层48传送到导电基底101且通过经图案化导电层82传送到互连结构821。半导体裸片20和22的偏移可按需要实施(例如，可制作为大或小)。
图5A到5I说明制造图4A描绘的半导体装置封装2的方法的一些实施例。参考图5A，提供导电基底101。导电基底101具有第一表面101u以及与第一表面101u相对的表面101b。导电基底101的材料例如为铜或另一金属或金属合金或其它导电材料。导电基底101在导电基底101的第一表面101u中界定腔30。腔30具有底部表面301。
参考图5B，导电粘合剂层48安置于腔30的底部表面301上。导电粘合剂层48可包含(例如)导电凝胶或环氧树脂膜(与导电材料混合的环氧树脂)。半导体裸片20安置于腔30的底部表面301上的导电粘合剂层48上。导电粘合剂48用以将半导体裸片20附接到腔30的底部表面301。半导体裸片20具有活性表面201以及与第一表面201相对的第二表面202。半导体裸片22具有活性表面221以及与第一表面221相对的第二表面222。半导体裸片22通过导电粘合剂层48堆叠于半导体裸片20的活性表面201上。半导体裸片24具有活性表面241以及与第一表面241相对的第二表面242。半导体裸片24安置于腔30的底部表面301上的导电粘合剂层48上。
参考图5C，保护层70安置于半导体裸片20、22和24上且至少部分地填充腔30。保护层70具有表面701。在一些实施例中，保护层70的材料可包含聚丙烯树脂；然而，另外或替代地可使用其它合适的材料。导电层80'安置于保护层70的表面701上。导电层80'的材料可包含(例如)铜或另一金属或金属合金或其它导电材料。
参考图5D，通孔38从经图案化导电层80'的表面穿过保护层70而形成。通孔38可例如通过钻孔而形成。在通孔38形成之后，半导体裸片20的表面201的一部分、半导体裸片22的表面221的一部分、半导体裸片24的表面241的一部分以及导电基底101的表面101u的一部分暴露。
参考图5E，通孔38填充有导电材料84，其类似于或相同于导电层80'的材料。导电层80'的厚度通过涂覆、溅镀、电镀或另一合适的技术而增加。
参考图5F，经图案化光致抗蚀剂层74安置于导电层80'、导电基底101的表面101b以及填充弯曲结构60的保护层70的一部分的底部表面上。经图案化光致抗蚀剂层74可包含正光致抗蚀剂或其它合适材料。
参考图5G，通孔36从导电层80'的表面穿过保护层70而形成。在通孔36形成之后，导电层80和82以及互连结构801和802形成。互连结构801和802以及导电层80和82的材料可包含(例如)铜或另一金属或金属合金或其它导电材料。
参考图5H，经图案化光致抗蚀剂层74通过例如蚀刻工艺等合适的技术而移除。互连结构801和821的上部表面暴露。
参考图5I，绝缘层50安置于保护层70的第一表面701上。绝缘层50覆盖经图案化导电层80的至少一部分。绝缘层50中的一者或两者的材料可包含聚丙烯树脂或另外或替代地使用的其它绝缘材料。表面修整层78安置于导电基底101的第二表面101b上且填充或形成于通孔37中。表面修整层78可包含任何合适的导电材料(例如镍(Ni)、钯(Pd)、金(Au)、银(Ag)、Cu和/或金属的组合)。在至少一个实施例中，表面修整层78可安置于导电基底101的第二表面101b上且覆盖至少部分地填充弯曲结构60的保护层70的一部分。在至少一个实施例中，表面修整层例如为绝缘层，例如焊料掩模。接着，导电连接件75填充到或形成于通孔37中，因此形成如图4A中所说明的半导体装置封装2。
图6A是根据本发明的第三方面的半导体装置封装3的一些实施例的横截面视图。半导体装置封装3以某些方式相似于图4A中描绘的半导体装置封装2，且一些相同编号的组件不再相对于图4A描述。导电基底101在导电基底101的第一表面101u中界定腔30。腔30具有底部表面301。半导体裸片22具有连接到经图案化导电层80的活性表面221和腔30的底部表面301上的表面222。半导体裸片20具有连接到经图案化导电层82的活性表面201和半导体裸片22的活性表面221上的表面202。半导体裸片22安置于腔30的底部表面301上，且半导体裸片20安置于半导体裸片22的活性表面221上。
半导体裸片24具有连接到经图案化导电层84的活性表面241和腔30的底部表面301上的表面242。半导体裸片24安置于腔30的底部表面301上。半导体裸片20、22和24中的一者可为电力裸片，且半导体裸片20、22和24中的一者可为控制裸片。导电基底101的第一表面101u通过互连结构801和821电连接到半导体裸片22的活性表面221和堆叠半导体裸片20的活性表面201。
图6B说明图6A中描绘的半导体装置封装3的一些实施例的俯视图。在图6B中，半导体裸片20和半导体裸片22至少稍微偏移且并不完美地重叠。半导体裸片22输出的电流可通过导电粘合剂层48传送到导电基底101且通过经图案化导电层80传送到互连结构801。半导体裸片20输出的电流可通过半导体裸片22和导电粘合剂层48传送到导电基底101且通过经图案化导电层82传送到互连结构821。半导体裸片20和22的偏移可按需要来实施(例如，可制作为大或小)。
图7A到7I说明制造图6A中描绘的半导体装置封装3的方法的一些实施例。参考图7A，提供导电基底101。导电基底101具有第一表面101u以及与第一表面101u相对的表面101b。导电基底101的材料包含例如铜或另一金属或金属合金或其它导电材料。导电基底101在导电基底101的第一表面101u中界定腔30。腔30具有底部表面301。导电基底101界定弯曲结构60。
参考图7B，导电粘合剂层48安置于腔30的底部表面301上。导电粘合剂层48可包含(例如)导电凝胶或环氧树脂膜(与导电材料混合的环氧树脂)。半导体裸片22安置于腔30的底部表面301中的导电粘合剂层48上。导电粘合剂48用以将半导体裸片22附接到腔30的底部表面301。半导体裸片22具有活性第一表面221以及与第一表面221相对的第二表面222。半导体裸片20具有活性表面201以及与第一表面201相对的表面202。半导体裸片20通过导电粘合剂层48堆叠于半导体裸片22的活性表面221上。半导体裸片24具有活性第一表面241以及与第一表面241相对的第二表面242。半导体裸片24安置于腔30的底部表面301上的导电粘合剂层48上。
参考图7C，保护层70安置于半导体裸片20、22和24上且至少部分地填充腔30。保护层70具有表面701。在一些实施例中，保护层70的材料可包含聚丙烯树脂；然而，另外或替代地可使用其它合适的材料。导电层80'安置于保护层70的表面701上。导电层80'的材料可包含(例如)铜或另一金属或金属合金或其它导电材料。
参考图7D，通孔38从经图案化导电层80'的表面穿过保护层70而形成。通孔38可例如通过钻孔而形成。在通孔38形成之后，半导体裸片20的表面201的一部分、半导体裸片22的表面221的一部分、半导体裸片24的表面241的一部分以及导电基底101的表面101u的一部分暴露。
参考图7E，通孔38填充有类似于或相同于导电层80'的材料的导电材料。导电层80'的厚度通过涂覆、溅镀、电镀或另一合适的技术而增加。
参考图7F，经图案化光致抗蚀剂层74安置于导电层80'上，导电基底101的表面101b上，以及至少部分地填充弯曲结构60的保护层70的一部分的底部表面上。经图案化光致抗蚀剂层74可包含正光致抗蚀剂或其它合适材料。
参考图7G，通孔36从导电层80'的表面穿过保护层70而形成。在通孔36形成之后，导电层80和82以及互连结构801和802形成。互连结构801和802以及导电层80和82的材料可包含(例如)铜或另一金属或金属合金或其它导电材料。
参考图7H，经图案化光致抗蚀剂层74通过例如蚀刻工艺等合适的技术而移除。互连结构801和821的第一表面暴露。
参考图7I，绝缘层50安置于保护层70的第一表面701上。绝缘层50覆盖经图案化导电层80的至少一部分。绝缘层50中的一者或两者的材料可包含聚丙烯树脂或另外或替代地使用的其它绝缘材料。表面修整层78安置于导电基底101的表面101b上且填充到通孔37中。当表面修整层78可包含任何合适的导电材料(例如包含例如镍(Ni)、钯(Pd)、金(Au)、银(Ag)、Cu和金属的组合)时填充于弯曲结构60中的保护层70从表面修整层78暴露。在一个实施例中，所述表面修整层可安置于导电基底101的表面101b上且覆盖至少部分地填充弯曲结构60的保护层70。在一些实施例中，所述表面修整层是例如绝缘层，例如焊料掩模。接着，导电连接件75填充到通孔37中以完成如图6A中所说明的半导体装置封装3。
图8是根据本发明的第四方面的半导体装置封装4的一些实施例的横截面视图。半导体装置封装4以某些方式类似于图1的半导体装置封装1，且一些相同编号的组件不再相对于图8描述。在图8中，半导体装置封装4包含导电基底101、半导体裸片20、22和24、导电粘合剂层48、保护层70a和72a、绝缘层50、经图案化导电层80、82、84和86、互连结构801、821、841和861，以及导电连接件75。
保护层70a覆盖导电基底101的表面101u和半导体裸片20的至少一部分。保护层70a具有表面701a。保护层70a覆盖半导体裸片22和24的至少一部分。经图案化导电层80形成于保护层70a上且电连接到半导体裸片20。半导体裸片22通过导电粘合剂层48结合到经图案化导电层80。半导体裸片24通过导电粘合剂层48结合到经图案化导电层80。保护层72a形成于经图案化导电层80上和保护层70a的表面701a上。保护层72a覆盖半导体裸片22的至少一部分。经图案化导电层82安置于电介质层72a上且电连接到半导体裸片22。
半导体裸片20具有活性表面201和表面202。导电基底101在导电基底101的第一表面101u中界定腔30。半导体裸片20通过导电粘合剂层48结合到腔30的底部表面301。互连结构801形成于保护层70a中。互连结构801电连接到导电基底101的表面101u和经图案化导电层80。半导体裸片20的活性表面201通过互连结构801电连接到经图案化导电层80。半导体裸片22具有活性表面221和表面222。半导体裸片20通过导电粘合剂层48结合到半导体裸片20的活性表面201。互连结构821形成于保护层72a中。互连结构821连接到经图案化导电层80和经图案化导电层82。半导体裸片22的活性表面222通过互连结构821连接到经图案化导电层82。半导体裸片24具有活性表面241和表面242。半导体裸片24通过导电粘合剂层48结合到腔30的底部表面301。半导体裸片20的活性表面201通过经图案化导电层80和互连结构801连接到半导体裸片24的活性表面241。互连结构801和821以及经图案化导电层80和82的材料可包含(例如)铜或另一金属或金属合金或其它导电材料。
图9A到9L说明制造图8中描绘的半导体装置封装4的方法的一些实施例。参考图9A，提供导电基底101。导电基底101具有第一表面101u以及与第一表面101u相对的表面101b。导电基底101界定弯曲结构60。导电基底101的材料例如为铜或另一金属或金属合金或其它导电材料。导电基底101在导电基底101的第一表面101u中界定腔30。腔30具有底部表面301。
参考图9B，导电粘合剂层48和裸片附接膜49安置于腔30的底部表面301上。导电粘合剂层48可包含(例如)导电凝胶或环氧树脂膜(与导电材料混合的环氧树脂)。在一些实施例中，导电粘合剂层48可包含裸片附接膜。半导体裸片20安置于腔30的底部表面301中的导电粘合剂层48上。导电粘合剂48用以将半导体裸片20附接到腔30的底部表面301。半导体裸片20具有活性第一表面201以及与第一表面201相对的第二表面202。半导体裸片24安置于腔30的底部表面301中的裸片附接膜49上。裸片附接膜49用以将半导体裸片24附接到腔30的底部表面301。半导体裸片24具有活性第一表面241以及与第一表面201相对的第二表面242。
参考图9C，保护层70a安置于半导体裸片20和24上且至少部分地填充腔30和弯曲结构60。保护层70a具有表面701a。在一些实施例中，保护层70a的材料可包含聚丙烯树脂；然而，另外或替代地可使用其它合适的材料。导电层80'安置于保护层70a的表面701a上。导电层80'的材料可包含(例如)铜或另一金属或金属合金或其它导电材料。
参考图9D，通孔38从经图案化导电层80'的表面穿过保护层70a而形成。通孔38可例如通过钻孔而形成。在通孔38形成之后，半导体裸片20的表面201的一部分、半导体裸片24的表面241的一部分以及导电基底101的表面101u的一部分暴露。
参考图9E，通孔38填充有类似于或相同于导电层80'的材料的导电材料。导电层80'的厚度通过涂覆、溅镀、电镀或另一合适的技术而增加。
参考图9F，导电层80和互连结构801是通过光刻技术形成。互连结构801和导电层80的材料可包含(例如)铜或另一金属或金属合金或其它导电材料。参考图9G，半导体裸片22通过导电粘合剂层48安置于互连结构801上。半导体裸片20和22可为电力裸片，且半导体裸片24可为控制裸片。
参考图9H，保护层72a安置于半导体裸片22上且覆盖互连结构801。保护层72a具有表面721a。在一些实施例中，保护层72a的材料可包含聚丙烯树脂；然而，另外或替代地可使用其它合适的材料。导电层82'安置于保护层72a的表面721a上。导电层82'的材料可包含(例如)铜或另一金属或金属合金或其它导电材料。
参考图9I，通孔38'是从经图案化导电层82'的表面穿过保护层72a而形成。通孔38'可例如通过钻孔而形成。在通孔38'形成之后，半导体裸片22的表面221的一部分以及互连结构801的表面的一部分暴露。
参考图9J，通孔38填充有类似于或相同于导电层82'的材料的导电材料。导电层82'的厚度通过涂覆、溅镀、电镀或另一合适的技术而增加。
参考图9K，导电层82和互连结构821是通过光刻技术而形成。互连结构821和导电层82的材料可包含(例如)铜或另一金属或金属合金或其它导电材料。
参考图9L，绝缘层50安置于保护层72a的第一表面721上。绝缘层50覆盖经图案化导电层82的至少一部分。绝缘层50中的一者或两者的材料可包含聚丙烯树脂或另外或替代地使用的其它绝缘材料。接着，导电连接件75填充到或形成于通孔37中，因此形成如图8中所说明的半导体装置封装4。
图10A到10M说明根据本发明的第五方面的制造半导体装置封装5的方法的一些实施例。参考图10A，提供导电基底101。导电基底101具有第一表面101u以及与第一表面101u相对的表面101b。导电基底101界定上部弯曲结构60'。导电基底101的材料例如为铜或另一金属或金属合金或其它导电材料。腔30是从导电基底101的第一表面101u界定。腔30具有底部表面301。
参考图10B，导电粘合剂层48安置于腔30的底部表面301上。导电粘合剂层48可包含(例如)导电凝胶或环氧树脂膜(与导电材料混合的环氧树脂)。半导体裸片20安置于腔30的底部表面301中的导电粘合剂层48上。导电粘合剂48用以将半导体裸片20附接到腔30的底部表面301。半导体裸片20具有活性第一表面201以及与第一表面201相对的第二表面202。半导体裸片24安置于腔30的底部表面301中的导电粘合剂层48上。导电粘合剂48用以将半导体裸片24附接到腔30的底部表面301。半导体裸片24具有活性第一表面241以及与第一表面201相对的第二表面242。在一些实施例中，导电粘合剂层48可为裸片附接膜。在一些实施例中，半导体裸片20可为电力裸片且半导体裸片24可为控制器。
参考图10C，保护层70a安置于半导体裸片20和24上且至少部分地填充腔30和上部弯曲结构60'。保护层70a具有表面701a。在一些实施例中，保护层70a的材料可包含聚丙烯树脂；然而，另外或替代地可使用其它合适的材料。导电层80'安置于保护层70a的表面701a上。导电层80'的材料可包含(例如)铜或另一金属或金属合金或其它导电材料。
参考图10D，通孔38从经图案化导电层80'的表面穿过保护层70a而形成。通孔38可例如通过钻孔而形成。在通孔38形成之后，半导体裸片20的表面201的一部分、半导体裸片24的表面241的一部分以及导电基底101的表面101u的一部分暴露。
参考图10E，通孔38填充有类似于或相同于导电层80'的材料的导电材料。导电层80'的厚度通过涂覆、溅镀、电镀或另一合适的技术而增加。
参考图10F，导电层80和互连结构801是通过光刻技术形成。互连结构801和导电层80的材料可包含(例如)铜或另一金属或金属合金或其它导电材料。上部弯曲结构60'下方的导电基底101的一部分是通过蚀刻移除以形成弯曲结构60。
参考图10G，半导体裸片22通过导电粘合剂层48安置于互连结构801上。半导体裸片20、22和24中的至少一者可为电力裸片，且半导体裸片20、22和24中的至少一者可为控制裸片。
参考图10H，保护层72a安置于半导体裸片22和导电基底101的表面101b上。保护层72a还覆盖互连结构801且至少部分地填充弯曲结构60。保护层72a具有表面721a和表面721b。在一些实施例中，保护层72a的材料可包含聚丙烯树脂；然而，另外或替代地可使用其它合适的材料。导电层82'安置于保护层72a的表面721a上，且导电层84安置于保护层72a的表面721b上。导电层82'和84的材料可包含(例如)铜或另一金属或金属合金或其它导电材料。
参考图10I，通孔38'是从经图案化导电层82'的表面穿过保护层72a而形成。通孔38'可例如通过钻孔而形成。在通孔38'形成之后，半导体裸片22的表面221的一部分以及互连结构801的表面的一部分暴露。
参考图10J，通孔38填充有类似于或相同于导电层82'的材料的导电材料。导电层82'的厚度通过涂覆、溅镀、电镀或另一合适的技术而增加。参考图10K，导电层82和互连结构821是通过光刻技术而形成。互连结构821和导电层82的材料可包含(例如)铜或另一金属或金属合金或其它导电材料。
参考图10L，绝缘层50安置于保护层72a的第一表面721上。绝缘层50覆盖经图案化导电层82的至少一部分。绝缘层50中的一者或两者的材料可包含聚丙烯树脂或另外或替代地使用的其它绝缘材料。参考图10M，导电连接件75填充到通孔37中。接着，表面修整层78形成于导电层84上以形成半导体装置封装5。表面修整层78可包含任何合适的导电材料(例如镍(Ni)、钯(Pd)、金(Au)、银(Ag)、Cu和金属的组合)。
图11A到11I说明根据第六方面的制造半导体装置封装6的方法的一些实施例。参考图11A，提供导电基底101和102。导电基底101具有第一表面101u以及与第一表面101u相对的表面101b。导电基底102具有第一表面102u以及与第一表面102u相对的表面102b。导电基底101和102的材料包含(例如)铜或另一金属或金属合金或其它导电材料。例如通过钻孔(例如，通过在初始导电基底中钻至少两个孔，进而形成单独导电基底101和102以及连接元件90)而形成连接元件90。导电基底101在导电基底101的第一表面101u中界定腔30，且导电基底102在导电基底102的第一表面102u中界定腔。腔30具有底部表面301。腔32具有上部表面321。导电基底101界定一或多个弯曲结构60。导电基底101的弯曲结构60经平滑且可帮助再分布应力以避免在层压期间对保护层70的损坏。导电基底101的结构可以与导电基底102相同或相似方式形成，例如以形成本文所描述的导电基底的任何适当方式。
参考图11B，导电粘合剂层48安置于腔30的底部表面301上，导电基底101的表面101b上以及腔32的上部表面321上。导电粘合剂层48可包含(例如)导电凝胶或环氧树脂膜(与导电材料混合的环氧树脂)。半导体裸片20安置于腔30中的导电粘合剂层48上。导电粘合剂48用以将半导体裸片20附接到腔30的底部表面301。半导体裸片22、24和26可通过导电粘合剂层48的附接而安置。
参考图11C，保护层70安置于半导体裸片20、22和24上且至少部分地填充腔30和32。保护层70具有第一表面701和第二表面702。在一些实施例中，保护层70的材料可包含聚丙烯树脂；然而，另外或替代地可使用其它合适的材料。导电层80'安置于保护层70的表面701上且导电层82'安置于保护层70的第二表面702上。导电层80'和82'的材料可包含(例如)铜或另一金属或金属合金或其它导电材料。
参考图11D，通孔38是从经图案化导电层80'和82'的表面穿过保护层70而形成。通孔38可例如通过钻孔而形成。在通孔38形成之后，半导体裸片20的表面201的一部分、半导体裸片22的表面221的一部分、半导体裸片24的表面241的一部分以及导电基底101的表面101u的一部分暴露。
参考图11E，至少部分地以类似于或相同于导电层80'和82'的材料的导电材料填充通孔38。导电层80'和82'的厚度通过涂覆、溅镀、电镀或另一合适的技术而增加。
参考图11F，经图案化光致抗蚀剂层74安置于导电层80'上且经图案化光致抗蚀剂层76安置于导电层82'上。经图案化光致抗蚀剂层74和76可包含正光致抗蚀剂或其它合适材料。
参考图11G，移除导电层80'和82'中的每一者的一部分。在所述移除之后，导电层80和82以及互连结构801和821形成。参考图11H，经图案化光致抗蚀剂层74和76通过例如蚀刻工艺等合适的技术而移除。在蚀刻之后，保护层70的第一表面701的一部分暴露且保护层70的第二表面702的一部分暴露。
参考图11I，绝缘层50安置于保护层70的第一表面701上且绝缘层52安置于保护层70的第二表面702上。绝缘层50覆盖经图案化导电层80的至少一部分且绝缘层52覆盖经图案化导电层82的至少一部分。绝缘层50和52中的一者或两者的材料可包含聚丙烯树脂或另外或替代地使用的其它绝缘材料。接着，导电连接件75填充或形成于通孔37中，因此形成半导体装置封装6。导电连接件75可包含一或多个焊料球。通孔37安置于经图案化导电层80上。
图12A到12I说明根据第七方面的制造半导体装置封装7的方法的一些实施例。参考图12A，提供导电基底101和102。导电基底101具有第一表面101u以及与第一表面101u相对的表面101b。导电基底102具有第一表面102u以及与第一表面102u相对的表面102b。导电基底101和102的材料包含(例如)铜或另一金属或金属合金或其它导电材料。例如通过钻孔(例如，通过在初始导电基底中钻至少两个孔，进而形成单独导电基底101和102以及连接元件90)而形成连接元件90。腔30是从导电基底101的第一表面101u界定。腔32是从导电基底102的第一表面102u界定。腔30具有底部表面301。腔32具有上部表面321。导电基底101界定一或多个弯曲结构60。导电基底101的弯曲结构60经平滑，且可帮助再分布应力以避免在层压期间对保护层70的损坏。导电基底101的结构可以与导电基底102相同或相似的方式形成，例如以本文所描述的任何适当方式。
参考图12B，导电粘合剂层48安置于腔30的底部表面301上，导电基底101的表面101b上以及腔32的上部表面321上。导电粘合剂层48可包含(例如)导电凝胶或环氧树脂膜(与导电材料混合的环氧树脂)。半导体裸片20安置于腔30中的导电粘合剂层48上。导电粘合剂48用以将半导体裸片20附接到腔30的底部表面301。半导体裸片22、24和26可通过导电粘合剂层48的附接而安置。
参考图12C，保护层70安置于半导体裸片20、22和24上且至少部分地填充腔30和32。保护层70具有第一表面701和第二表面702。在一些实施例中，保护层70的材料可包含聚丙烯树脂；然而，另外或替代地可使用其它合适的材料。导电层80'安置于保护层70的表面701上且导电层82'安置于保护层70的第二表面702上。导电层80'和82'的材料可包含(例如)铜或另一金属或金属合金或其它导电材料。
参考图12D，通孔38是从经图案化导电层80'和82'的表面穿过保护层70而形成。通孔38可例如通过钻孔而形成。在通孔38形成之后，半导体裸片20的表面201的一部分、半导体裸片22的表面221的一部分、半导体裸片24的表面241的一部分以及导电基底101的表面101u的一部分暴露。
参考图12E，通孔38填充有类似于或相同于导电层80'和82'的材料的导电材料。导电层80'和82'的厚度通过涂覆、溅镀、电镀或另一合适的技术而增加。
参考图12F，经图案化光致抗蚀剂层74安置于导电层80'上且经图案化光致抗蚀剂层76安置于导电层82'上。经图案化光致抗蚀剂层74和76可包含正光致抗蚀剂或其它合适材料。
参考图12G，移除导电层80'和82'的一部分。在所述移除之后，导电层80和82以及互连结构801和821形成。参考图12H，经图案化光致抗蚀剂层74和76通过例如蚀刻工艺等合适的技术而移除。在蚀刻之后，保护层70的第一表面701的一部分暴露且保护层70的第二表面702的一部分暴露。
参考图12I，绝缘层50安置于保护层70的第一表面701上且绝缘层52安置于保护层70的第二表面702上。绝缘层50覆盖经图案化导电层80的至少一部分且绝缘层52覆盖经图案化导电层82的至少一部分。绝缘层50和52中的一者或两者的材料可包含聚丙烯树脂或另外或替代地使用的其它绝缘材料。接着，导电连接件75填充或形成于通孔37中，以形成半导体装置封装7。导电连接件75可包含一或多个焊料球。通孔37安置于经图案化导电层80上。
如本文中所使用，术语“大致”、“大体上”、“大体”及“约”用以描述并考虑小变化。当与事件或情形结合使用时，所述术语可以指其中事件或情形明确发生的情况以及其中事件或情形极接近于发生的情况。举例来说，当结合数值使用时，术语可指代小于或等于所述数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％。因此，参考两个值的术语“近似相等”可指代所述两个值的比率处于0.9与1.1之间(包含性)的范围内。
另外，有时在本文中按范围格式呈现量、比率及其它数值。应理解，此类范围格式是用于便利和简洁起见，且应灵活地理解，不仅包含明确地指定为范围限制的数值，而且包含涵盖于所述范围内的所有个别数值或子范围，如同明确地指定每一数值和子范围一般。
两个表面或侧面可在所述两个表面之间的位移不大于0.5μm、不大于1μm、不大于5μm、不大于10μm或不大于15μm的情况下视为对准的。在一些实施例的描述中，提供于另一组件“上”的组件可涵盖前一组件直接在后一组件上(例如，物理接触)的情况，以及一或多个介入组件位于前一组件与后一组件之间的情况。
虽然已参考本发明的特定实施例描述及说明本发明，但这些描述及说明并不限制本发明。所属领域的技术人员应理解，可在不脱离如由所附权利要求书界定的本发明的真实精神和范围的情况下，作出各种改变且取代等效物。所述说明可能未必按比例绘制。归因于制造工艺和容差，本发明中的艺术再现与实际设备之间可存在区别。可存在并未特定说明的本发明的其它实施例。应将本说明书及图式视为说明性的而非限制性的。可做出修改，以使具体情况、材料、物质组成、方法或工艺适应于本发明的目标、精神和范围。所有所述修改都既定在所附权利要求书的范围内。虽然本文中所揭示的方法已参考按特定次序执行的特定操作加以描述，但应理解，可在不脱离本发明的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此，除非本文中特别指示，否则操作的次序和分组并非本发明的限制。

Claims (20)

1.一种半导体装置封装，其包括：
第一导电基底，其具有第一表面和与所述第一表面相对的第二表面，且在所述第一导电基底的所述第一表面中界定第一腔，所述第一腔具有底部表面；
第一半导体裸片，其安置于所述第一腔的所述底部表面上；
电介质层，其安置于所述第一半导体裸片、所述第一导电基底的所述第一表面和所述第二表面上且填充所述第一腔，其中所述电介质层具有第一表面和与所述第一表面相对的第二表面；
第一经图案化导电层，其安置于所述电介质层的所述第一表面上；
第二经图案化导电层，其安置于所述电介质层的所述第二表面上；
多个第一互连结构，其安置于所述电介质层中且电连接到所述第一半导体裸片和所述第一经图案化导电层；以及
多个第二互连结构，其安置于所述电介质层中且电连接到所述第一导电基底的所述第二表面和所述第二经图案化导电层。
2.根据权利要求1所述的半导体装置封装，其进一步包括：
第二导电基底，其具有第一表面和第二表面，所述第二导电基底的所述第一表面与所述第一导电基底的所述第一表面相对，第二腔界定于所述第二导电基底的所述第一表面中，所述第二导电基底的所述第二腔具有顶部表面；
第二半导体裸片，其安置于所述第二腔的所述顶部表面上，所述电介质层囊封所述第二导电基底的所述第一表面和所述第二表面且囊封所述第二半导体裸片；
其中所述第二导电基底的所述第二表面通过所述多个第一互连结构电连接到所述第一经图案化导电层，且所述第二半导体裸片通过所述多个第二互连结构电连接到所述第二经图案化导电层。
3.根据权利要求2所述的半导体装置封装，其中所述第一半导体裸片通过所述第一导电基底和所述第二互连结构电连接到所述第二半导体裸片。
4.根据权利要求2所述的半导体装置封装，其进一步包括：
第四裸片，其安置于所述第二导电基底的所述第二表面上，其中所述第四裸片电连接到所述第一经图案化导电层。
5.根据权利要求2所述的半导体装置封装，其中所述第一和第二导电基底中的至少一者界定至少一个弯曲结构。
6.根据权利要求1所述的半导体装置封装，其进一步包括：
第一焊料掩模，其安置于所述电介质层的所述第一表面上；以及
第二焊料掩模，其安置于所述电介质层的所述第二表面上。
7.根据权利要求1所述的半导体装置封装，其进一步包括：
第三裸片，其安置于所述第一腔的所述底部表面上，其中所述第三裸片电连接到所述第二经图案化导电层。
8.根据权利要求1所述的半导体装置封装，其进一步包括：
连接元件，其安置于所述电介质层中，其中所述连接元件电连接到所述第一经图案化导电层和所述第二经图案化导电层中的至少一者。
9.根据权利要求8所述的半导体装置封装，其中所述连接元件是金属组件或填充有导电材料的穿孔。
10.一种半导体装置封装，其包括：
导电基底，其具有第一表面和与所述第一表面相对的第二表面，且在所述第一导电基底的所述第一表面中界定腔，所述腔具有底部表面；
第一半导体裸片，其安置于所述腔的所述底部表面上；
第二半导体裸片，其安置于所述第一半导体裸片上；
电介质层，其安置于所述导电基底的所述第一表面、所述第一半导体裸片和所述第二半导体裸片上且填充所述腔，其中所述电介质层具有第一表面；
第一经图案化导电层和第二经图案化导电层，其安置于所述电介质层的所述第一表面上；
多个第一互连结构，其安置于所述电介质层中且电连接到所述第一半导体裸片和所述第一经图案化导电层；以及
多个第二互连结构，其在所述电介质层中且电连接到所述第二半导体裸片和所述第二经图案化导电层。
11.根据权利要求10所述的半导体装置封装，其进一步包括：
多个第三互连结构，其安置于所述电介质层中且电连接到所述导电基底的所述第一表面以及所述第一和第二经图案化导电层中的一者。
12.根据权利要求10所述的半导体装置封装，其中所述第一半导体裸片具有连接到所述第一经图案化导电层的第一活性表面以及在所述腔的所述底部表面上的第二表面，且所述第二半导体裸片具有连接到所述第二经图案化导电层的第一活性表面以及在所述第一半导体裸片的所述第一活性表面上的第二表面。
13.根据权利要求12所述的半导体装置封装，其中所述第一半导体裸片和所述第二半导体裸片横向地偏移。
14.根据权利要求10所述的半导体装置封装，其进一步包括在所述导电基底的所述第二表面上的表面修整层。
15.一种半导体装置封装，其包括：
导电基底，其具有第一表面和与所述第一表面相对的第二表面，且在所述导电基底的所述第一表面中界定腔，所述腔具有底部表面；
第一半导体裸片，其安置于所述腔的所述底部表面上；
第一电介质层，其安置于所述导电基底的所述第一表面和所述第一半导体裸片上，其中所述第一电介质层具有第一表面；
第一经图案化导电层，其安置于所述第一电介质层上且电连接到所述第一半导体裸片；
第二半导体裸片，其安置于所述第一经图案化导电层上；
第二电介质层，其安置于所述第一经图案化导电层、所述第一电介质层的所述第一表面以及所述第二半导体裸片上；以及
第二经图案化导电层，其安置于所述第二电介质层上且电连接到所述第二半导体裸片。
16.根据权利要求15所述的半导体装置封装，其进一步包括：
多个互连结构，其安置于所述第一电介质层中且电连接到所述第一半导体裸片和所述第一经图案化导电层。
17.根据权利要求15所述的半导体装置封装，其进一步包括：
多个互连结构，其安置于所述第一电介质层中且电连接到所述导电基底的所述第一表面和所述第一经图案化导电层。
18.根据权利要求15所述的半导体装置封装，其进一步包括：
多个互连结构，其安置于所述第二电介质层中且电连接到所述第一经图案化导电层和所述第二经图案化导电层。
19.根据权利要求15所述的半导体装置封装，其进一步包括：
多个互连结构，其安置于所述第二电介质层中且电连接到所述第二半导体裸片和所述第二经图案化导电层。
20.根据权利要求15所述的半导体装置封装，其进一步包括：
第三裸片，其安置于所述腔中且电连接到所述第一经图案化导电层。
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