CN107768363A - 可堆叠模制封装及其制造方法 - Google Patents

可堆叠模制封装及其制造方法 Download PDF

Info

Publication number
CN107768363A
CN107768363A CN201710701275.1A CN201710701275A CN107768363A CN 107768363 A CN107768363 A CN 107768363A CN 201710701275 A CN201710701275 A CN 201710701275A CN 107768363 A CN107768363 A CN 107768363A
Authority
CN
China
Prior art keywords
substrate
interconnection
attached
encapsulation
insert
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710701275.1A
Other languages
English (en)
Inventor
阿希莱什·库马尔·辛格
尼尚特·拉赫拉
纳瓦斯·坎·奥拉提卡兰达尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of CN107768363A publication Critical patent/CN107768363A/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/162Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1076Shape of the containers
    • H01L2225/1082Shape of the containers for improving alignment between containers, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

提供一种可堆叠封装组件和制造方法。所述方法包括将多个互连球附接至基板的第一表面,以及用包封剂包封所述基板的所述第一表面和所述多个互连球。在所述包封剂的第一表面中形成暴露所述互连球的一部分的沟槽。提供具有第一互连层的插入件。通过将第一互连层的连接部位附接至所述互连球的所述暴露的部分形成组件,第二基板的第一表面延伸到所述沟槽中。

Description

可堆叠模制封装及其制造方法
技术领域
本公开大体上涉及装置封装,并且更具体地说,涉及可堆叠模制封装及制作可堆叠模制封装的方法。
背景技术
封装的半导体装置往往见于大范围的电子产品中--从缝纫机到洗衣机,从汽车到蜂窝电话等等。这些封装的半导体装置通常安装在例如印刷电路板的基板上。为了保持产品成本较低或为了减少产品成本,通常的做法是使产品内所使用的材料量最小化,从而频繁地减少产品自身的大小。由于电子产品大小减少,所以印刷电路板基板面变得更加珍贵,从而对封装的半导体装置的大小、数量和特征赋予额外约束。可堆叠封装可堆叠在层叠封装布置中,从而使功能最大化,同时对印刷电路板基板面具有最小影响。
发明内容
根据本发明的第一方面,提供一种制造封装组件的方法,所述方法包括:
将多个互连球附接至第一基板的第一表面;
用包封剂包封所述第一基板的所述第一表面和所述多个互连球;
在所述包封剂的暴露所述互连球的一部分的第一表面中形成沟槽,所述互连球的暴露的部分为安置在所述第一基板的所述第一表面处的第一导电层提供电连接性;
提供具有安置在第二基板的第一表面处的第一互连层的插入件;以及
通过将所述第一互连层的连接部位附接至所述互连球的暴露的部分形成组件,所述第二基板的所述第一表面延伸到所述沟槽中。
在一个或多个实施例中,所述方法进一步包括将第一多个球连接器附接至所述第一基板的第二表面。
在一个或多个实施例中,包封进一步包括包封附接至所述第一基板的所述第一表面的半导体管芯。
在一个或多个实施例中,在倒装芯片配置中,所述半导体管芯被附接至所述第一基板的所述第一表面。
所述沟槽为至少部分围绕所述半导体管芯的连续沟槽。
形成组件进一步包括所述第二基板的第二表面,与所述包封剂的所述第一表面相比,所述第二基板的第二表面被定位成距第一基板的所述第一表面更远。
在一个或多个实施例中,所述方法进一步包括将封装的装置附接至安置在所述第二基板的所述第二表面处的第二互连层的连接部位。
在一个或多个实施例中,所述封装的装置在所述半导体管芯上方。
在一个或多个实施例中,使用膜辅助模制技术形成所述沟槽。
根据本发明的第二方面,提供一种制造封装组件的方法,所述方法包括:
提供具有第一表面的封装基板;
将管芯附接至所述封装基板的所述第一表面;
将多个互连球附接至所述封装基板的所述第一表面,所述多个互连球至少部分围绕所述管芯且电连接至所述管芯;
用包封剂包封所述封装基板的所述第一表面、管芯和多个互连球;
在所述包封剂的暴露所述互连球的顶部的第一表面中形成空腔,所述互连球的所述暴露的顶部为安置在所述封装基板的所述第一表面处的第一导电层提供电连接性;
提供具有安置在插入件基板的第一表面处的第一互连层的插入件;以及
通过将所述第一互连层的连接部位附接至所述互连球的暴露的顶部形成组件,所述插入件基板的所述第一表面延伸到所述空腔中。
在一个或多个实施例中,所述方法进一步包括将第一多个球连接器附接至所述封装基板的第二表面。
在一个或多个实施例中,在倒装芯片配置中,所述半导体管芯被附接至所述封装基板的所述第一表面。
在一个或多个实施例中,形成空腔为形成暴露至少部分围绕所述管芯的所述互连球的顶部的连续空腔。
在一个或多个实施例中,形成组件进一步包括所述插入件基板的第二表面在所述包封剂的所述第一表面上方延伸。
在一个或多个实施例中,所述方法进一步包括将封装的装置附接至安置在所述插入件基板的所述第二表面处的第二互连层的连接部位。
在一个或多个实施例中,所述多个互连球使用焊料回流工艺附接至所述封装基板的所述第一表面。
根据本发明的第三方面,提供一种封装组件,包括:
第一封装,包括:
具有第一表面的封装基板,
附接至所述封装基板的所述第一表面的管芯,
附接至所述封装基板的所述第一表面的多个互连球,所述多个互连球至少部分围绕所述管芯,
具有顶面的包封剂,所述包封剂包封所述封装基板的所述第一表面、管芯和多个互连球,以及
形成在所述包封剂的暴露所述互连球的顶部的所述顶面中的沟槽,所述互连球的所述暴露的顶部为安置在所述第一基板的所述第一表面处的第一导电层提供电连接性;以及
插入件,包括:
具有顶面和底面的插入件基板,所述底面被放置在所述沟槽中且在所述包封剂的所述顶面下方,
安置在所述插入件基板的所述顶面处的第一互连层,以及
安置在所述插入件基板的所述底面处的第二互连层,所述第二互连层具有耦合至所述互连球的所述暴露的顶部的连接部位。
在一个或多个实施例中,所述封装组件进一步包括附接至所述封装基板的第二表面的第一多个球连接器。
在一个或多个实施例中,所述封装组件进一步包括附接至所述第一互连层的连接部位的第二封装。
在一个或多个实施例中,在倒装芯片配置中,所述管芯被附接至所述封装基板的所述第一表面。
本发明的这些和其它方面将根据下文中所描述的实施例显而易见,且参考这些实施例予以阐明。
附图说明
借助于例子示出本发明,并且本发明不受附图限制,在附图中,类似标记指示类似元件。为简单和清楚起见,示出图中的元件,并且未必按比例绘制图中的元件。
图1至图3以简化的横截面视图示出根据本公开的实施例的示例性可堆叠封装的制造阶段。
图4至图5以简化的平面视图和横截面视图示出根据本公开的实施例的示例性插入件。
图6至图7以简化的横截面视图示出根据本公开的实施例的用图5的插入件和图3的可堆叠封装形成的示例性组件。
图8以简化的横截面视图示出根据本公开的实施例的示例性层叠封装配置。
具体实施方式
大体上,提供可堆叠封装和制造可堆叠封装的方法,可堆叠封装和制造可堆叠封装的方法使用重新配置的插入件并入嵌入式互连球,从而允许柔性层叠封装配置。所形成的沟槽暴露嵌入式互连球的顶部,从而提供各种插入件的附接。通过将插入件附接至可堆叠封装所形成的组件允许封装的装置被安裝在可堆叠封装上方。
图1以简化的横截面视图示出根据本公开的实施例的包括第一基板和第一管芯的示例性可堆叠封装100的制造阶段。例如,基板102包括多个互连或路由层(未示出),多个互连或路由层(未示出)允许从基板102的顶面至基板102的底面的信号传递。在倒装芯片配置中,管芯104借助于导电凸块或键合球106以有源表面面向下附接至基板102。虽然图1将管芯104示为倒装芯片键合到基板102,但是管芯104可使用其它技术,例如通过有源表面向上、具有在管芯104的有源表面和基板102的顶面之间提供电连接性的键合线,附接至基板102。
基板102可包括任何合适的非导电材料,例如陶瓷、FR-4、BT环氧树脂或有机散装材料(例如,标准印刷电路板(PCB)材料)。例如,基板102可形成为具有安置在非导电层之间的导电互连层的层压体。例如,基板102可形成为任何合适的形状,例如矩形和正方形。例如,互连层可通过任何合适的工艺,例如溅镀、沉积、电镀等等附接至基板102或形成在基板102中。基板102的多个互连层允许在基板102的顶侧表面和基板102的底侧表面之间的信号传递。互连层可由各种导电材料形成,各种导电材料包括例如,铜、金、银、铝、镍、钨及其合金,以包括焊料、掺杂材料(例如,磷、硼掺杂的多晶硅)、超导材料和陶瓷(例如,氧化铜材料、铁基材料和其它合适的金属基材料)。也可取决于工艺由多于一种类型的材料形成互连层,以创建导电层、组件和特定封装结构。
管芯104可为由任何半导材料,例如硅、锗、砷化镓、氮化镓等等形成的半导体管芯。管芯104可包括数字电路、模拟电路、存储器、处理器、MEMS、传感器等等中的任一个,或数字电路、模拟电路、存储器、处理器、MEMS、传感器等等的组合。例如,在一些实施例中,管芯104可包括一或多个分立部件,例如电阻器、电感器、电容器、高压场效应晶体管等等。管芯104可形成为任何大小或几何形状。
导电键合球106将管芯104上的键合部位与基板102的互连层电耦合。在此实施例中,键合球106可被称为焊料球或焊料凸块。例如,可由一种或多种导电材料,例如锡、银、铜等等形成键合球106。例如,在可替换的实施例中,键合球106可为任何合适的导电结构,例如金扣柱、铜柱等等,以将管芯104上的键合部位与基板102的互连层电耦合。
图2以简化的横截面视图示出根据本公开的实施例的包括附接至基板102的第一互连球202的可堆叠封装100的后续制造阶段。互连球202被电耦合至基板102的一个或多个互连层。例如,可由一种或多种导电材料,例如锡、银、铜等等形成互连球202。例如,在可替换的实施例中,互连球202可包括任何合适的导电结构,例如金扣柱、铜柱等等。
图3以简化的横截面视图示出根据本公开的实施例的包括包封剂302的可堆叠封装100的后续制造阶段。基板102的顶面、管芯104和互连球202的一部分为包封的模制复合材料。模制复合材料可为任何合适的包封剂,所述包封剂包括例如,填二氧化硅环氧膜塑料、塑料包封树脂和其它聚合材料(例如硅树脂、聚酰亚胺、酚醛树脂和聚氨脂)。可通过用于包封中的各种处理技术施加模制复合材料。例如,可使用膜辅助模制,借此空腔、凹部或沟槽304形成在包封剂中,留下未被模制材料覆盖的互连球202的顶部,因此暴露顶部。
例如,取决于封装布局和配置,沟槽304可被配置成各种形状,例如条带、L形、C形、矩形、正方形、其它正交和非正交形状。沟槽304大体上形成为连续形状或一组形状,并且沟槽304被配置成使得暴露的互连球202的导电表面可与插入件配对。在此实施例中,沟槽304形成为围绕管芯104的连续矩形或正方形形状。在此实施例中,互连球202的暴露的表面凹陷到包封剂302的顶面下方,使得当与插入件配对时,插入件的一部分向下延伸到沟槽304中。在此实施例中,如从基板102的顶面所测量的包封剂302的顶面的高度可为互连球202的高度的至少两倍。在一些实施例中,如从基板102的顶面所测量的包封剂302的顶面的高度可为互连球202的高度的至少1.2倍。
图4以简化的平面视图示出根据本公开的实施例的示例性插入件400。在正方形的内部中具有开口410的正方形配置中,插入件400被示为顶侧向上。插入件400包括基板402,基板402具有由信号管道以及互连或路由层形成的互连。第一互连层404的连接部位在基板402的顶侧周围分布。在剖面线A-A处截取插入件400的横截面视图。应理解,可独立形成或制造插入件400和可堆叠封装100中的每个。
图5以简化的横截面视图示出根据本公开的实施例的图4的示例性插入件。在示例性插入件400的剖面线A-A处截取图5的横截面视图。插入件400包括基板402,基板402具有包括信号管道406以及第一互连和第二互连或路由层404和路由层408的多层互连。插入件400可包括几个互连层。第一互连层404的连接部位分布在基板402的顶面处,并且第二互连层408的连接部位分布在基板402的底面处。连接部位或垫提供至插入件的互连层的电连接性的位置。
基板402可包括任何合适的多层基板,任何合适的多层基板由非导电材料,例如陶瓷或有机散装材料(例如,多层层压体印刷电路板(PCB)材料)形成。例如,取决于可堆叠封装100布局和配置,基板402可被配置成各种形状,例如条带、L形、C形、矩形、正方形、其它正交和非正交形状。可期望如在可堆叠封装100中配置的,基板402的配置补足沟槽304。
一般来说,基板402形成为一种形状且被配置成使得在插入件400的底面处的第二互连层408的连接部位可可堆叠封装100的暴露的互连球202的导电表面配对。在插入件400的顶面处的第一互连层404的连接部位被布置成使得封装的装置的导电表面可电耦合至插入件400。通过重新配置在插入件400的顶面处的第一互连层404的连接部位的布置,大量封装的装置可耦合至插入件400。
例如,信号管道406可通过任何合适的工艺,例如溅镀、沉积和电镀附接至基板402或形成在基板402中。例如,信号管道406允许从在第一互连层404处的基板402的顶面到第二互连层408的基板402的底面的信号传递。可由各种导电材料形成信号管道406,各种导电材料包括例如,铜、金、银、铝、镍、钨及其合金,以包括焊料、掺杂材料(例如,磷、硼掺杂的多晶硅)、超导材料和陶瓷(例如,氧化铜材料、铁基材料和其它合适的金属基材料)。也可取决于工艺由多于一种类型的材料形成信号管道304,以创建管道、组件和特定封装结构。
例如,互连层404和互连层408可由任何合适的导电材料(例如,铜、镍、铝及其合金)形成。互连层408的连接部位允许暴露的互连球202的导电表面与插入件400连接。例如,互连层408的连接部位可提供连接互连球、金扣柱、铜柱等等。
图6以简化的横截面视图示出根据本公开的实施例的与可堆叠封装100一起放置以形成示例性组件的插入件400。插入件被放置成使得在互连层408上的连接部位与暴露的互连球202的对应的导电表面对齐。
图7以简化的横截面视图示出根据本公开的实施例的用插入件400和可堆叠封装100形成的示例性组件700。插入件400被附接至可堆叠封装100,使互连层408的连接部位电耦合至暴露的互连球202的导电表面。当附接时,插入件400延伸到形成在可堆叠封装100的顶侧上的空腔中。例如,互连层408的连接部位和暴露的互连球202的导电表面可使用已知技术,例如焊料回流等等彼此粘在一起。
导电球连接器702形成在基板102的底面上,用于将可堆叠封装100连接至其它封装或其它部件,例如印刷电路板。球连接器702电耦合至基板102的互连层。在一个实施例中,球连接器702为焊料球。球连接器702也可被称作由一种或多种导电材料形成的球导体。球连接器702可由与图2中示出的互连球202类似的材料形成。在一些实施例中,球连接器702可由不同于互连球202的材料形成。在球连接器702的形成、安插和附接中可使用已知技术。在此实施例中,在插入件400附接至可堆叠封装100之后,球连接器702形成在基板102的底面上。在一些实施例中,在附接插入件400之前,球连接器702可形成在基板102的底面上。在可替换的实施例中,球连接器702和插入件400可在相同焊料回流步骤期间,同时附接至可堆叠封装100。
在图7中示出的示例性组件700中,可实现包括信号管道406、互连层404和互连层408连同互连球202和球连接器702的导电通路形成在插入件400的顶面处的第一互连层404的连接部位和在可堆叠封装300的底面处的球连接器702之间。基板102的互连或路由层(未示出)提供在管芯104和球连接器702之间以及在管芯104和第一互连层404的连接部位之间的导电通路。例如,这些导电通路允许从管芯104到在第一互连层404的连接部位处连接的封装的装置的信号传递。
图8以简化的横截面视图示出根据本公开的实施例的示例性层叠封装(POP)配置800。PoP配置800包括安裝至示例性组件700的示例性封装的装置802。
封装的装置802可包括适用于安装在PoP配置中的任何装置和/或分立部件。在此实施例中,示例性封装的装置802包括基板804、管芯806和包封剂812。例如,管芯806可包括数字电路、模拟电路、存储器、处理器、MEMS、传感器、电阻器、电感器、电容器、分立晶体管等等中的任一个,或数字电路、模拟电路、存储器、处理器、MEMS、传感器、电阻器、电感器、电容器、分立晶体管等等的组合。在此实施例中,管芯806借助于管芯附接材料808附接至基板804。键合线810将在管芯806的有源表面上的位置与在基板804的顶面处的位置电耦合。球连接器814形成在基板804的底面处,并且允许借助于基板互连(未示出)将信号电耦合至在基板804的顶侧上的位置。使用已知的技术和材料形成且安插球连接器814。球连接器814被布置在匹配组件700的互连层404的连接部位中的一个或多个连接部位的配置中。球连接器814和互连层404的连接部位可使用已知的技术和方法,例如焊料回流等等彼此粘在一起。本公开的实施例不限于在互连层404的连接部位处耦合封装的装置。例如,分立部件、散热片或护罩可焊接耦合至互连层404的连接部位。
在图8的示例性层叠封装(PoP)配置800中,可实现信号管道406、互连层404和互连层408连同互连球202以及球连接器702和球连接器814在封装的装置802和组件700之间形成导电通路。例如,这些导电通路可被用于使得实现在可堆叠封装300的管芯104和PoP安裝的封装的装置802的管芯806之间的电连接。
大体上,提供一种制造封装组件的方法,包括:将多个互连球附接至第一基板的第一表面;用包封剂包封第一基板的第一表面和多个互连球;在包封剂的第一表面中形成暴露互连球的一部分的沟槽,互连球的暴露的部分提供至安置在第一基板的第一表面处的第一导电层的电连接性;提供具有安置在第二基板的第一表面处的第一互连层的插入件;以及通过将第一互连层的连接部位附接至互连球的暴露的部分形成组件,第二基板的第一表面延伸到沟槽中。方法可另外包括将第一多个球连接器附接至第一基板的第二表面。包封可另外包括包封附接至第一基板的第一表面的半导体管芯。在倒装芯片配置中,半导体管芯可附接至第一基板的第一表面。沟槽可为至少部分围绕半导体管芯的连续沟槽。形成组件可另外包括与包封剂的第一表面相比,第二基板的第二表面被定位成距第一基板的第一表面更远。方法可另外包括将封装的装置附接至安置在第二基板的第二表面处的第二互连层的连接部位。封装的装置可在半导体管芯上方。可使用膜辅助模制技术形成沟槽。
在另一个实施例中,提供一种制造封装组件的方法,包括:提供具有第一表面的封装基板;将管芯附接至封装基板的第一表面;将多个互连球附接至封装基板的第一表面,多个互连球至少部分围绕管芯且电连接至管芯;用包封剂包封封装基板的第一表面、管芯和多个互连球;在包封剂的第一表面中形成暴露互连球的顶部的空腔,互连球的暴露的顶部提供至安置在封装基板的第一表面处的第一导电层的电连接性;提供具有安置在插入件基板的第一表面处的第一互连层的插入件;以及通过将第一互连层的连接部位附接至互连球的暴露的顶部形成组件,插入件基板的第一表面延伸到空腔中。方法可另外包括将第一多个球连接器附接至封装基板的第二表面。在倒装芯片配置中,半导体管芯可附接至封装基板的第一表面。形成空腔可形成暴露至少部分围绕管芯的互连球的顶部的连续空腔。形成组件可另外包括插入件基板的第二表面在包封剂的第一表面上方延伸。方法可另外包括将封装的装置附接至安置在插入件基板的第二表面处的第二互连层的连接部位。多个互连球可使用焊料回流工艺附接至封装基板的第一表面。
在又一个实施例中,提供一种封装组件,包括:第一封装,包括:具有第一表面的封装基板;附接至封装基板的第一表面的管芯;附接至封装基板的第一表面的多个互连球,多个互连球至少部分围绕管芯;具有顶面的包封剂,包封剂包封封装基板的第一表面、管芯和多个互连球;以及形成在包封剂的顶面中暴露互连球的顶部的沟槽,互连球的暴露的顶部;以及插入件,包括:具有顶面和底面的插入件基板,底面被放置在沟槽中且在包封剂的顶面下方;安置在插入件基板的顶面处的第一互连层;以及安置在插入件基板的底面处的第二互连层,第二互连层具有耦合至互连球的暴露的顶部的连接部位。封装组件可另外包括附接至封装基板的第二表面的第一多个球连接器。封装组件可另外包括附接至第一互连层的连接部位的第二封装。在倒装芯片配置中,管芯可附接至封装基板的第一表面。
到目前为止,应了解,已提供可堆叠封装和制造可堆叠封装的方法,可堆叠封装和制造可堆叠封装的方法使用重新配置的插入件并入嵌入式互连球,从而允许柔性层叠封装配置。所形成的沟槽暴露嵌入式互连球的顶部,从而提供各种插入件的附接。通过将插入件附接至可堆叠封装所形成的组件允许封装的装置被安裝在可堆叠封装上方。
在描述和权利要求书中的术语“前面”、“背面”、“顶部”、“底部”、“上方”、“在……下”等等(若有的话)用于描述性目的,且未必用于描述永久性相对位置。应理解,如此使用的术语在适当情况下可互换,使得本文中所描述的本发明的实施例例如能够以除本文中所示出或以其它方式描述的那些取向之外的其它取向操作。
虽然本文中参考具体实施例描述了本发明,但是在不脱离如所附权利要求书中所阐述的本发明的范围的情况下,可作出各种修改和改变。于是,本说明书和图应视为说明性的而不具是限制性意义,并且所有此类修改旨在包括在本发明的范围内。本文中关于具体实施例描述的任何益处、优点或针对问题的解决方案不旨在被解释为任何或所有权利要求的关键、必需或必要的特征或要素。
如本文中所使用的术语“耦合”不旨在限制于直接耦合或机械耦合。
此外,如本文中所使用的术语“一个(a/an)”被限定为一个或多于一个。再者,权利要求书中例如“至少一个”和“一个或多个”的介绍性短语的使用不应解释为暗示由不定冠词“一个(a/an)”所引导的另一权利要求要素将包含此类引导的权利要求要素的任何特定权利要求限于仅包含一个此类要素的发明,甚至当同一权利要求包括介绍性短语“一个或多个”或“至少一个”和例如“一个(a/an)”的不定冠词时。对于定冠词的使用也是如此。
除非另有陈述,否则例如“第一”和“第二”的术语用于任意地区别此类术语所描述的元件。因此,这些术语未必旨在指示此类要素的时间或其它优先次序。

Claims (10)

1.一种制造封装组件的方法,其特征在于,所述方法包括:
将多个互连球附接至第一基板的第一表面;
用包封剂包封所述第一基板的所述第一表面和所述多个互连球;
在所述包封剂的暴露所述互连球的一部分的第一表面中形成沟槽,所述互连球的暴露的部分为安置在所述第一基板的所述第一表面处的第一导电层提供电连接性;
提供具有安置在第二基板的第一表面处的第一互连层的插入件;以及
通过将所述第一互连层的连接部位附接至所述互连球的暴露的部分形成组件,所述第二基板的所述第一表面延伸到所述沟槽中。
2.根据权利要求1所述的方法,其特征在于,进一步包括将第一多个球连接器附接至所述第一基板的第二表面。
3.根据权利要求1所述的方法,其特征在于,包封进一步包括包封附接至所述第一基板的所述第一表面的半导体管芯。
4.根据权利要求3所述的方法,其特征在于,在倒装芯片配置中,所述半导体管芯被附接至所述第一基板的所述第一表面。
5.根据权利要求3所述的方法,其特征在于,所述沟槽为至少部分围绕所述半导体管芯的连续沟槽。
6.根据权利要求3所述的方法,其特征在于,形成组件进一步包括所述第二基板的第二表面,与所述包封剂的所述第一表面相比,所述第二基板的第二表面被定位成距第一基板的所述第一表面更远。
7.根据权利要求6所述的方法,其特征在于,进一步包括将封装的装置附接至安置在所述第二基板的所述第二表面处的第二互连层的连接部位。
8.根据权利要求1所述的方法,其特征在于,使用膜辅助模制技术形成所述沟槽。
9.一种制造封装组件的方法,其特征在于,所述方法包括:
提供具有第一表面的封装基板;
将管芯附接至所述封装基板的所述第一表面;
将多个互连球附接至所述封装基板的所述第一表面,所述多个互连球至少部分围绕所述管芯且电连接至所述管芯;
用包封剂包封所述封装基板的所述第一表面、管芯和多个互连球;
在所述包封剂的暴露所述互连球的顶部的第一表面中形成空腔,所述互连球的所述暴露的顶部为安置在所述封装基板的所述第一表面处的第一导电层提供电连接性;
提供具有安置在插入件基板的第一表面处的第一互连层的插入件;以及
通过将所述第一互连层的连接部位附接至所述互连球的暴露的顶部形成组件,所述插入件基板的所述第一表面延伸到所述空腔中。
10.一种封装组件,其特征在于,包括:
第一封装,包括:
具有第一表面的封装基板,
附接至所述封装基板的所述第一表面的管芯,
附接至所述封装基板的所述第一表面的多个互连球,所述多个互连球至少部分围绕所述管芯,
具有顶面的包封剂,所述包封剂包封所述封装基板的所述第一表面、管芯和多个互连球,以及
形成在所述包封剂的暴露所述互连球的顶部的所述顶面中的沟槽,所述互连球的所述暴露的顶部为安置在所述第一基板的所述第一表面处的第一导电层提供电连接性;以及
插入件,包括:
具有顶面和底面的插入件基板,所述底面被放置在所述沟槽中且在所述包封剂的所述顶面下方,
安置在所述插入件基板的所述顶面处的第一互连层,以及
安置在所述插入件基板的所述底面处的第二互连层,所述第二互连层具有耦合至所述互连球的所述暴露的顶部的连接部位。
CN201710701275.1A 2016-08-16 2017-08-16 可堆叠模制封装及其制造方法 Pending CN107768363A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/237,827 US20180053753A1 (en) 2016-08-16 2016-08-16 Stackable molded packages and methods of manufacture thereof
US15/237,827 2016-08-16

Publications (1)

Publication Number Publication Date
CN107768363A true CN107768363A (zh) 2018-03-06

Family

ID=61192168

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710701275.1A Pending CN107768363A (zh) 2016-08-16 2017-08-16 可堆叠模制封装及其制造方法

Country Status (2)

Country Link
US (1) US20180053753A1 (zh)
CN (1) CN107768363A (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019204841A (ja) * 2018-05-22 2019-11-28 株式会社村田製作所 半導体装置
US10825782B2 (en) * 2018-12-27 2020-11-03 Micron Technology, Inc. Semiconductor packages and associated methods with solder mask opening(s) for in-package ground and conformal coating contact
KR20210016119A (ko) 2019-07-31 2021-02-15 삼성전자주식회사 반도체 패키지
KR20220049975A (ko) 2020-10-15 2022-04-22 삼성전자주식회사 반도체 패키지
US11854837B2 (en) * 2021-04-22 2023-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of manufacturing

Family Cites Families (81)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0945805A (ja) * 1995-07-31 1997-02-14 Fujitsu Ltd 配線基板、半導体装置及び半導体装置を配線基板から取り外す方法並びに半導体装置の製造方法
US5696666A (en) * 1995-10-11 1997-12-09 Motorola, Inc. Low profile exposed die chip carrier package
US6069407A (en) * 1998-11-18 2000-05-30 Vlsi Technology, Inc. BGA package using PCB and tape in a die-up configuration
US6396136B2 (en) * 1998-12-31 2002-05-28 Texas Instruments Incorporated Ball grid package with multiple power/ground planes
US6495916B1 (en) * 1999-04-06 2002-12-17 Oki Electric Industry Co., Ltd. Resin-encapsulated semiconductor device
US6404043B1 (en) * 2000-06-21 2002-06-11 Dense-Pac Microsystems, Inc. Panel stacking of BGA devices to form three-dimensional modules
US6660945B2 (en) * 2001-10-16 2003-12-09 International Business Machines Corporation Interconnect structure and method of making same
US6906415B2 (en) * 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
TWI290757B (en) * 2002-12-30 2007-12-01 Advanced Semiconductor Eng Thermal enhance MCM package and the manufacturing method thereof
US7015571B2 (en) * 2003-11-12 2006-03-21 Advanced Semiconductor Engineering, Inc. Multi-chips module assembly package
US7345361B2 (en) * 2003-12-04 2008-03-18 Intel Corporation Stackable integrated circuit packaging
KR100652397B1 (ko) * 2005-01-17 2006-12-01 삼성전자주식회사 매개 인쇄회로기판을 사용하는 적층형 반도체 패키지
US7279786B2 (en) * 2005-02-04 2007-10-09 Stats Chippac Ltd. Nested integrated circuit package on package system
US8089143B2 (en) * 2005-02-10 2012-01-03 Stats Chippac Ltd. Integrated circuit package system using interposer
US7528474B2 (en) * 2005-05-31 2009-05-05 Stats Chippac Ltd. Stacked semiconductor package assembly having hollowed substrate
US20070141751A1 (en) * 2005-12-16 2007-06-21 Mistry Addi B Stackable molded packages and methods of making the same
US8058101B2 (en) * 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US20070216008A1 (en) * 2006-03-20 2007-09-20 Gerber Mark A Low profile semiconductor package-on-package
US7714453B2 (en) * 2006-05-12 2010-05-11 Broadcom Corporation Interconnect structure and formation for package stacking of molded plastic area array package
JP4901458B2 (ja) * 2006-12-26 2012-03-21 新光電気工業株式会社 電子部品内蔵基板
US7829990B1 (en) * 2007-01-18 2010-11-09 Amkor Technology, Inc. Stackable semiconductor package including laminate interposer
TWI335070B (en) * 2007-03-23 2010-12-21 Advanced Semiconductor Eng Semiconductor package and the method of making the same
US8409920B2 (en) * 2007-04-23 2013-04-02 Stats Chippac Ltd. Integrated circuit package system for package stacking and method of manufacture therefor
JP5280014B2 (ja) * 2007-04-27 2013-09-04 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法
US7635914B2 (en) * 2007-05-17 2009-12-22 Texas Instruments Incorporated Multi layer low cost cavity substrate fabrication for pop packages
US7687899B1 (en) * 2007-08-07 2010-03-30 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US20090127686A1 (en) * 2007-11-21 2009-05-21 Advanced Chip Engineering Technology Inc. Stacking die package structure for semiconductor devices and method of the same
US8247893B2 (en) * 2007-12-27 2012-08-21 Stats Chippac Ltd. Mountable integrated circuit package system with intra-stack encapsulation
US7859120B2 (en) * 2008-05-16 2010-12-28 Stats Chippac Ltd. Package system incorporating a flip-chip assembly
US8823160B2 (en) * 2008-08-22 2014-09-02 Stats Chippac Ltd. Integrated circuit package system having cavity
FR2939963B1 (fr) * 2008-12-11 2011-08-05 St Microelectronics Grenoble Procede de fabrication d'un support de composant semi-conducteur, support et dispositif semi-conducteur
US7851894B1 (en) * 2008-12-23 2010-12-14 Amkor Technology, Inc. System and method for shielding of package on package (PoP) assemblies
US8012797B2 (en) * 2009-01-07 2011-09-06 Advanced Semiconductor Engineering, Inc. Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
US8222538B1 (en) * 2009-06-12 2012-07-17 Amkor Technology, Inc. Stackable via package and method
US8034660B2 (en) * 2009-07-24 2011-10-11 Texas Instruments Incorporated PoP precursor with interposer for top package bond pad pitch compensation
US9875911B2 (en) * 2009-09-23 2018-01-23 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interposer with opening to contain semiconductor die
US8198131B2 (en) * 2009-11-18 2012-06-12 Advanced Semiconductor Engineering, Inc. Stackable semiconductor device packages
US8987896B2 (en) * 2009-12-16 2015-03-24 Intel Corporation High-density inter-package connections for ultra-thin package-on-package structures, and processes of forming same
TWI408785B (zh) * 2009-12-31 2013-09-11 Advanced Semiconductor Eng 半導體封裝結構
TWI419283B (zh) * 2010-02-10 2013-12-11 Advanced Semiconductor Eng 封裝結構
US8304296B2 (en) * 2010-06-23 2012-11-06 Stats Chippac Ltd. Semiconductor packaging system with multipart conductive pillars and method of manufacture thereof
KR20120020983A (ko) * 2010-08-31 2012-03-08 삼성전자주식회사 패키지 온 패키지
US8409922B2 (en) * 2010-09-14 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect
JP2012114173A (ja) * 2010-11-23 2012-06-14 Shinko Electric Ind Co Ltd 半導体装置の製造方法及び半導体装置
US20120159118A1 (en) * 2010-12-16 2012-06-21 Wong Shaw Fong Lower IC Package Structure for Coupling with an Upper IC Package to Form a Package-On-Package (PoP) Assembly and PoP Assembly Including Such a Lower IC Package Structure
US10204879B2 (en) * 2011-01-21 2019-02-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming wafer-level interconnect structures with advanced dielectric characteristics
KR101817159B1 (ko) * 2011-02-17 2018-02-22 삼성전자 주식회사 Tsv를 가지는 인터포저를 포함하는 반도체 패키지 및 그 제조 방법
US9171792B2 (en) * 2011-02-28 2015-10-27 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having a side-by-side device arrangement and stacking functionality
US8669137B2 (en) * 2011-04-01 2014-03-11 International Business Machines Corporation Copper post solder bumps on substrate
EP2745317A4 (en) * 2011-08-16 2015-08-12 Intel Corp OFFSET INTERPOSTERS FOR LARGE BOTTOM HOUSINGS AND LARGE CHIP STRUCTURES HOUSING ON HOUSING
KR20130075251A (ko) * 2011-12-27 2013-07-05 삼성전자주식회사 복수의 세그먼트로 구성된 인터포저를 포함하는 반도체 패키지
US9691636B2 (en) * 2012-02-02 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Interposer frame and method of manufacturing the same
US8766460B2 (en) * 2012-02-02 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Package with interposer frame and method of making the same
US9842798B2 (en) * 2012-03-23 2017-12-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a PoP device with embedded vertical interconnect units
US10049964B2 (en) * 2012-03-23 2018-08-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units
US9362197B2 (en) * 2012-11-02 2016-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Molded underfilling for package on package devices
US9287245B2 (en) * 2012-11-07 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Contoured package-on-package joint
US9799592B2 (en) * 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
US9165876B2 (en) * 2013-03-11 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure and methods for forming the same
US9484327B2 (en) * 2013-03-15 2016-11-01 Qualcomm Incorporated Package-on-package structure with reduced height
US8941225B2 (en) * 2013-04-18 2015-01-27 Sts Semiconductor & Telecommunications Co., Ltd. Integrated circuit package and method for manufacturing the same
US8951834B1 (en) * 2013-06-28 2015-02-10 Stats Chippac Ltd. Methods of forming solder balls in semiconductor packages
US9754870B2 (en) * 2013-07-10 2017-09-05 Kinsus Interconnect Technology Corp. Compound carrier board structure of flip-chip chip-scale package and manufacturing method thereof
US8883563B1 (en) * 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9252076B2 (en) * 2013-08-07 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
KR102245770B1 (ko) * 2013-10-29 2021-04-28 삼성전자주식회사 반도체 패키지 장치
KR20150049622A (ko) * 2013-10-30 2015-05-08 삼성전자주식회사 패키지 온 패키지 장치
US9472533B2 (en) * 2013-11-20 2016-10-18 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming wire bondable fan-out EWLB package
US9559064B2 (en) * 2013-12-04 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage control in package-on-package structures
JP6335513B2 (ja) * 2014-01-10 2018-05-30 新光電気工業株式会社 半導体装置、半導体装置の製造方法
US9570413B2 (en) * 2014-02-25 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with solder ball revealed through laser
TWI546932B (zh) * 2014-07-17 2016-08-21 矽品精密工業股份有限公司 半導體封裝件及其製法
US10319607B2 (en) * 2014-08-22 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure with organic interposer
JP2017503361A (ja) * 2014-12-16 2017-01-26 インテル コーポレイション スタック型電子装置を含む電子アセンブリ
US9859200B2 (en) * 2014-12-29 2018-01-02 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with interposer support structure mechanism and method of manufacture thereof
US20160225748A1 (en) * 2015-01-29 2016-08-04 Qualcomm Incorporated Package-on-package (pop) structure
KR101640341B1 (ko) * 2015-02-04 2016-07-15 앰코 테크놀로지 코리아 주식회사 반도체 패키지
US9478500B2 (en) * 2015-02-17 2016-10-25 Advanced Semiconductor Engineering, Inc. Interposer substrate, semiconductor structure and fabricating process thereof
TWI559419B (zh) * 2015-08-21 2016-11-21 力成科技股份有限公司 使用模封互連基板製程之柱頂互連(pti)型態半導體封裝構造及其製造方法
KR20170082677A (ko) * 2016-01-06 2017-07-17 에스케이하이닉스 주식회사 관통 몰드 커넥터를 포함하는 반도체 패키지 및 제조 방법
KR102420126B1 (ko) * 2016-02-01 2022-07-12 삼성전자주식회사 반도체 소자

Also Published As

Publication number Publication date
US20180053753A1 (en) 2018-02-22

Similar Documents

Publication Publication Date Title
CN107768363A (zh) 可堆叠模制封装及其制造方法
KR101895019B1 (ko) 영역 어레이 유닛 컨넥터를 갖는 적층 가능한 몰딩된 마이크로전자 패키지
CN104229720B (zh) 芯片布置及用于制造芯片布置的方法
CN102456584B (zh) 在半导体小片和互连结构周围形成可穿透膜包封料的半导体器件和方法
CN105637633B (zh) 具有预形成过孔的嵌入式封装
CN103367169B (zh) 超薄包埋模模块及其制造方法
CN109449141A (zh) 半导体封装
CN108091615A (zh) 半导体封装件
CN108352361A (zh) 用于干扰屏蔽的引线接合线
CN107093598A (zh) 包括天线的半导体装置
US20090127682A1 (en) Chip package structure and method of fabricating the same
US9281284B2 (en) System-in-packages having vertically-interconnected leaded components and methods for the fabrication thereof
TW201703210A (zh) 半導體封裝及其製造方法
EP3147942B1 (en) Semiconductor package, semiconductor device using the same and manufacturing method thereof
TW544876B (en) Semiconductor device and process for fabricating the same
CN110010553A (zh) 形成超高密度嵌入式半导体管芯封装的半导体器件和方法
TW201301460A (zh) 一種封裝結構及其製造方法
CN110534506A (zh) 半导体器件层叠封装件、半导体器件封装件及其制造方法
KR100991623B1 (ko) 반도체 디바이스 및 그 제조 방법
CN107622996A (zh) 三维高密度扇出型封装结构及其制造方法
TW201803053A (zh) 扇出型多晶片堆疊封裝之電子裝置及形成該裝置之方法
CN206293435U (zh) 半导体器件与半导体封装件
CN109216310A (zh) 半导体封装装置及其制造方法
CN108630626A (zh) 无基板封装结构
CN107452635B (zh) 半导体装置封装和其制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20180306

WD01 Invention patent application deemed withdrawn after publication